trends in vlsi design : methodologies and cad...

Trends in VLSI Design :

Methodologies and CAD Tools

Presenter : Raj Singh

IC Design GroupCEERIPilani – 333 031

Tel : 01596-242359

Fax : 01596-242294

Email : [email protected]

View of VLSI Design

View of VLSI Design

Algorithm

Technology

CAD Tools

Architecture

c©CEERI, Pilani IC Design Group 1

VLSI Design Complexity Issues

VLSI Design : Problem Domain Complexity

• Competing or contradictory requirements (speed, power, area).

• Application area specialization and knowledge.

• Changing/evolving specifications.



VLSI Design : Design/Development Process Complexity

• Rapidly changing technology.

• Large task requiring multi-disciplinary team.

• Large design space.

• Short design cycle.



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VLSI Design : Design/Development Process Complexity

• First-time success requirement.

• Multiple views/representations each with different characterization.

• Inadequate documentation.



VLSI Design : Complexity Due to Many Choices

• Many technologies/implementation choices (NMOS, CMOS, . . . )

• Many methodologies (FPGA, Semi-custom, Full custom, ASIC, . . . )

• Many logic forms (Dynamic, 2-phase, 4-phase, Static, . . . )

• Combinatorial explosion as one goes down in abstraction level.

• Many possible partitions at each level.



VLSI Design : Other Complexities

• Clocking and Timing issues.

• Concurrency of hardware operations.

• Testing-related issues.

• Packaging-related issues.


VLSI Design Process Overview

Synthesis and Analysis

VLSI design activity is

Synthesis and then Analysis

at several successive levels of design abstraction.

Synthesis Phase : Proposing a solution of the design problem at a certainlevel of abstraction.

Analysis Phase : Checking that solution for its validity as well as its con-sistency with some other design representation (usually at a different level ofabstraction) and the characterization/evaluation of the design solution.



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At each level of design abstraction, synthesis and analysis may be used in aloop (iterative procedure) to arrive at an optimal solution.

Synthesis involves creativity and new concepts.

Analysis (except when developing new methods of analysis) involves applyingknown methods for checking the design and processing of large data usingknown/standard methods.

Thus, synthesis has traditionally been the prerogative of humans, while anal-ysis has traditionally been the first task to have been handed over to the com-puters via creation of CAD tools.



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Synthesis tools are created when the synthesis process can be expressedas a method.

Analysis tools also improve as a result of human creativity and exploration.

Therefore, the division of labour in VLSI design is clear :

Humans do the creative parts and computers (CAD tools) do the cumber-some detailed work.



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. . .

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. . .

Top Level of Abstraction

Lower Level of Abstraction

Lowest Level of Abstraction

More Abstract Level

Synthesis

(Check)

Analysis

(Consistency)

Less Abstract Level


Traditional VLSI Design Flow

Traditional VLSI Design Flow

Design VerificationDesign Entry /

OK ?

Design Output

Design Entry /

Design Output

Yes

No

No

Yes

OK ?No

Yes Design Output

OK ?No

Yes Design Output

OK ?No

Yes Design Output

Specification From User

OK ?

Design VerificationThrough Simulation

Design Synthesis

Design Synthesis

Design SynthesisDesign Entry /

Transistor/Circuit Level

Layout/Physical Level

Design Entry /Design Synthesis


Logic/Gate Level



Design Entry /Design Synthesis

Register−Transfer Level

Through Simulation

Behavioural Level


HDL-Based Design Flow

HDL-Based Design Flow

Code Organization Choice

Architectural Choice

Logic Implementation Choice

Placement and Routing Choice

Behavioral Description in HDL

RT−Level Description in HDL

Physical Design

Specifications + Constraints

Gate−Level Netlist


VLSI Design Methodologies


Systematic design methods (called design methodologies) are necessary forsuccessfully designing complex digital hardware.

Different design methodologies differ in their choice of number and levels ofdesign abstractions used during the design process and the manner of con-straints on the translations between the abstraction levels.

These constraints are usually in the form of use of a particular structure typeat the lower level of design abstraction while translating the design descriptionthat exists at a higher level of abstraction.



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For example, while translating from the logic level abstraction to physical level,popular design methodologies are :

1. FPGA.

2. Gate-Array.

3. Standard-Cell.

4. Full-Custom.



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The popular methodologies for implementing the control part are :

1. Hardwired Control.

2. Microcoded ROM-based Control.

3. PLA-based Control.


Design-CAD-Foundry Interfaces

Design-CAD-Foundry Interfaces

Fabricated Design

CAD ToolsBack−end

CAD ToolsFront−end

Proprietary Design Tools

and Libraries

Design for Fabrication

Vendor

Foundry

CAD Tools

DesignCenter Users

Chip


CAD Tools

CAD Tools : Reducing Risk of Failure

• Simulate performance before fabrication. (simulation)

• Explore various alternatives and characterize them in terms of cost, per-formance, ... (design space exploration)

• Check against all possible known fabrication process violations beforedata is given to manufacturing. (design sign-off)

CAD tools help discover problems so that they can be correcte d at min-imal cost, both in terms time and resources. (catch errors as early aspossible)c©CEERI, Pilani IC Design Group 17

Design Methodologies and CAD Tools

CAD Tools at Various Levels of Design Hierarchy

Design Entry (HDL)

Design Entry (C, C++, ...)

Design Entry (HDL)

Design Entry (Schematic)

Specification From User

Behavioural Simulation

Behavioural Level

Behavioural Synthesis

RTL Simulation

Analysis

Synthesis

Synthesis

Logic Simulation, LVL,

Static Timing Analysis, ERC

AnalysisSynthesis

Design Entry (HDL)Design Entry (Schematic)DFT Insertion, ATPG

Logic Synthesis

Register−Transfer Level

Logic/Gate Level

Circuit Synthesis

Design Entry (Schematic)

Design Entry (SPICE)

Circuit Simulation,Power Analysis,Delay Estimation

Transistor/Circuit Level

AnalysisSynthesis

Layout/Physical Level

LVS, DRC,

Circuit Extraction

AnalysisSynthesis

Design Entry (Layout),Floor Plan,Place−and−Route

Flash Analysis

AnalysisSynthesis

PG File Creation

Fracturing, Sorting,

Process Simulation, Lithography Simulation

Analysis

Logic Optimization

Layout Synthesis

Mask Level

FoundryYield Prediction, Tester File Creation



VLSI Design and CAD Tools

System Design and Behavioral Design

Layout Design

STRUCTURALDOMAIN

BEHAVIORALDOMAIN

DOMAINPHYSICAL

System Structure

Processors, Buses

RAM, Registers, ALUs

Gates, Flip−flops

Transistors

Transistor Layouts

Cell Layouts

Block Layouts

Chips, Floorplans

Boards, MCM, System Partitions

Transistor Functions

Boolean Expressions

Register Transfers

Flow charts, Algorithms

System Behavior

RTL Design andLogic Design

Transistor Design

Cell Design



CAD Tools Classification : Interaction-Based

Front-end Tools :

Design Entry, Editors, Simulation, Synthesis, Timing Analysis, DFT Insertion,Test Generation, . . .

Back-end Tools :

Floor Planning, Place-and-Route, Extraction, LVS (Layout vs. Schematic), LVL(Layout vs. Logic), ERC, DRC, Pattern Generators, Format Converters, MaskGraphics, . . .



CAD Tools Classification : Function-Based

Design Capture Tools :

Editors, VHDL, SystemVerilog, SystemC, State Charts, FSM Capture, . . .

Synthesis Tools :

Behavioral Synthesis, RTL Synthesis, FPGA Synthesis, Logic Synthesis, Phys-ical Synthesis, Module/Cell Generators (ROM, PLA, RAM), Data-path Com-piler, Adder/Multiplier Generators, DSP Synthesis, . . .



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CAD Tools Classification : Function-Based

Analysis Tools :

• Checkers : DRC, ERC, Net Compare, Ratio Checker, Short-circuit Checker,Fan-in / Fan-out Checker, Power Checker, . . .

• Verifiers : Timing Verifier, Simulators, ICE/Hardware Simulators, FormalVerifier, . . .

Testing Related Tools :

ATPG, DFT Tools, . . .


Trends in Design Methodologies and CAD Tools

Design Methodologies and CAD Tools : First Epoch (1959-1979 )

Full-custom design methodology.

Layout level tools , Circuit level tools.

Technology at SSI, MSI, LSI levels.

Designer, User and Tools Developer — all at a single company (monolithic).

Productivity of designer (notionally) = 10 transistors/da y.



Design Methodologies and CAD Tools : Second Epoch (1980-198 9)

Standard-Cell / Gate-Array / ASIC design methodology. Shorter synthe-sis/analysis loop.

Logic level tools , Macro generators, Module compilers.

Technology at LSI, VLSI levels.

User/Designer separated from Tools Developer i.e. separate companies sellingtools come into being.

Productivity of designer (notionally) = 10 gates/day.



Design Methodologies and CAD Tools : Third Epoch (1990-1999 )

HDL-based design methodology. FPGA-based prototyping. Design explo-ration made easier, Estimators for performance become available.

RT-level synthesis , Preliminary Behavioural synthesis tools; HDL-based de-sign entry, HDL Code analyzers/advisers.

Technology at VLSI levels. Deep-submicron (DSM) issues.

User, Designer and Tools Developer become separate groups/companies. Fa-bless companies.

CAD tools move towards PC platforms.

Productivity of designer (notionally) = 10 lines of VHDL code/day.c©CEERI, Pilani IC Design Group 25


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Design Methodologies and CAD Tools : Third Epoch (1990-1999 )

Low-power gains importance. Mixed-signal design issues.

Tools for designing MEMS and Embedded systems appear.

Intellectual Property, Design Re-use, Reconfigurable Computing, Cores, ASIP,ASSP, DSP, . . .



Design Methodologies and CAD Tools : Fourth Epoch (2000-. . . )

System-on-Chip design methodology. Block-level chip design (using cores,IP blocks).

System-level synthesis , MEMS design tools. Mixed-signal design tools.

Consolidation among EDA companies.

Technology at VLSI, ULSI levels. Deep-submicron (DSM) and power-leakageissues. Copper metallization, new dielectric materials, new device structures.

Productivity of designer (notionally) = 10 lines of specific ation code/day.

RF IC Design, Hardware-Software Codesign, Web-based CAD tools and de-sign environment.

Methodology and Tools for Non-Silicon based Designs ? Nano-technology ?


Trends : Codesign and Embedded Systems

What is Hardware-Software Codesign ?

Integrated design of electronic systems implemented using hardware and soft-ware components developed concurrently and cooperatively.

It is a part of the system-level design which may consist of mechanical, elec-trical or chemical parts in addition to electronics.



Advantages of Hardware-Software Systems

• Family of products on a common hardware platform.

• Upgradation and efficient evolution path of product through updating soft-ware.

• Chip/circuit’s high cost reduced by providing functionality in software.

• Range of system costs and performances – from (high cost + high perfor-mance) to (low cost + low performance).

Embedded core, ASIC/FPGA, Microprocessor + Software, . . .



Application Areas

• Large systems e.g. Aircraft, Telecommunication.

• Computing systems e.g. Supercomputer, Workstation, PC.

• Strategic/Defence systems e.g. Radar, Missile.

• Embedded systems.

– Control e.g. automobile, medical, industrial.

– Hand-held e.g. cellular phone, PDA.



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Application Areas

– Consumer e.g. microwave oven, washing machine.

– Music systems e.g. MP3 players, M4a players, Ogg players.

– Sound recording e.g. phone-answering machine.

– Speech processing e.g. voice synthesis.

– Graphics processing e.g. laser printer, X-terminal.

– Video processing e.g. VCD, DVD, Digital TV, HDTV.

– Robotics and Mechatronics.



Typical Embedded System Architecture

INPUT(S)OUTPUT(S)

SensorsActuators

Processor

Memory

ASIC

GlueLogic



Embedded System Design Steps

• System-level Modeling and Simulation.

• Hardware-Software Partitioning.

• Concurrently,

– Hardware Synthesis.

– Interface Synthesis.

– Software Code Generation.



Embedded System Codesign Environment

System Model

Partitioning

INTERFACE

Netlist Netlist ? Code

CO−SIMULATION

Optimization

TranslatorSynthesis ?Synthesis

SOFTWAREHARDWARE

uP, uC, DSP, ...ROM, Glue LogicFPGA, ASIC, ...


Trends : Reconfigurable Computing

What is Reconfigurable Computing ?

Reconfigurable Computing is an approach that allows reconfigurable aspectsof hardware (e.g. FPGAs) to be as flexible as software.

It can be implemented either statically (configure and then repeatedly execute)or dynamically (repeatedly configure-and-execute).

It requires extensive kowledge base and quantitative approach for evaluat-ing different system architectural options vis-a-vis the system requirements(in terms of speed, power, cost, user-interface, configurability, . . . ).



Why Reconfigurable Computing ?

• Reduced time-to-market.

• Cheaper than ASICs or processors.

• More application specific adaptation than processors.

• Lower system life-time cost and upgradeable in the field.



Types of Reconfigurable Computing

• Processor + FPGA (Embedded Systems).

• Reconfigurable Compiler.

• Rapid Prototyping.

• Hardware Accelerator; Hardware Emulator.


Conclusion

Conclusion

• VLSI Design is a complex task.

• Design methodologies and CAD tools are important partners of the VLSIdesigner in overcoming this complexity.

• CAD tools free the VLSI designer from easy-to-do tasks and allow thedesigner to concentrate on creative tasks.

• Design methodologies and CAD tools evolve based on designer’s needs.


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