two day fdp on asic physical design using cadence first encounter
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7/24/2019 Two Day FDP on ASIC Physical Design Using Cadence First Encounter
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A Two day Faculty Development Program
ASIC Physical Design using Cadence First Encounter
Shastra Micro Systemswww.shastramicro.com
Motivation:
Empowering electronics back ground engineers with concepts and practical knowledge on Chip
design. Mostly focused on providing hands on experience on SoC back end design using one of world top
physical design tool [Cadence First Encounter]. Attending the event would provide overall knowledge of
chip design with specialized and practical skill set on Physical Design.
Agenda:
Day1:
Morning session: [Theory session]
ASIC Design flow
Analog, Digital & Mixed signal flows
Front End (Logic) Design
Back End (Physical) design
Verification Vs Testing
Design For Testability
Design For Manufacturability
Introduction to Sign off analysis [STA/IR Drop/SI/Noise/EM]
ASIC Physical Design
Inputs to Physical Design [Hands on]
Afternoon session: [50% Theory50% Practical]
Floor planning [Hands on]
Introduction to Cadence First Encounter (FE) tool [Hands on]
Loading db into FE [Hands on]
Floor planning using FE [Hands on]
Floor planning experiments [Hands on]
Blockages [Hands on]
Power Planning
Power planning using Cadence FE [Hands on]
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7/24/2019 Two Day FDP on ASIC Physical Design Using Cadence First Encounter
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Day2:
Morning session: [25% theory75% practical]
Placement
Placement using cadence FE [Hands on]
Congestion analysis
Congestion analysis using Cadence FE [Hands on]
Setup timing analysis
Setup timing analysis using Cadence FE [Hands on]
Other QOR checks after placement
Clock Tree Synthesis (CTS)
CTS using Cadence FE [Hands on session]
Power analysis [Static (Active/Leakage) & Dynamic]
Power Analysis using Cadence FE [Hands on session]
Hold timing analysis
Hold timing analysis using cadence FE. [Hands on session]
Other QOR checks after CTS
Afternoon session: [25% theory75% practical]
Routing
Routing using cadence FE [Hands on session]
Physical verification [DRC/LVS]
Physical verification and fixing using Cadence FE [Hands on session]
Transition, capacitance analysis.
Transition, capacitance fixing using Cadence FE [Hand on session]
Introduction to ECOs [Hands on session]
Research scope.
Lab requirements:
1)
Cadence First Encounter installed in PCs with 2 participants : 1 PC ratio
2)
All the PCs with Linux OS [Of course cadence FE is installed on only linux/solaries]
3)
Class setup (Projector/board) in the lab. (All the theory + Practical sessions will run parallel in
the lab)
Eligible attendees:
Faculty with back ground knowledge of Digital Design, EDC & Network theory.
Should be good at UNIX / Linux OS usage.
TCL scripting knowledge is an added advantage.
For more details mail us: [email protected] | Web:www.shastramicro.com
Follow us: www.facebook.com/shastra.micro| www.linkedin.com/company/shastra-micro-systems
Call us : 040-666 66 883 / 884
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