ucsd vlsicad laboratory 1 si for free: machine learning of interconnect coupling delay and...
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UCSD VLSICAD Laboratory 1
SI for Free: Machine Learning of Interconnect Coupling Delay and
Transition Effects
Andrew B. Kahng‡†, Mulong Luo†, Siddhartha Nath†
‡† ECE and †CSE Departments, UC San Diego{abk, muluo, sinath}@ucsd.edu
UCSD VLSICAD Laboratory 2
Outline
• Motivation• Previous Work• Our Methodology and Accuracy Results• Design of Experiments and Robustness Results• Conclusions
UCSD VLSICAD Laboratory 3
Non-SI to SI Calibration Use Case
SI Timing Report
Calibration: Recipe to Convert Non-SI Timing Report to SI Timing Report
Non-SI Timing Report
.sdc
.v
Save costSave runtimeBut still accurate
.db, .lib .spef .v .sdc
Post P & R Database
Non-SI Timing ReportNon-SI Timing Report
SI Timing ReportSI Timing Report
UCSD VLSICAD Laboratory 4
Non-SI vs. SI: How Bad is the Divergence?• Slack diverges by 81ps (clock period = 1.0ns) • 81ps is ~4 stages of logic at 28nm FDSOI
81ps
Path slack in SI Mode (ns)
Path
Sla
ck in
Non
-SI M
ode
(ns) Ideal correlation
UCSD VLSICAD Laboratory 5
Non-SI to SI Calibration is Difficult!
• Multiple electrical, logic structure and layout parameters
• Complex interactions between parameters• Black-box code in STA tools
Electrical parameters
Logic structure parameters
Layout parameters
SI Timing reports:Incr delay
Transition timePath delay
Commercial STA tools
UCSD VLSICAD Laboratory 6
Example Challenge: Clock Period Dependency
• ∆path slack is 81ps at signoff clock period of 1.0ns• Tightening clock period to 0.82ns changes ∆path
slack to 143ps!
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Clock period (ns)
Max
Del
ta P
ath
Slac
k (S
I – n
on-S
I) (n
s)
81ps at signoff clock period
143ps at tighter clock period
UCSD VLSICAD Laboratory 7
Example Challenge: Ground Capacitance Dependency
• Incremental transition time (DTran) increases but incremental delay (SI Incr Delay) due to SI decreases
• This anti-correlation is non-obvious!
0.004 0.005 0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.0140
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0.16
DTranSI Incr DelayNon-SI Incr Delay
Ground Capacitance (pF)
Arc
Tim
ing
(ns)
14ps
15ps
UCSD VLSICAD Laboratory 8
Our Contributions
• Identify multiple sources of timing divergence between non-SI and SI modes
• Provide new insights in terms of modeling parameters required to calibrate non-SI to SI timing
• Develop new models to calibrate non-SI to SI timing using machine learning-based techniques
• Demonstrate accuracy and robustness of our models on a variety of testcases• Worst-case divergence of 5.2ps in incremental delay due to
SI• Worst-case divergence of 8.2ps in SI-aware path delay
UCSD VLSICAD Laboratory 9
Outline
• Motivation• Previous Work• Our Methodology and Accuracy Results• Design of Experiments and Robustness Results• Conclusions
UCSD VLSICAD Laboratory 10
Review of Previous Works• Analytical SI-induced delay models
• Sapatnekar2000• Lumps coupling capacitance to ground capacitance using Miller coupling factors• Uses an iterative algorithm to estimate crosstalk delay on nets
• Xiao2000• Derive a two-pole model for crosstalk noise computation using iterative Newton-
Raphson method
• Correlation of STA tools• Thiel2004
• Correlate SPICE to PT timing reports
• Kahng2013• Propose an offset-based correlation and wire delay estimation using linear
regression to calibrate path slacks with PT
• Han2014• Develop machine learning models to correlate SI to SI and non-SI to non-SI timing
between STA tools, and STA and design implementation tools
UCSD VLSICAD Laboratory 11
Miscorrelations of Han2014• Calibrate non-SI to non-SI or SI to SI
• Signoff timer to signoff timer• Signoff timer to IC implementation tools
• Divergence of 60ps when trying to calibrate non-SI to SI
Actual Incremental Delay in SI Mode (ps)
Pred
icte
d In
crem
enta
l Del
ay in
SI
Mod
e us
ing
non-
SI M
ode
Info
rmati
on
(ps)
60ps
Ideal correlation
We need new models to calibrate SI from non-SI!
UCSD VLSICAD Laboratory 12
Outline
• Motivation• Previous Work• Our Methodology and Accuracy Results• Design of Experiments and Robustness Results• Conclusions
UCSD VLSICAD Laboratory 13
Identifying Modeling Parameters
• Need to consider new electrical parameters
• Rw is the resistance of an arc
• Cc is the coupling capacitance of an arc
• LE is the logic effort of a driver
• Thus, RW, Cc, LE have great impacts on timing, we identify them as parameters for incremental delay in SI mode
Rw x Cc
Incr
emen
tal D
elay
in S
I Mod
e (n
s)
LEIn
crem
enta
l Del
ay in
SI M
ode
(ns)
UCSD VLSICAD Laboratory 14
List of Modeling Parameters
Incremental transition time
due to SI
Incremental delay due to SI
SI-aware path delay
Modeling Parameters Type SourceTransition time in non-SI mode Electrical Non-SI timing reportsResistance of an arc Electrical SPEFCoupling cap of an arc Electrical, layout SPEFRatio of coupling to total capacitance Electrical, layout SPEFLogical effort of driver Electrical SPEF, LibertyRatio of arc’s stage to total # stages Logic structure Non-SI timing reportsClock period Constraint SDC{Min, max} x {rise, fall} delta arrival times between the worst aggressor and victim
Electrical Non-SI timing reports
Toggle rate of victim net Operational, logic structure Non-SI timing reportsPath delay in non-SI mode Electrical Non-SI timing reports
Electrical, logic structure, and layout parameters and constraint
Several new electrical, logic structure, layout parameters
UCSD VLSICAD Laboratory 15
Comparison between Models
• Han2014 models have worst-case path delay error of 87.3ps vs. 8.2ps error from our models
Actual Path Delay (ps)
Pred
icte
d Pa
th D
elay
(ps)
87.3ps
Ideal correlation
Actual Path Delay (ps)Pr
edic
ted
Path
Del
ay (p
s)
8.2ps
Ideal correlation
UCSD VLSICAD Laboratory 16
Modeling FlowTiming Reports
in SI ModeTiming Reports in
Non-SI Mode
Create Training, Validation and Testing Sets
ANN (2 Hidden Layers, 5-Fold Cross-Validation)
Save Model and Exit
SVM (RBF Kernel, 5-Fold Cross-Validation)
HSM(Weighted Predictions from ANN and SVM)
• Linear regression cannot capture complex interactions between parameters
• Non-linear techniques capture these interactions using hidden parameters
UCSD VLSICAD Laboratory 17
Incremental Transition Time (Due to SI) Model
• Incremental Transition Time (Due to SI): Transition Time considering SI – Transition Time w/o SI
• We use six modeling parameters
∆ 𝑇𝑠𝑖= 𝑓 (𝑇 𝑠𝑖 ′ ,𝑅𝑤 ,𝐶𝑐 ,𝑟𝐶𝑐 ,𝐶𝑡𝑜𝑡 ,𝑐𝑙𝑘𝑝 ,𝐿𝐸 )
Meaning
Incremental transition time of an arc due to SI
Transition time of an arc in non-SI mode
Resistance of an arc
Coupling capacitance of an arc
Ratio of coupling to total capacitance
Clock period
Logical effort of the driver of the net
UCSD VLSICAD Laboratory 18
Accuracy of Incremental Transition Time Prediction
• Worst-case absolute error of 7.0ps (8.8%)• Range of errors is 11.3ps• Average absolute error of 0.7ps (0.6%)
Actual Incremental Transition Time (ps)
Pred
icte
d In
crem
enta
l Tra
nsiti
on T
ime
(ps)
7.0ps
Ideal correlation
UCSD VLSICAD Laboratory 19
Incremental Delay (Due to SI) Model
• Incremental Delay (Due to SI): Delay considering SI – Delay w/o SI• We use 11 modeling parameters
∆𝐷𝑠𝑖= 𝑓 (𝐷𝑠𝑖 ′ ,∆𝑇 𝑠𝑖 ,𝑅𝑤 ,𝐶𝑐 ,𝑟𝐶𝑐 ,𝐶𝑡𝑜𝑡 ,𝑟𝑆 ,𝑁𝑠𝑡𝑔 ,𝑐𝑙𝑘𝑝 , ∆𝑎𝑟𝑟𝑚𝑖𝑛 ,(𝑟 , 𝑓 ) ,∆𝑎𝑟𝑟𝑚𝑎𝑥 ,(𝑟 , 𝑓 ) , 𝐴𝑟 ,𝐿𝐸 )
Meaning
Incremental delay of an arc due to SI
Incremental delay of an arc in non-SI mode
Incremental transition time of an arc due to SI (predicted)
Resistance of an arc
Coupling capacitance of an arc
Ratio of coupling to total capacitance
Ratio of arc’s stage to total # stages
Clock period
Delta of min (rise, fall) arrival time between aggressor and victim
Delta of max (rise, fall) arrival time between aggressor and victim
Toggle rate of net
Logical effort of the driver of the net
UCSD VLSICAD Laboratory 20
Accuracy of Incremental Delay Prediction
• Worst-case absolute error of 5.2ps (15.7%)• Range of errors is 9.8ps• Average absolute error of 1.2ps (1.1%)
Actual SI Incr Delay (ps)
Pred
icte
d SI
Incr
Del
ay (p
s)
5.2ps
Ideal correlation
UCSD VLSICAD Laboratory 21
SI-Aware Path Delay Model
• We use three modeling parameters
∆ 𝑃 𝑠𝑖= 𝑓 (𝑃𝑠𝑖 ′ ,∑𝑖=1
𝑁 𝑠𝑡𝑔
∆𝐷𝑠𝑖 ,𝑁 𝑠𝑡𝑔)Meaning
Difference in path delays in SI and non-SI modes
Non-SI path delay across all timing arcs
Sum of incremental delay due to SI (predicted) across all stages in a pathNumber of stages in a timing path
UCSD VLSICAD Laboratory 22
Accuracy of Path Delay Prediction
• Worst-case absolute error of 8.2ps (6.9%)• Average absolute error of 1.7ps (1.4%)
Actual Path Delay (ps)
Pred
icte
d Pa
th D
elay
(ps)
8.2ps
Ideal correlation
UCSD VLSICAD Laboratory 23
Outline
• Motivation• Previous Work• Our Methodology and Accuracy Results• Design of Experiments and Robustness Results• Conclusions
UCSD VLSICAD Laboratory 24
Testcases• We use real open-source designs and artificial testcases• Technology: 28nm foundry FDSOI• Total data points: 188K
Testcase Type Testcase Name Source Signoff Clock Period (ns)
#Instances at Post-Synthesis
CPU OST2 (1-core) Oracle (formerly, Sun)
2.2 350K
GPU THEIA OpenCores 2.0 125K
Modem Viterbi OpenCores 1.0 97K
Encoder JPEG OpenCores 0.8 62K
Crypto AES OpenCores 1.0 13K
Stack FIFO Designware 0.75 6.5K
Artificial ART UCSD 1.0 >= 100
UCSD VLSICAD Laboratory 25
Artificial Testcases
• Clock periods: tight (-200ps less than signoff period) and loose (200ps more than signoff period)
• #Stages in artificial testcase: {15, 20, 25, 30}• Miller coupling factor (MCF): {2, 1, 0}• RC scaling factors: {0.5, 1.0, 2.0}• Driver sizes in artificial: {X6, X16, X24, X32}
UCSD VLSICAD Laboratory 26
STA Tool Flows
• Read databases of timing libraries• Read and link design (post-P&R netlist)• Read constraints (.sdc) and parasitics (.spef)• In non-SI mode, use MCF to add coupling cap to
ground cap• In SI mode, set flags to not reselect critical path for
SI analysis, select clock nets and delay analysis mode as edge-aligned
• Perform path-based timing analysis of top-1K paths• Obtain detailed timing reports
UCSD VLSICAD Laboratory 27
Robustness of Models
• New implementation of JPEG has different clock period, #stages, utilization
• Worst-case absolute error of 7.9ps (12.3%)• Average absolute error of 1.6ps (2.6%)
Actual SI Incr Delay (ps)
Pred
icte
d SI
Incr
Del
ay (p
s)
7.9ps
Ideal correlation
UCSD VLSICAD Laboratory 28
Outline
• Motivation• Previous Work• Our Methodology and Accuracy Results• Design of Experiments and Robustness Results• Conclusions
UCSD VLSICAD Laboratory 29
Conclusions• Calibration of non-SI to SI enables cost and runtime savings for SoC
design teams• We analyze electrical, logic structure and layout parameters that cause
timing divergence between non-SI and SI modes• We develop machine learning-based models to accurately calibrate
non-SI to SI timing• Our models have a worst-case error of 8.2ps Si-aware path delay in a
28nm foundry FDSOI technology• Ongoing
• Correlate graph-based and path-based timing analysis• Integrate our models with an academic timer
THANK YOU!!!Our thanks to Dr. Tuck-Boon Chan of Qualcomm Inc. and Ms. Nancy MacDonald of Broadcom Corp.
UCSD VLSICAD Laboratory 30
BACKUP
UCSD VLSICAD Laboratory 31
Han2014 Modeling Parameters
• Transition Time
• Wire delay
• wire delay• cell output transition time • wire resistance• , , , wire, effective, coupling capacitance
UCSD VLSICAD Laboratory 32
Why Bother About SI vs. Non-SI Calibration?
• Calibration: Conversion of a Non-SI timing report to SI timing report
• Many tools perform static timing analysis (STA) in both signal integrity (SI) mode and non-SI mode
• Cost differences• STA tool with SI mode: expensive• STA tool without SI mode: cheap
• Runtime differences• For a design with 110K instances, exhaustive path-based analysis
runtime of SI is 3 the runtime of non-SI
• Question: Should design team buy SI licenses or cheaper non-SI licenses?
Can we calibrate SI to non-SI to
reduce cost and
runtime?