Microelectronics Journal 42 (2011) 358–364

Contents lists available at ScienceDirect

Microelectronics Journal

0026-26

doi:10.1

n Corr

E-m

journal homepage: www.elsevier.com/locate/mejo

Ultra low power phase detector and phase-locked loop designs and theirapplication as a receiver

Bo Li a, Yiming Zhai a, Bo Yang a, Thomas Salter a,b, Martin Peckerar a, Neil Goldsman a,n

a Department of Electrical and Computer Engineering, University of Maryland, College Park, MD 20742, USAb Laboratory for Physical Sciences, College Park, MD 20740, USA

a r t i c l e i n f o

Article history:

Received 11 June 2010

Received in revised form

11 October 2010

Accepted 13 October 2010Available online 20 November 2010

Keywords:

Low power mixer

Phase detector

Ring oscillator

VCO

Phase-locked loops (PLL)

Frequency-modulation (FM) receiver

Frequency-shift keying (FSK)

92/$ - see front matter & 2010 Elsevier Ltd. A

016/j.mejo.2010.10.010

esponding author. Tel.: +1 301 405 3648.

ail address: neil@umd.edu (N. Goldsman).

a b s t r a c t

In this paper, we present a new low power down-conversion mixer design with single RF and LO input

topology which consumes 48 mW power. Detailed analysis of the mixer has been provided. Using the

presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and

fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been

fabricated through 0.13 mm CMOS technology. Dissipating 0.26 mW from a 1.2 V supply, the fabricated

PLL can track signals between 1.62 and 2.49 GHz. For receiver applications, the energy per bit of the

receiver is only 0.26 nJ making it attractive for low power applications including wireless sensor

networks.

& 2010 Elsevier Ltd. All rights reserved.

1. Introduction

High speed, low power phase-locked loops (PLL) are extensivelyused in frequency synthesis, clock generation and recovery circuitsfor microprocessors and wireless communication systems. A PLLcan also be used as a natural demodulator for wireless commu-nication receiver applications. Wireless communication ICs areextensively used in mobile devices, portable electronics andpositioning systems. For most of these applications, limited batterypower necessitates low power design. This paper discusses circuittechniques and design methodologies to build a high speed, lowpower PLL, with specific application for ultra low power FSK and FMreceivers such as those used in ad-hoc distributed wireless sensornetworks (WSN). For such applications, receivers are typically leftunattended for extended periods of time (perhaps several monthsor even years), and thus require maximum power efficiency. Tohelp meet these low power requirements, instead of using a digitalphase detector [1–3], we have designed an extremely low poweranalog phase detector and a PLL for signal demodulation.

Generally, Gilbert cell based mixers are widely used as analogphase detectors in PLLs [4]. However Gilbert cell based mixers(phase detectors) [4,5] often consume prohibitive power for WSNapplications because of their current sources and related stacked

ll rights reserved.

structures. The Gilbert cell also uses differential inputs whichusually require additional accessory circuitry. A differential topol-ogy of a VCO [4], LNA or balun [6] is often used to meet the Gilbertcell’s differential input requirement. However, a differential inputstructure can be vulnerable to phase error due to device mismatch,and a balun usually occupies a large area on the chip.

In this paper, a single RF and LO input mixer, which we use as aphase detector for the PLL, is presented and implemented. Thephase detector achieves ultra low power consumption and highlinearity. The presented phase detector consumes low power due toits single end topology and current re-use. This phase detector alsotakes advantages of the parasitic capacitors of the MOSFET to filterout high order harmonic signals and thus achieves high linearity.The low pass filter formed by the parasitic capacitors also helps toremove harmonic distortion. (In other circuits this function ispartially performed by a differential topology such as a Gilbert cellwhich naturally removes even harmonics.) Also in the presentedcircuit, the constituent PLL circuit components are simplified as aresult of the single input phase-detector topology.

An oscillator is another necessary component in a PLL. LCoscillators and ring oscillators are widely used in different applica-tions. Both LC oscillators [4] and ring oscillators [7] have previouslybeen implemented in PLL applications. LC oscillators are generallyused in favor of ring oscillators due to their superior phase noise[8,9] and lower sensitivity to variations in power supply voltage,while consuming milliwatts of power in on-chip topologies[8,10,11]. However, for ultra low power applications (on the order

B. Li et al. / Microelectronics Journal 42 (2011) 358–364 359

of 100 mW), we find the losses due to on-chip inductors limit theapplicability of on-chip LC oscillators. On the other hand, ringoscillators do not suffer from on-chip inductor losses, and canachieve oscillations at a 100 mW power level. Additionally, mobilecommunication systems commonly impose stringent phase noiserequirements to eliminate interference from nearby frequencybands to accommodate more users. LC oscillators are typically usedto meet this requirement. However, in applications such as WSN,interference from neighboring bands is often less of a concernbecause there can be less nodes in the band, or the WSN may beoperating in a remote location where interference is minimal butpower conservation is essential, and a ring oscillator with SAW filterin front can satisfy the combined bandwidth and power constraint[13]. We thus find that it is preferable to use a current-starved ringoscillator for WSN applications. Similar findings have been obtainedby other authors for ultra low power applications [12].

The Type-I analog PLL is at the core of the ultra low powerreceiver. Often, On–Off Keying (OOK) architectures [13] or super-regenerative architectures [14,15] are implemented to minimizepower consumption. In this paper, a PLL based architecture isexplored. Compared with super-regenerative architecture [14,15],the data rate of the FSK is higher. The potential difficulty of OOK andthe presented FSK ultra low power receivers with respect tointerference can be met by using a highly selective surface acousticwave (SAW) filter at the input as discussed above.

This paper consists of four sections. Section 2 presents thecircuit components mixer/phase detector and oscillator. Detailedcircuit analysis and design procedures have been given for thepresented single input low power mixer. Section 3 explores PLL’sapplication as a receiver. Section 4 presents the fabricated inte-grated circuit and the measured results for the PLL, and demon-strates its application as a receiver. Section 5 summarizes the workand provides conclusions.

2. Design and implementation of the presented PLL

2.1. PLL architecture

A block diagram of the second-order PLL architecture we use isenclosed in the dashed-line box in Fig. 1. The analog phase detector(PD) compares the phase difference between RF and local oscillatorsignals. It employs a single RF and LO input mixer topology. Thistopology simplifies voltage-controlled oscillator design for the PLLapplication, and also simplifies the LNA design required when thePLL is used in FM and FSK demodulation. The low pass filter (LPF)removes the high frequency components and is fundamental indetermining the dynamics of the PLL. As will be discussed later, weuse a relatively high bandwidth low pass filter to increase the lock-in range of the PLL to facilitate FM demodulation. A ring oscillator

Fig. 1. Block diagram of PLL and its application as an FSK receiver when used with a

LNA, comparator and a DSP.

topology is utilized for the VCO to obtain mW power consumptionwith reasonable phase noise.

2.2. Down-conversion mixer topology

Fig. 2(a) shows the schematic of the single RF and LO inputmixer. The radio frequency signal and local oscillator signals areconnected to the gates of transistors M1 and M2, respectively. Themixer core consists of three transistors M1, M2 and M3. M1 and M3work in the saturation region, M2 is turned on/off by the local ringoscillator signal (0–1.2 V square wave). M2 chops (multiplies) theRF signal with a square wave. In other words, M1 and M2 performthe non-linear mixer frequency translation. Both of the transistors(M1 & M2) are close to minimally sized devices. The detailedreasoning is given in Section 2.3. We make use of the intrinsiccapacitors of M3 to filter out the high frequency harmonic signals toobtain high linearity while amplifying the desired down convertedsignal. Fig. 2(b) shows the mixer with one extra transistor to furtherfilter out high frequency harmonic signals and improve the mixerlinearity. Moreover, the wide frequency range of the mixer is due toM1 and M2, which have very large unity gain frequencies (fT) due totheir minimal sizes. Thus, according to ADS post layout simulationsthe mixer topology can operate in a very high frequency rangebetween 1.6 and 40 GHz. This range seems plausible since mea-surements by the foundry show good agreement with the devicemodel up to 40 GHz.

The presented mixer topology consumes less power due to itssingle branch structure and current re-use. In other words, we use asingle current through the structure to multiply, amplify and filterthe signal. Also, since M2 can be a minimum size device, it usesultra low power for switching.

Another attribute of the mixer is that it provides a natural DCbias for the next stage (VCO) of the PLL. More specifically, Vctrl, asseen in Fig. 2, sets the DC bias for M1 and controls the DC outputvoltage (point O). Since the output has a DC connection to the VCO(after the LPF), Vctrl controls both the DC bias point and thus the VCOoperation frequency with a single bias. This multi-purpose bias

Fig. 2. Schematic of the mixers. (a): Three transistor mixer. (b): Four

transistor mixer.

B. Li et al. / Microelectronics Journal 42 (2011) 358–364360

thereby also provides the ability of the PLL to operate over a widefrequency range by simply adjusting the single bias voltage Vctrl.

2.3. Analysis of mixer

The mixing process for the circuit in Fig. 2(a) is described asfollows: the local oscillator signal switches the transistor M2 atoscillator’s frequency. The RF signal applied to the gate of M1 iscoupled to the LO signal and appears at the drain of M2 in the form of afunction of the LO signal. The multiplication of the RF and LO signals isdescribed by Eq. (1). For a pure sinusoidal RF signal, the mixed signalat point g in Fig. 2(a) can be mathematically described as

VguðtÞ ¼ VRF

XDnG

2ðcosðnoLOþoRF ÞtþcosðnoLO�oRF ÞtÞ,

Dn ¼ Vppsinðnp=4Þ

np=2ð1Þ

where n is a integer, G is the magnitude of the gain of the multiplierfrom the RF input port to the output at point g and is equal to gm1/gm3

where gm1 and gm3 are trans-conductance of transistor M1 and M3,respectively, Vg, is the loaded voltage at point g, and V 0g is the opencircuit voltage at g. Vpp is the peak to peak voltage of the square waveand Dn is square wave Fourier coefficients.

As indicated previously, transistor M3 amplifies the desired lowfrequency signal and filters out the high frequency harmoniccomponents to improve the linearity of the down-conversionmixer. Fig. 3 shows the small signal equivalent circuit seen atthe point g, looking into the source of M3. Rg and ro are the outputresistance looking toward M2 at point g and the M3 channelmodulation resistance, respectively.

The small signal voltage gain VO/Vg0 is given as

A¼ZLð1þgm3roÞ

ðZLþroÞð1þsCgsRgÞþðgm3roþ1ÞRgð2Þ

where Ct is (Cgd+Cdb) and ZL is RL//(1/oCt), and gm3, Cgd and Cdb

refer to M3.Since gm3rob1, for low frequency signals the voltage gain is

Alow ¼RL

Rgð3Þ

For high frequency, the voltage gain is

Ahigh ¼ð1þgm3roÞ

ð1þsCtroÞð1þsCgsRgÞþRgsCtðgm3roþ1Þo

1

RgsCt51 ð4Þ

Judging by Eqs. (3) and (4), the capacitor Ct needs to be largeenough to filter out the high frequency signal but small enough toamplify the intermediate frequency (IF) signal. To achieve this, thesize of transistor M3 has been chosen as 200 mm/640 nm in thisdesign. Transistors M1 and M2 are chosen to be as small as possiblefor high frequency applications. ADS simulation results show thatthe mixer can operate from 1.6 to 40 GHz with a 1.2 V supplyvoltage. The power consumption, which is verified by measure-ments on the fabricated chips, is mainly determined by supplyvoltage (Vdd) and RF DC bias voltage (Vctrl).

In Fig. 2(b), we show a small revision to the mixer topology byadding an additional transistor M4 to improve linearity. For this circuit,

Fig. 3. Equivalent circuit looking into the source of transistor M3 as seen by voltage

source Vg0 with source resistance Rg.

M3 works in the linear region. The operation of this circuit is analogousto that in Fig. 2(a), however, the addition of the extra transistor M4 actsas a second filter in series with the filtering effects provided by M3,thereby increasing the high frequency roll-off of the mixer andimproving the linearity. In addition, it should be pointed out thatM4 provides the voltage gain of the down converted (IF) signal, while inFig. 2(a), M3 provided the voltage gain. The mixer in Fig. 2(b) achieves ahigher linearity than that of Fig. 2(a) while having a similar voltage gain.These analyses agree well with ADS simulation results.

The mixer voltage gain is constrained by the power consump-tion, so is the noise. M1 is chosen as a minimum length device(L¼130 nm) to help minimize the in-direct flicker noise [16], as wellas to achieve a high unity gain frequency fT. The transistor M2 isturned on/off by the ring oscillator signal and consumes CV2f powerwhere C is the M2 gate capacitor, V is the peak to peak voltage of theoscillation signal (LO as shown in Fig. 2) and f is the oscillationfrequency. M2 is chosen as a minimum size device to minimizepower consumption. Due to the super low power constraint, gm1 issmall. It thus requires a large resistor to obtain reasonable voltagegain. Furthermore, for the receiver application, the next stagefollowing the mixer is the low pass loop filter, and thus does notload down the AC voltage gain at baseband frequencies. We use aresistor load RL instead of an active load to eliminate flicker noise.

To arrive at our circuit, we established several constraints tofacilitate design in 130 nm process for WSN applications. Thepower is constrained to be less than 50 mW and the voltageamplitude of the down converted signal is required to be at least50 times larger than the amplitudes of other harmonic signals.Furthermore, the output voltage at point O, which is DC connectedto the mixer through the low pass filter, needs to vary around aquiescent voltage of 0.6 V (half of the Vdd) which is well suited forthe VCO operation. The bias current is set by the power consump-tion, I¼P/Vdd. The resistor value (RL) is calculated using the currentand the required voltage gain. The M1 size is calculated from thecurrent, after a single DC bias voltage is applied to both Vctrl andVbias. The minimal device area of the transistor M3 is calculatedfrom Eqs. (3) and (4). The precise sizes of the transistors are thenrefined using ADS, while employing BSIM4 transistor models, tooptimize performance and satisfy the design constraints. Thesimulation results agree reasonably well with the analytical results.

Power consumption, noise figure, conversion gain and linearity(IIP3) help to determine mixer performance. For our designedmixer, simulation results show that the power consumption,voltage conversion gain, noise figure and IIP3 are 48 mW, 8, 26.5and 23 dB, respectively. The mixer figure of merit (FOM) [17], whichis used to evaluate the combined effect of these mixer parameters,can be expressed as

FOM¼ 10log10G=2010ðIIP3�10Þ=20

10NF=10P

!ð5Þ

where G and NF represent voltage gain and noise figure in dB, P

represents power consumption in Watts and IIP3 describes linearity indB. It can be seen in Eq. (5) that a higher FOM indicates betterperformance. By the simulation results, our mixer shows a FOM of 27.2.

2.4. VCO design

In this work, we seek the goal of extremely low power for use inWSN receiver applications. A CMOS inverter ring oscillator struc-ture is chosen as the VCO in this PLL for its 100 mW range powerconsumption, compactness and ease of implementation.

Fig. 4 shows the current-starved ring oscillator used as the VCO inthe PLL. It uses three inverting stages in a ring to generate oscillation,and one more inverter to minimize the loading effect at the output(Vosci). The input control voltage VVCO sets the drain current ID that

Fig. 4. Schematic of the current-starved ring oscillator.

Fig. 5. Measured (symbols with solid line) and extracted simulated (solid line) VCO

tuning characteristics.

Fig. 6. Simulated demodulated FM signal with 16 MHz modulation at 2.3 GHz input

signal.

B. Li et al. / Microelectronics Journal 42 (2011) 358–364 361

controls the oscillating frequency of the VCO. The current ID ismirrored with a ratio of 1:140 in each inverting stage to minimizepower consumed by references. The output of the ring oscillator Vosci

is buffered by an inverter to reduce capacitive loading.The sizes of the inverting stage transistors are designed to

obtain the switching point at half of the power supply voltage. Thesymmetry of the rising and falling edges improves the phase noiseby decreasing the 1/f 3 corner frequency [9].

In the PLL, the output of the ring oscillator Vout is connected to theLO input of the phase-detector (mixer) as is shown in Fig. 2. Thefiltered phase-detector output is connected to VVCO as shown inFig. 4. The voltage, VVCO, has been designed to make the VCO oscillatein a range between 1.8 and 2.4 GHz. Fig. 5 shows both the simulatedand the measured oscillation frequency and VCO voltage (VVCO)curves obtained by varying VVCO. The extracted layout simulationfrequencies are slightly lower than the measured data. Thediscrepancy may result from process threshold voltage variationof the transistors. The linearity around the PLL working frequencyrange is sufficient for proper operation. The power consumption ofthe VCO is 207 mW. The area of the VCO layout is 25�30 mm2, whichis order of magnitude smaller than a LC oscillator of similarfrequencies.

3. Receiver application and its sensitivity

This PLL has been integrated with a common source cascodeLNA to work as a RF receiver. The receiver can demodulate both FM

and FSK signals. In general, a FM signal can be described as

VRF ðtÞ ¼ Asinðo0tþM sinðostÞÞ ð6Þ

where the o0, os and M are carrier frequency, baseband frequencyand modulation index, respectively. When the PLL tracks the inputsignal, the VCO output is

VLOðtÞ ¼ Bsinðo0tþM sinðostÞþfÞ ð7Þ

fLOðtÞ ¼o0tþMsinðostÞþf ð8Þ

where B and f are the VCO amplitude and phase error which areconstants. So the VCO input is

VVCO ¼ b@fout

@t¼ bðo0þMos sinðostÞÞ ð9Þ

where b is a constant. Eq. (9) shows the VCO input voltage (VVCO) isthe demodulated signal under locked conditions.

The loop filter is fundamental in determining the settling speedand lock-in range of the PLL. Generally, the lock-in range in type-IPLLs is of the same order as the loop bandwidth, and a larger loopbandwidth means faster PLL settling, which is preferred in most ofapplications. However, a higher �3 dB point frequency in the loopfilter increases ripple while increasing the VCO phase noise. In thisreceiver application, a 100 MHz bandwidth LPF is used. Simulationshows a 90 MHz lock-in range for a fixed Vctrl. For receiverapplications, VVCO(t) is the demodulated signal under the PLLlocked condition as shown by Eq. (9).

For a FM input signal, Fig. 6 shows the ADS simulation results forthe demodulated signal (VVCO) for a 2.3 GHz FM signal with 16 MHz

Fig. 7. Simulated demodulated BFSK signal with 5 MHz modulation at 2.3 GHz

input signal.

Fig. 8. Die photo of the PLL test chip integrated with a LNA (1 mm2).

Fig. 9. PLL close loop spectrum. (Hor

B. Li et al. / Microelectronics Journal 42 (2011) 358–364362

baseband modulation; the lock-in time is approximately 80 ns. Fora BFSK input signal, the VVCO yields two constant voltages as shownin Fig. 7 under the PLL locked condition. The RF frequency(the carrier frequency) for the output shown is 2.3 GHz, which isdigitally modulated by a 5 MHz BFSK signal. The data rate is 5 Mbpswith the lock-in time of approximately 50 ns as shown in Fig. 7. Inorder to successfully demodulate the FSK signal, the PLL needs tolock to the carrier signal frequency in a baseband signal timeperiod. Thus the lock-in time limits the data rate. Fig. 6 shows thelock-in time is approximately 50 ns which implies a maximum20 Mbps data rate. ADS simulation predicts a data rate as high as10 Mbps for the BFSK signal.

4. Experimental results

The prototype chip has been fabricated in a 0.13 mm single-polyseven-metal standard CMOS process. Fig. 8 shows the micropho-tograph of the 1�1 mm2 fabricated chip. A typical common sourcecascode LNA is included to explore the PLL in an actual wirelessreceiver application. The PLL is fully integrated and its coreoccupies 75�45 mm2 chip area. The total power consumption ofthe PLL part of the receiver is only 0.26 mW.

The closed loop PLL spectrum has been measured by a MXAN9020A spectrum analyzer and an Agilent E8267D signal gen-erator. Fig. 9 shows the closed loop PLL spectrum after the buffercircuit for a 2.232 GHz input signal. The measured amplitudeagrees with simulated signal amplitude (�15 dBm). The spectrumhas a phase noise of �95 dBc/MHz at 200 KHz.

For the VCO, a one-stage common drain buffer is included forimpedance matching to facilitate measurement. Fig. 5, of theprevious section, shows the tuning characteristic of the VCO. Themeasured tuning range is more than 600 MHz. The power con-sumption is 207 mW.

Fig. 10 shows the measured demodulated signal of a 2.23 GHzFM signal with 1 MHz modulation with a modulation index of 8(see Eq. (8)). The demodulated signal can be clearly seen at the topof the oscilloscope screen; the bottom of the screen shows thesignal after a 1 MHz low pass filter. Fig. 11 shows the PLL centralfrequency as a function of the mixer control voltage (Vctrl) (lefty-axis). It shows that the PLL can track signals continuously from

iz. 500 KHz/div Vert. 10 dB/div).

B. Li et al. / Microelectronics Journal 42 (2011) 358–364 363

1.62 to 2.49 GHz by varying the phase-detector control voltage(Vctrl). Fig. 11(right y-axis) shows the PLL tracking frequency rangeas a function of phase-detector control voltage. For a fixed Vctrl, thelock-in range decreases as the bias voltage moves away from theoptimized bias voltage (0.7 V). This variation is attributed to theoscillator and phase-detector, which have their best performancewhen Vctrl is in the range of 0.65–0.75 V. The measured result showsthe maximum lock-in range is 90 MHz, which is close to the pole ofthe PLL loop filter. It also agrees with the simulation result as statedin Section 3. The PLL can track a signal from �67 to �25 dBm with

Fig. 10. Measured waveform of demodulated PLL for 1 MHz modulation with

8 MHz derivation at 2.3 GHz. Upper: measured PLL output. Bottom: measured PLL

output after a 1 MHz oscilloscope digital filter. (Horiz. 1 ms/div Vert. 10 mV/div

(Vp�p 10 mV.))

Fig. 11. Left y-axis: measured PLL center lock frequency as a function of control

voltage (blue dotted line). Right y-axis: measured PLL tracking range as a function of

control voltage (black solid line). (For interpretation of the references to colour in

this figure legend, the reader is referred to the web version of this article.)

Table 1PLL performance comparisons.

[1] [2]

Technology (mm) 0.18 0.13

Supply (V) 1.8 1

Frequency (GHz) 6.3 1.575

Power 14.8 mWa 0.56 mW

Lock range N/A 1.35 MH

Phase noise �104 dBc/Hz at 200 KHz �120 dB

a Frequency divider power not included for fair comparisons.

an on-chip LNA. However, this is highly dependent on the LNAcharacteristics and can be improved by LNA gain and poweroptimization. The PLL based architecture weakly suppresses outof band signals through the mixer and PLL loop filters. Suppressionof interferers could be increased at the price of lock-in frequencyrange. Table 1 summarizes and compares the PLL performance withthose of recently published works [1–3]. (We did not include powerconsumed by frequency dividers in the other works to achieveconsistent comparison). We also compared this receiver with otherlow power receiver works such as OOK receiver [13] and super-regenerative receiver [14] in Table 2. This work achieves a lowerenergy per bit compared with OOK receiver [13] for comparablesensitivity. While the super-regenerative design [14] has highersensitivity than our receiver, our topology uses less energy per bit,which attributes to the efficient power utilization of our mixer andVCO; it also indicates potential design tradeoffs between powerand sensitivity.

5. Conclusion

In this paper, a single input mixer topology with extremely lowpower consumption has been designed and fabricated. Our mixerhas a simulated figure of merit of 27.2. The mixer is used as a phase-detector. According to simulation, the phase-detector can work in awide frequency range (1.6–40 GHz) due to its small device size andtopology. By using the proposed phase-detector, a low power PLL isdesigned and fabricated. The fabricated PLL circuit occupies75�45 mm2 chip area and consumes 260 mW. The measuredpower consumption and chip area of the PLL are compared withprevious publications as shown in Tables 1 and 2. A common LNA isintroduced to demonstrate PLL’s application as a natural demodu-lator in ultra low power wireless applications, such as wirelesssensor networks. Experiments show that a 2.3 GHz FM signal with1 MHz modulation has been successfully demodulated for a1 Mbps data rate. Furthermore, RFDE ADS simulation resultsindicate that it is possible to obtain data rates as high as 10 Mbps.The energy per bit of the receiver is only 0.26 nJ which should makethe design attractive for ultra low power applications.

[3] This Work

0.18 0.13

1.2 1.2

24 2.3a 0.52 W 0.26 mW

z N/A 600 MHz

c/Hz at 200 KHz N/A �95 dBc/Hz at 200 KHz

Table 2Receiver performance comparisons.

[12] [14] This Work (No LNA)

Center frequency 916.5 MHz 2.4 GHz 2.3 GHz

Sensitivity (dBm) �37 �90 �35

Power (mW) 0.5 2.8 0.26

Data rate 1 Mbps 500 Kbps 1 Mbpsa

Energy per Bit (nJ) 0.5 5.6 0.26

Interference suppression ability None Moderate Weak

a Limited by measurement equipment.

B. Li et al. / Microelectronics Journal 42 (2011) 358–364364

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