understanding arm11 processor power saving modes...

Understanding ARM11 ProcessorPower Saving Modes

Application Note 143

Released on: October 2007

ARM DAI 0143C Copyright © 2006, 2007. All rights reserved. 1

Understanding ARM11 Processor Power Saving ModesApplication Note 143

Copyright © 2006, 2007. All rights reserved.

Release Information

Table 1 lists the changes to this document.

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Table 1 Change history

Date Issue Confidentiality Change

15 September 2006 A Non-Confidential Initial issue

20 December 2006 B Non-Confidential Updated for compatibility with InfoCenter

26 October 2007 C Non-Confidential Updated example code changes

2 Copyright © 2006, 2007. All rights reserved. ARM DAI 0143C

1 Power Management Modes on the ARM11 Processors

This document describes the power management modes available on the ARM11 processors and hardware and software considerations for implementing power management in an ARM11 design.

The ARM11 processor core supports four levels of power management, discussed in the following sections:

• Run Mode

• Standby Mode

• Shutdown Mode on page 14

• Dormant Mode on page 4.

1.1 Run Mode

This mode is the normal mode of operation in which all of the functionality of the ARM11 processor is available. If an ARM1176 or other IEM-aware core is used, the Energy Management capabilities of the IEM module are used in Run Mode. For more information on this power saving capability, see the Intelligent Energy Management section in the appropriate technical reference manual.

1.2 Standby Mode

This mode disables most of the clocks of the device, while keeping the device powered up. This reduces the power drawn to the static leakage current, plus a tiny clock power overhead required to enable the device to wake up from Standby Mode. The user requests entry into Standby Mode through the execution of a Wait For Interrupt instruction and the ARM11 processor signals it is in Standby Mode by asserting the STANDBYWFI signal. The transition from Standby Mode to Run Mode is caused by one of the following:

• an interrupt (nIRQ) or fast interrupt (nFIQ), whether masked or unmasked

• an external debug request (EDBGRQ), regardless of whether debug is enabled

• assertion of Reset.

1.3 Shutdown Mode

This mode allows the entire device to power down. All processor state, including cache and TCM state, must be saved externally. This state saving finishes with a Data Synchronization Barrier Operation, also called Drain Write Buffer or Data Write Barrier. When the necessary state information of the ARM11 processor core is saved, the user executes a Wait For Interrupt instruction. The core then asserts the


STANDBYWFI signal to indicate to the external power controller that the processor is in Standby Mode and is ready to be powered down to enter Shutdown Mode. Implementation of Shutdown Mode also requires the following external considerations:

• Implementation of an external Power Management Controller to control the power supply and reset signals for the core, and that can differentiate between an initial Power On Reset and subsequent returns from Dormant or Shutdown Mode.

• The part must be returned to Run Mode by the assertion of Reset.

1.4 Dormant Mode

This mode enables the ARM11 processor core to power down while leaving the caches and the TCM powered up and maintaining their state. Similar to Shutdown Mode, all state must be saved, with the exception of the contents of the caches and the TCMs. It finishes with a Data Synchronization Barrier and a Wait For Interrupt instruction. The core then asserts the STANDBYWFI signal to indicate to the external power controller that the processor is in Standby Mode and is ready to be powered down to enter Dormant Mode.

Although software visibility of the cache Master Valid bits and the TLB lockdown entries is provided to enable implementation of Dormant Mode, the following are required for full implementation of Dormant Mode:

• modification of the RAM blocks to allow clamping of RAM inputs

• implementation of separate power domains

• implementation of an external Power Management Controller to control the power supply and reset signals for the core, and that can differentiate between an initial Power On Reset and subsequent returns from Dormant or Shutdown Mode

• the part must be returned to Run Mode by the assertion of Reset.


2 Design Considerations for Power Management

This section describes the design considerations for power management in the four modes. It includes these sections:

• Standby Mode

• Dormant Mode on page 6

• Shutdown Mode on page 14

• Communication with Power Management Controller on page 15.

2.1 Standby Mode

The Wait For Interrupt CP15 operation is executed to enter into Standby Mode. A Data Synchronization Barrier operation must be performed before the Wait For Interrupt operation to ensure the memory system is not affected by the entry into the Standby state. This synchronization ensures that all explicit memory accesses occurring in program order before the Wait For Interrupt have completed, and avoids any possible deadlocks that can caused in a system where a memory access triggers or enables an interrupt that the core is waiting for.

The DMA continues running during a Wait For Interrupt and any queued DMA operations are executed as normal. This continuation enables an application using the DMA to set up the DMA to signal an interrupt when the DMA has completed, and then for the application to issue a Wait For Interrupt instruction. When the DMA completes an operation, it signals either Complete or Error, not Idle. The system software must then set the DMA state to Idle before the core can enter Standby Mode.

Any other memory accesses started at the time the Wait For Interrupt instruction is executed are completed as normal. This completion ensures the level two memory system does not see any disruption caused by the Wait For Interrupt.

The debug channel remains active throughout a Wait For Interrupt. You must tie the DBGTCKEN signal to VSS to avoid clocking unnecessary logic to ensure best power-saving when not using debug. Systems that use the VIC interface must ensure the VIC is not masking interrupts that are required for restarting the ARM11 processor when in this mode of operation.

The clock module within the ARM11 processor waits for other modules to indicate they are ready to enter Standby Mode before it stops the clock signals. These modules are:

• the Main TLB

• the Instruction port

• the DMA

• the ETM, through the input signal nETMWFIREADY.


When the processor clocks are stopped, the signal STANDBYWFI is asserted to indicate that the ARM11 processor core is in Standby Mode.

2.2 Dormant Mode

Dormant Mode is supported on ARM11 processors. Care is required to implement this mode on a standard synthesizable flow. The RAM blocks designated to remain powered up must be implemented on a separate power domain, and there is a requirement to clamp all of the inputs of the RAMs to a known logic level, with the chip enable being held inactive. This clamping is not implemented in gates as part of the default synthesis flow because it contributes to a tight critical path.

Designers who want to implement Dormant Mode must add these clamps around the RAMs, either as explicit gates in the RAM power domain, or as pull-down transistors that clamp the values while the core is powered down.

The RAM blocks that must remain powered up during Dormant Mode are:

• all Data RAMs associated with the caches and tightly-coupled memories

• all Tag RAMs associated with the caches

• all Valid RAMs and Dirty RAMs associated with the caches

• all Valid RAMs and Dirty RAMs associated with SmartCache (ARM1136 processor only).

The state of the Branch Target Address Cache is not maintained in Dormant Mode.

The ARM1136 processor can optionally power down the RAMs associated with the Main TLB, so that a trade-off can be made between Dormant Mode leakage power and the recovery time. This option is not available on the ARM1176 processor because the software access to the main TLB valid bits was removed from ARM1176 processor to enhance security for TrustZone considerations.

The state of the ARM11 processor, excluding the contents of the RAMs that remain powered up in Dormant Mode, must be saved to external memory before entering Dormant Mode. These state saving operations must ensure the following occur:

• All ARM registers, including CPSR and SPSR registers are saved.

• Any DMA operations in progress are stopped.

• All CP15 registers are saved, including the DMA state.

• All VFP registers are saved if the VFP contains defined state.

• Any locked entries in the Main TLB are saved.


• All debug-related states are saved.

• The Master Valid bits for the cache and SmartCache are saved using CP15

operations.

• If the Main TLB is powered down on entry into Dormant Mode (ARM1136 only), then the Valid bits of the Main TLB must be saved using CP15 operations.

• On the ARM1136, a Drain Write Buffer instruction is executed to ensure that all state saving has been completed. This is the same as the Data Write Barrier operation on the ARM1176 processor.

• A Wait For Interrupt CP15 operation is then executed, putting the ARM11 processor in Standby Mode and enabling the signal STANDBYWFI to indicate that the processor can enter Dormant Mode.

Transition from Standby Mode to Dormant Mode is then triggered by the external power controller asserting Reset to the ARM11 processor for at least three CLKIN clock cycles.

While Reset is asserted, the RAMs that remain powered during Dormant Mode must have their input clamps turned on. Power can then be removed from the ARM11 processor. The ARM1176 core has a RAMCLAMP input that enables control of clamps on RAMs within the ARM11 macrocell. This signal must be added to the ARM1136 core by the user. The implementation of the clamps is specific to the individual design and must be implemented by the user.

Transition from Dormant Mode to Run Mode is triggered by the external power controller asserting Reset to the ARM11 processor, and holding Reset while restoring power to the processor. When power is restored, the external power controller must release the signal clamps to the RAMs. Then the Reset pin to the core can be released. The core leaves the reset state and, by interrogating the external power controller, can determine the saved state must be restored.

Caches

The ARM11 processor save and restore routines can work independent of the cache status. If the cache is enabled when the Dormant Mode save is initiated, then cache status is preserved by the save of all CP15 registers, including the Cache Master Valid registers. The restore sequence then automatically re-enables the cache because the cache and MMU enables are part of the restored CP15 state. While it is possible to save most state into the cache, the cache state cannot be saved into the cache. On exit, this state must be restored before the cache is re-enabled. You must disable the cache before saving the cache state to ensure that cache state is saved to main memory.


Table 2 shows the Cache Master Valid registers that must be saved, depending on the cache sizes.

Tightly coupled memory

This section describes tightly coupled memory (TCM).

Normal configuration

If TCMs are not enabled as SmartCache, SmartCache master valid bits do not need to be saved, just the TCM region registers (for both the Instruction and Data TCMs). Saving and restoring the TCM region registers on a system with no TCMs has no effect, and may be easier and quicker for the operating system than testing if the TCMs exist.

SmartCache configuration (ARM1136 only)

If TCMs are enabled as SmartCache, the operating system dormant code needs to save the SmartCache master valid bits in addition to the TCM region registers. Writing the TCM Region registers clears all SmartCache Master Valid registers, so on exit the TCM region registers must be restored before the SmartCache Master Valid registers. The dormant code could check if TCMs are enabled as SmartCache as is done in the example code referenced in Dormant and Shutdown Mode Example Code on page 31.

Table 2 Cache Master Valid registers to save

Cache size Registers numbers to save

4KB 0

8KB 0

16KB 0 and 1

32KB 0 to 3

64KB 0 to 7


Table 3 shows the SmartCache master valid registers that must be saved, depending on the TCM sizes.

The example code referenced in Dormant and Shutdown Mode Example Code on page 31 checks for the TCM size before storing the master valid registers. Saving and restoring unused SmartCache Master Valid registers has no effect, and may be more efficient for the operating system than testing if the TCMs exist, are enabled as SmartCache, and determining their size. However, this can impact performance because of extra accesses to CP15 and main memory.

Memory management unit/Translation look-aside buffer

The ARM11 save and restore routines can work independently of the memory management unit (MMU) status. If the MMU is enabled when Dormant Mode entry is initiated, MMU status is preserved by the save of all CP15 registers. The restore sequence then automatically reenables the MMU because the cache and MMU enables are part of the restored CP15 state. Page tables are unaffected because they reside in memory that is not changed. Although it is possible to save most status into the cache, the MMU status cannot be saved into the cache. This is because on exit this status must be restored before the cache and MMU are re-enabled. You must disable the cache and MMU before saving the MMU status.

For the ARM1136 processor only, the main translation look-aside buffer (TLB) can be configured to remain powered up while the ARM11 core is in Dormant Mode. In this case, the Main TLB Master Valid registers must be saved when entering Dormant Mode.

The operating system must ensure the page tables in the main memory have not changed, because changes would make the main TLB and the main memory page table entries noncoherent.

Table 3 SmartCache Master Valid registers to save

TCM size Registers numbers to save

0KB None

4KB 0

8KB 0

16KB 0 and 1

32KB 0 to 3

64KB 0 to 7


If you use the TLB Lockdown feature, and the P bit of the CP15 TLB Lockdown Register is set when you run code to enter Dormant Mode, this can result in page table walks that go into the lockdown region of the TLB. This can overwrite previously locked down TLB entries and the lockdown region of the TLB will not be exactly preserved. To avoid this inaccurate preservation, clear the P bit of the CP15 TLB Lockdown Register before running Dormant Mode entry code. The example code referenced in Dormant and Shutdown Mode Example Code on page 31 clears this P bit as early as possible to avoid this problem. It can not prevent page table walks prior to this point in the code that write into the lockdown region of the TLB.

Direct memory access

If any direct memory access (DMA) channel is running or queued, it must be stopped before entering Dormant Mode. The DMA status that indicates how far the DMA operation progressed, must be saved. On exit, the DMA status is restored and any DMA channel that was running or queued is restarted from its previous point of progress.

The processor will not assert the STANDBYWFI output to signal it is ready to enter Dormant Mode until all DMA channels are Idle. When the DMA completes an operation, it signals either Complete or Error, it does not signal Idle. The system software must set the state to Idle before the core can enter Dormant Mode.

The Dormant Mode entry code must address any DMA channels that indicate an error. It must stop and clear all DMA channels before entering Dormant Mode. Because you cannot restore a DMA channel’s Error status, any error must be handled before entering Dormant Mode.

In a system with an external DMA, it is the user’s responsibility to ensure the external DMA is correctly handled when entering Dormant Mode. This can include stopping and clearing the external DMA and saving its state. The code to handle any external DMA must be written by the user.

Debug

Various registers must be saved and restored to preserve the current debug setup information. These registers are all accessible through CP14, and include:

• Debug Status and Control Register (DSCR)

• breakpoint value and control registers

• watchpoint value and control registers

• vector catch register.

To save CP14 debug registers, you must first save the DSCR, then write this register with bit 15 set and bit 14 clear to enable Debug monitor mode. This allows access to other debug registers.


Some debug registers contain bits that can only be read or written by an external Debug Test Access Port (DBGTAP) controller. The processor must not enter Dormant Mode if these bits are in use because this state cannot be saved and restored by software.

The DBGTAP controller must indicate when it controls bits by writing bit 9 of the DSCR. The value of this bit is visible on the top level output DBGNOPWRDWN. This signal should be connected to the power controller so the power controller will not enter Dormant Mode if DBGNOPWRDWN is set.

If you want to debug your Dormant Mode exit code, you must restore the debug registers very early in this code to set up and enable debug. This is described in the example code referenced in Dormant and Shutdown Mode Example Code on page 31.

Coprocessors that include VFP

If a coprocessor exists in your system, it must be accessed and its current state saved in main memory. The operating system’s Dormant Mode entry code must first save the state of the CP15 coprocessor access control register, then write to that register to enable the coprocessor so it can save its state. Because coprocessors are different, you must write specific code to save and restore the state of each coprocessor.

If you have a VFP coprocessor, the code must save the VFP Exception Register, then write to that register setting bit 30 to enable the VFP. This enables access to all other VFP registers.

You must also resolve any VFP exceptions before entering Dormant Mode. If the VFP is in an exceptional state, any instructions that address the VFP to save its state will fail with an Undefined Instruction exception.

Memory-mapped peripherals

Any memory-mapped peripheral that is powered down in Dormant Mode must have its state saved and restored using load and store instructions. To ensure correct behavior of the peripheral, you must ensure the state of each peripheral is restored before it is used. For example, if you have a Vectored Interrupt Controller (VIC), you must restore its state before enabling interrupts.

TrustZone for ARM1176 processor only

The TrustZone features of the ARM1176 processor include CP15 registers that are banked, and have separate Secure and Non-secure versions. Both versions must be saved and restored. To facilitate this and other aspects of TrustZone, the Dormant Mode save and restore code should run in Secure Monitor mode. Running in Secure Monitor


mode allows access to Secure and Non-secure versions of CP15 banked registers by changing the NS bit in the Secure Configuration Register. You must save this before you modify it.

Because the state is a mixture of both Secure world state and Non-secure world state, it is simplest and most secure to save all state into memory marked as Secure. This is achieved by running the code in Secure Monitor mode. Running in this mode has an additional advantage; you can save both Non-secure cache and MMU state into the cache, because this state is not used in Secure Monitor mode.

Branch prediction

Branch prediction is enabled by the CP15 Control and Auxiliary Control registers, that are restored on exit from Dormant Mode, and re-enable branch prediction if necessary. Because the Branch Tag Array Cache (BTAC) RAM is not powered up in Dormant Mode, any dynamic branch prediction information is lost. Branch prediction information is rebuilt in the normal way after exiting Dormant Mode.

Interrupts

You must consider whether to enable interrupts during the Dormant Mode save and restore code routines. These routines can require long times to complete. You might want to enable interrupts to avoid excessive interrupt latency. If your power controller brought the processor out of Dormant Mode because an external interrupt, do not enable interrupts until the exit code finishes. This avoids servicing the interrupt before the processor’s state is fully restored. If you choose to enable interrupts, consider the following:

• Disable interrupts while saving and restoring FIQ, IRQ, Secure Monitor (TrustZone only) and Abort mode registers and Saved Program Status Registers (SPSRs), because the interrupt will write to r14 and the SPSR of one of these modes.

• On exit, do not enable interrupts until you have restored all state required to handle them. These can include:

— MMU state, if exception vector addresses are mapped

— the V bit of the CP15 Control Register that indicates high exception vectors

— external Vectored Interrupt Controller, if present

— Vector Base Address registers

— Secure Configuration Register in a TrustZone enabled system (ARM1176 processor only).


• In a TrustZone enabled system (ARM1176 processor only), if an interrupt occurs in Secure Monitor mode when the NS bit is set, the NS bit is automatically cleared to keep the processor in the Secure world. If interrupts are enabled at this time, the interrupt handler must return to Secure Monitor mode and set the NS bit before returning from the interrupt.

• Some parts of the processor, such as the DMA and the performance monitor, can produce interrupt requests. You must consider if you want these interrupts to be honored and then enable or disable interrupts or the functionality of these features accordingly.

State restoration

The basic rule for restoring the state of the ARM11 processor existing prior to Dormant Mode entry, is restore the registers in the opposite order in which they were saved. The exceptions to this rule are:

• Coprocessors, including the VFP, must be enabled by writing to the CP15 Coprocessor Access Control Register with the appropriate bits set, before the state of the coprocessors is restored.

• In Debug state, the Debug monitor mode must be enabled by writing to the DSCR with bit 15 set and bit 14 clear, before accessing any other debug register.

• Any setup code required to enable a peripheral or coprocessor must be run prior to the first access of that device in the state restore code. For example, the VFP must be enabled by writing to the VFP Exception Register with bit 30 set before accessing any other VFP register.

• Any register that must be modified to enable functionality to restore its state, must itself be restored after this modification has taken place. For example, if the CP15 Coprocessor Access Control register is written to enable a coprocessor so the coprocessor’s state can be restored, the Coprocessor Access Control Register must be restored after it has been modified. This ensures the register is restored to its original value.

• After restoring the DMA status, any DMA channel that was running or queued before entering Dormant mode must be restarted.

There are some states that must be restored on exiting Dormant Mode before re-enabling the caches and MMU, even when the caches and MMU are enabled:

• the cache master valid registers

• the control register

• auxiliary control register

• translation table base registers 0 and 1


• control register

• domain register

• the FCSE PID register

• the Context ID register

• the cache lockdown registers.

The Dormant Mode entry code must disable the caches and MMU, then save this state to ensure it is written into main memory. The Dormant Mode exit code must restore this state, reading it from main memory, before enabling the caches and MMU.

2.3 Shutdown Mode

This section describes shutdown mode.

Differences from Dormant mode

All previous considerations for Dormant Mode also apply to Shutdown Mode with the following exceptions:

• Shutdown Mode does not preserve the contents of the RAMs.

This includes the caches and the TCMs. Normally you incur the penalty of losing the cache data and expect the normal cache linefill mechanisms to cope with this on exit from Shutdown Mode. However, the TCMs do not have the same mechanism, even if the TCMs are enabled as SmartCache. If one or more ways of the caches are locked with the cache lockdown registers, the data or instructions in the locked cache way(s) will probably require restoration upon exit from Shutdown Mode. Because of this, the contents of the TCMs must be saved to main memory and restored on exit. For example, when you use the DMA engine, if cache lockdown is in use, the lines locked in the caches must be loaded back into the correct cache way(s) and locked again on exit.

On ARM1136 processors it is possible to automate this process because there are CP15 registers that enable software to identify which addresses are in the caches so they can be saved and the lines can be reloaded into the caches on exit from Shutdown Mode. It may be more desirable to load the required cache lines on exit from Shutdown Mode, because they will probably know what should be in there. On the ARM1176 processor there is no way to identify the addresses in the caches because the corresponding CP15 registers are removed to ensure the security of TrustZone. The operating system software must load the correct information into locked cache ways on exit from Shutdown Mode.

• Because cache and TLB RAMs are not preserved, it is not necessary to save and restore any Master Valid bits.


• Although entry to Dormant Mode does not require the user to perform a cache clean operation, before entry to Shutdown Mode the user must clean the entire data cache and also the data TCM(s) if enabled as SmartCache.

Table 4 lists these differences.

2.4 Communication with Power Management Controller

The Power Management Controller (PMC) performs the powering up and powering down of the power domains of the processor. The communication mechanism between the ARM11 processor core and the PMC is not specified by ARM, but could typically be a memory-mapped interface, accessed by the processor performing Strongly-Ordered memory accesses to it.

The precise operation or configuration of the PMC is not specified by ARM due to its application-specific nature. The basic functions related to Dormant and Shutdown Modes that the PMC must provide are:

• Determine, for instance when instructed by the processor, that the processor should be put into Dormant or Shutdown Mode.

• Wait for the STANDBYWFI output to be asserted by the ARM11 core.

• Assert and hold the core Reset pin for at least three clock cycles of CLKIN.

Table 4 Summary of differences between Dormant and Shutdown Modes

Dormant Mode Shutdown Mode

Don’t clean any caches. Clean the entire data cache and the entire Data SmartCache (if enabled).

Restore cache lockdown registers. Don’t restore cache lockdown registers. If cache lockdown features are used, the operating system must restore the lockdown registers and contents of locked ways.

Don’t save and restore the contents of enabled TCMs. Save and restore the entire contents of enabled TCMs, using DMA operations.

Save and restore Master Valid registers for caches, SmartCaches (if enabled), and the main TLB (if it remains powered up).

Don’t save any Master Valid registers.

For best performance, save state (except for memory setup state) into the data cache by saving to a write back memory region.

All RAMs are powered down and, thus, all state must be written out to main memory. It makes little difference whether the memory region used to store Shutdown Mode state is defined as write-back or write-through or non-cachable.


• If entering Dormant Mode, while holding Reset, enable the input clamps to all RAMs that will remain powered up during Dormant Mode.

• While holding Reset, remove power from the ARM11 processor core, and also from the RAMs if entering Shutdown Mode.

It is the responsibility of the PMC to determine when the core should exit Dormant or Shutdown Mode. This may typically be required when an external interrupt request is detected. When exiting Dormant or Shutdown Mode, the PMC must do the following, in order:

• Assert and hold the Reset pin to the ARM11 processor core.

• While holding Reset, restore power to the processor.

• If exiting Dormant Mode, while holding Reset, disable the input clamps to all RAMs that were active during Dormant Mode.

• Release the Reset pin to the processor core.

The PMC must also have the capability to inform the processor what type of reset has occurred. For example, whether the reset was due to exiting Dormant Mode or Shutdown Mode. This notification enables the processor to branch to the correct state restore routine, supplied by the operating system, to correctly restore the state of the processor prior to entry into the low power mode. This also requires the operating system to query the PMC regarding the cause of the reset.


3 Timing Considerations for Dormant and Shutdown Modes

This section includes:

• Factors Affecting Entry and Exit Times

• Example Cycle Counts on page 19

• Reducing Cycle Counts on page 22.

3.1 Factors Affecting Entry and Exit Times

The time taken for entry into Dormant or Shutdown Mode varies according to your specific system implementation and the amount of state you must save and restore. There are various factors that affect the number of cycles taken. These factors are discussed in the following sections.

Memory system

Up to 1KB of state information must be written to memory when entering Dormant or Shutdown Mode. The same state must be loaded when exiting Dormant or Shutdown Mode. The performance of the memory system directly affects the time required to enter and exit these low power modes.

In Shutdown Mode, all state must be written off-chip to main memory, so the configuration of the level 1 memory system is not critical. A high-performance bus between the processor and off-chip memory will reduce the time required to enter and exit Shutdown Mode.

Because on-chip RAMs remain powered up in Dormant Mode, the time required to enter and exit Dormant Mode can be significantly reduced by saving state into level 1 cache or TCM. With the cache, this is set up by enabling the data cache and MMU, and setting up page tables so that state is saved into a region of memory marked as write-back. ARM11 processors do not allocate into the data cache on writes, so any stores during entry to Dormant Mode that miss in the cache will write into main memory, and not fill into the cache, so on exit the data will be read from main memory, increasing memory access times. To avoid this penalty, the state save memory region can be preloaded and locked into the data cache using the cache lockdown feature. Alternatively, state can be saved into the data TCM, which guarantees that every memory write and read will hit in level 1, resulting in high performance. The data TCM cannot be used to store state for Shutdown Mode, as the TCMs are powered down in Shutdown Mode. Instead, state can be saved directly to main memory, or into the data cache and then written back to main memory using a cache clean operation.


When the caches and MMU are enabled, there is some state information that must be restored on exiting Dormant or Shutdown Mode before re-enabling the caches and MMU:

• the Cache Master Valid registers

• the Control Register

• Auxiliary Control Register

• Translation Table Base registers 0 and 1 and Control Register

• the Domain Register

• the FCSE PID Register

• the Context ID Register

• the Cache Lockdown Registers.

The Dormant Mode entry code must disable the caches and MMU, then save this state to ensure it writes to main memory. (This is not necessary for Shutdown Mode as the data cache must be cleaned so all state will be written to main memory.) The Dormant and Shutdown Mode exit code must restore this state, reading it from main memory, before enabling the caches and MMU. Alternatively, if Dormant Mode state is being saved into the data TCM, all of this state can be saved into the data TCM. The Dormant Mode exit code must write the data TCM region register to enable the data TCM so that it can restore state from it. (Shutdown Mode entry code cannot save state into the data TCM as it is powered down in Shutdown Mode.)

System coprocessors CP14 and CP15

Most state that needs to be saved and restored is in CP14 and CP15 registers, and is accessed using the MCR and MRC instructions. In typical code, these registers are rarely accessed, so the instructions to read and write them are not optimized for speed: it takes between three and eight clock cycles to execute a read or write of a CP14 or CP15 register. Dormant and Shutdown Mode entry and exit code is unusual in that it must execute many CP14 and CP15 register reads and writes, which takes a large number of clock cycles to complete. To reduce the total time taken, optimize the Dormant and Shutdown Mode entry and exit code to only save and restore the CP14 and CP15 registers that you ever use. For instance, if you never use the TLB lockdown feature, you can remove the code that saves and restores the TLB lockdown registers, which removes 32 MCR or MRC instructions on both entry and exit, as well as removing 24 word reads or writes to memory.

Optional and additional system components

Optional system components such as TCMs, DMA, and VFP, and additional components such as coprocessors and memory-mapped peripherals, all need to have their state saved and restored for Dormant and Shutdown Modes. This requires more


instructions and memory writes and reads, which increases the time taken. Some components, for instance coprocessors, have an additional overhead as they must be enabled before their state is saved or restored.

3.2 Example Cycle Counts

The ARM example code referenced in Section 4.2 was used to produce examples of the number of cycles required to enter and exit Dormant and Shutdown Modes with various memory system configurations. Example cycle times are given in Table 5 on page 20 through Table 8 on page 22 for both the ARM1136 and ARM1176 processors, both of which had the following hardware configuration:

• 16KB instruction and data caches

• 16KB instruction and data TCMs (in ARM1176 these were arranged as two 8KB instruction TCMs and two 8KB data TCMs)

• ARM internal DMA engine

• VFP coprocessor

• Two additional coprocessors with 16 registers each, saved and restored using LDC and STC instructions

• One memory-mapped peripheral with 3 registers.

Static and dynamic branch prediction were enabled. All TCMs were enabled (as local RAM on ARM1136, not as SmartCache). The memory system configurations used were:

• Instruction and data caches disabled, MMU disabled

• Instruction cache enabled, data cache disabled, MMU disabled

• Instruction and data caches enabled, MMU enabled, state saved to write-through memory region

• Instruction and data caches enabled, MMU enabled, state saved to write-back memory region

• Instruction cache enabled, data cache disabled, MMU disabled, state saved to data TCM (Dormant Mode only).

The example code referenced in Dormant and Shutdown Mode Example Code on page 31 was used without modification to produce example cycle counts. Entry to Dormant or Shutdown Mode was requested by a regularly recurring IRQ interrupt, with


a delay of 0x8000 clock cycles between exiting Dormant or Shutdown Mode and the following entry request. The IRQs interrupted the validation test T2-32 from the armv4 suite, which tests shift operations of data processing instructions.

Example cycle counts were produced for both Dormant and Shutdown Mode in all of these memory system configurations, except for saving state to the data TCM, as this is only useful for Dormant Mode. To illustrate the effects of the caches as data and instructions are cached and so the cache hit rate improves, Dormant Mode cycle times are given for both the first time Dormant Mode is entered and exited, with no cache hits, and for the third time Dormant Mode is entered and exited, with most memory accesses hitting in the caches. This effect is not seen in Shutdown Mode as the contents of the caches are lost when the RAMs are powered down. Shutdown Mode cycle times are given both for when the TCMs are assumed to be in use, so their contents are written to main memory and restored using ARM’s internal DMA engine, and for when the TCMs are assumed not to be in use so their contents are not preserved.

ARM1136 processor example

For these cycle counts, the ARM1136 TCMs were enabled as local RAM, not as SmartCache, so the SmartCache master valid registers are not saved and restored for Dormant Mode. The main TLB was assumed to be kept powered up in Dormant Mode, so the main TLB master valid registers are saved and restored for Dormant Mode.

A total of 206 words of state information were saved and restored for Dormant Mode, and 198 words for Shutdown Mode.

The example number of cycles taken to enter and exit Dormant and Shutdown Modes with an ARM1136 processor are shown in Table 5 and Table 6 on page 21 respectively.

Table 5 ARM1136 processor Dormant Mode example cycle counts

Instructioncache

Datacache

State save memoryregion

1st entry(cycles)

1st exit(cycles)

3rd entry(cycles)

3rd exit(cycles)

Off Off Main memory (MMU off) 3757 3605 3757 3605

On Off Main memory (MMU off) 3721 3617 3376 3252

On On Data cache (write-through) 2537 2927 2289 2149

On On Data cache (write-back) 2555 2909 1960 2122

On Off Data TCM (MMU off) 1832 1877 1710 1786


ARM1176 processor example

ARM1176 has TrustZone, which increases the number of registers that must be saved and restored. It also has an additional memory-mapped peripheral to control the level 2 memory security setup. This peripheral has 8 registers that are saved and restored.

A total of 250 words of state information were saved and restored for Dormant Mode, and 243 words for Shutdown Mode.

The example number of cycles taken to enter and exit Dormant Mode with an ARM1176 processor are shown in Table 7.

Table 6 ARM1136 Shutdown Mode example cycle counts

Instructioncache

Datacache


TCMs saved via DMA TCMs not saved

Entry(cycles)

Exit(cycles)

Entry(cycles)

Exit(cycles)





Table 7 ARM1176 Dormant Mode example cycle counts

Instructioncache

Datacache


1st entry(cycles)

1st exit(cycles)

3rd entry(cycles)

Off Off Main memory (MMU off) 4323 3830 4323

On Off Main memory (MMU off) 4161 3758 3893

On On Data cache (write-through) 2888 3015 2568

On On Data cache (write-back) 2888 2993 2345

On Off Data TCM (MMU off) 2422 2248 2311


The example number of cycles taken to enter and exit Shutdown Mode with an ARM1176 processor are shown in Table 8.

3.3 Reducing Cycle Counts

This section describes mechanisms to reduce cycle counts.

Reduce counts through memory system configuration

You can significantly reduce cycle counts by configuring the memory system correctly. Enabling the caches and storing state to a write-back memory region for Dormant Mode, or a write-through memory region for Shutdown Mode, speeds up low power mode entry and exit significantly. For Dormant Mode, the performance can be further improved using the cache lockdown feature to ensure the required data and instructions are always in the cache. Alternatively, storing state to the data TCM is another way to guarantee that every memory access hits in level 1 memory, reducing the cycle count.

A possible system level optimization to reduce the time required to enter and exit Dormant Mode when saving state into the level 1 data cache is to have a static, known memory setup specifically for the Dormant Mode entry and exit code. This allows memory configuration state, that can be up to 15 words, to be saved locally into the data cache rather than saving it to main memory. This optimization is only useful if both the original memory system and the Dormant Mode specific memory system define the region of memory used to store Dormant Mode state as write-back, so that it can be written into the data cache instead of main memory. This optimization is not useful for Shutdown Mode because the data cache contents are not preserved. This optimization is described in the ARM example code referenced in State to be Saved on page 24, and is enabled using the option DM_STATICMEM in that code. See the comments in the code for more details.

Table 8 ARM1176 Shutdown Mode example cycle counts

Instructioncache

Datacache


TCMs saved via DMA TCMs not saved

Entry(cycles)

Exit(cycles)

Entry(cycles)

Exit(cycles)






Reduce counts through code optimization

The example code is generic and can be used for many different implementation options, such as varying cache and TCM sizes, presence or absence of TCMs, DMA, and VFP, and inclusion of two additional coprocessors. For a specific implementation, many of these options are fixed, and the save and restore code can be optimized to match the implementation. For example, if you have no coprocessors or VFP, you can remove the code that tests for the presence of these and saves their state.

The example code assumes that all state is variable and must be saved and restored for Dormant or Shutdown Mode. In a real system, it is likely that on Reset the operating system sets up some aspects of the processor’s state that are static and never change. This static state does not need to be saved for Dormant or Shutdown Mode. On exit, the operating system can rerun the code that sets up this static state, and avoid reading state and long memory writes and reads.

There can be some state that is not necessary to save and restore because it controls a feature that is not used. In this case you can optimize the save and restore code so it does not save and restore this state. For example, if you never use the TLB lockdown feature, you can remove the code that saves and restores the TLB lockdown registers. This removes 32 MCR or MRC instructions on both entry and exit, as well as removing 24 word reads or writes to memory. Similarly, if you do not need to preserve the contents of TCMs when you enter Shutdown Mode, there is no need to write their contents to main memory. The example cycle counts show both examples: writing the contents of the TCMs to main memory and not writing the contents of the TCMs to main memory.


4 State to be Saved

Table 9 lists the system state and the ARM Limited recommended order in which it must be saved in the transition to Dormant or Shutdown Mode on the ARM11 core. The reverse sequence must occur when restoring the processor state from Dormant or Shutdown Mode to Run Mode.

Table 9 State to be saved on entry to Dormant or Shutdown Mode

State Words ARM1136 ARM1176 Notes

CPSR 1 Y Y

General purpose registers: r0-r14(System and User modes)

15 Y Y

SPSRs: FIQ, IRQ, Undefined, Abort, Supervisor

5 Y Y Change to each modeto read its SPSR

Banked registers: FIQ r8-r14, IRQ r13-r14, Undefined r13-r14, Abortr13-r14, Supervisor r13-r14

15 Y Y Change to each modeto read its bankedregisters

TrustZone SPSR: Monitor 1 - Y TrustZone registers

TrustZone banked registers: Monitorr13-r14

2 - Y

CP15 Secure Configuration Register 1 - Y

CP15 TLB Lockdown Register 1 Y Y After save, clear bit [0]to avoid changing theTLB lockdown region

CP15 Secure Debug Enable Register 1 - Y TrustZone registers

CP15 Non-secure Access ControlRegister

1 - Y

CP15 (Secure) Data Fault StatusRegister

1 Y Y Secure version on ARM1176

CP15 (Secure) Instruction Fault StatusRegister

1 Y Y

CP15 (Secure) Fault Address Register 1 Y Y

CP15 (Secure) Instruction Fault AddressRegister

1 Y Y


CP15 Secure PA Register 1 - Y TrustZone register

CP15 Secure TCM SelectionRegister

1 - Y Register in ARM1176only

CP15 (Secure) User Read/WriteThread and Process ID Register

1 ? Y Register in ARM1136from r1p0 onwardsSecure version onARM1176CP15 (Secure) User Read Only

Thread and Process ID Register1 ? Y

CP15 (Secure) Privileged OnlyThread and Process ID Register

1 ? Y

CP15 Non-secure Cache DirtyStatus Register

1 - Y TrustZone registers

CP15 Non-secure Control Register 1 - Y

CP15 Non-secure Translation TableBase Registers 0-1

2 - Y

CP15 Non-secure Translation TableBase Control Register

1 - Y

CP15 Non-secure Domain AccessControl Register

1 - Y

CP15 Non-secure FCSE PIDRegister

1 - Y

CP15 Non-secure Context IDRegister

1 - Y

CP15 Non-secure Primary Region Remap Register

1 - Y

CP15 Non-secure Normal MemoryRemap Register

1 - Y

CP15 Non-secure Peripheral PortMemory Remap Register

1 - Y

CP15 Non-secure Data Fault StatusRegister

1 - Y

Table 9 State to be saved on entry to Dormant or Shutdown Mode (continued)



CP15 Non-secure Instruction FaultStatus Register

1 - Y TrustZone registers

CP15 Non-secure Fault AddressRegister

1 - Y

CP15 Non-secure Instruction FaultAddress Register

1 - Y

CP15 Non-secure PA Register 1 - Y

CP15 Non-secure TCM SelectionRegister

1 - Y

CP15 Non-secure User Read/WriteThread and Process ID Register

1 - Y

CP15 Non-secure User Read OnlyThread and Process ID Register

1 - Y

CP15 Non-secure Privileged OnlyThread and Process ID Register

1 - Y

CP15 Non-secure Vector BaseAddress Register

1 - Y

CP15 Auxiliary Control Register 1 Y Y

CP15 Coprocessor Access Control Register

1 Y Y

CP15 DMA User Accessibility Register 1 Y Y If ARM internal DMAengine is present

CP15 DMA Channel Number Register 1 Y Y

CP15 DMA Channel Status Registerfor each DMA channel

2 Y Y If ARM internal DMAengine is present. UseDMA Channel NumberRegister to select aDMA channel. Save DMAchannel status then stopthe DMA channel. Whenrestoring, if the status wasRunning or Queued,restart the DMA channel.




CP15 DMA Control Registerfor each DMA channel

2 Y Y If ARM internal DMA engineis present. Use DMA ChannelNumber Register to select aDMA channel.CP15 DMA Internal Start Address

Register for each DMA channel2 Y Y

CP15 DMA External Start AddressRegister for each DMA channel

2 Y Y

CP15 DMA Internal End AddressRegister for each DMA channel

2 Y Y

CP15 DMA Context ID Registerfor each DMA channel

2 Y Y

CP14 Jazelle OS Control Register 1 - - Do not save or restore the Jazelle DBX registers because these registers are managed by the Java Virtual Machine. Faulty register restoration can result in incorrect operation of the Java Virtual Machine.

CP14 Jazelle Configuration Register 1 - -

CP14 Jazelle Parameters Register 1 - -

CP15 TLB Lockdown IndexRegister

1 - Y Register in ARM1176only

CP15 TLB VA, PA and Attributesregisters for all 8 TLB lockdownregion entries

24 Y Y ARM1136: use CP15 ReadMain TLB Entry Register toread each entryARM1176: use CP15 TLBLockdown Index Register toselect each entry to read.

State of any memory-mapped

peripherals

Y Y Implementation defined




VFP control registers: VFPException, VFP Status and Control,VFP Instruction, and VFPInstruction 2 registers

4 Y Y If VFP is present. Beforeaccessing these registers,enable access to the VFPcoprocessor by setting bits[23:20] of the CoprocessorAccess Control Register, andenable the VFP by setting bit[30] of the VFP ExceptionRegister once it has beensaved.

VFP data registers: D0-D15 / S0-S31 32 Y Y

State of any other coprocessors Y Y Implementation defined

CP15 Performance Monitor ControlRegister

1 Y Y

CP15 Cycle Counter Register 1 Y Y

CP15 Count Registers 0-1 2 Y Y

CP14 Debug Status and ControlRegister

1 Y Y

CP14 Breakpoint Value registers 0-5 6 Y Y Before accessing theseregisters, enable DebugMonitor Mode by writing theCP14 Debug Status andControl Register with bit[15] set and bit [14] clear.

CP14 Breakpoint Control registers 0-5 6 Y Y

CP14 Watchpoint Value registers 0-1 2 Y Y

CP14 Watchpoint Control registers 0-1 2 Y Y

CP14 Watchpoint Fault Address Register 1 - Y Register in ARM1176 only. Before accessing thisregister, enable DebugMonitor Mode by writing theCP14 Debug Status andControl Register with bit[15] set and bit [14] clear.

CP14 Vector Catch Register 6 Y Y Before accessing theseregisters, enable DebugMonitor Mode by writing theCP14 Debug Status andControl Register with bit[15] set and bit [14] clear.




CP14 Debug State Cache ControlRegister

1 - Y Register in ARM1176 only. Before accessing theseregisters, enable DebugMonitor Mode by writing theCP14 Debug Status andControl Register with bit[15] set and bit [14] clear.

CP14 Debug State MMU ControlRegister

1 - Y

Secure Vector Base Address Register 1 - Y TrustZone registers

Monitor Vector Base AddressRegister

1 - Y

CP15 (Secure) Control Register 1 Y Y Secure version on ARM1176

CP15 (Secure) Translation Table Base Registers 0-1

2 Y Y

CP15 (Secure) Translation Table BaseControl Register

1 Y Y

CP15 (Secure) Domain AccessControl Register

1 Y Y

CP15 (Secure) FCSE PID Register 1 Y Y

CP15 (Secure) Context ID Register 1 Y Y

CP15 (Secure) Primary RegionRemap Register

1 ? Y Register in ARM1136from r1p0 onwards. Secure version on ARM1176.

CP15 (Secure) Normal MemoryRemap Register

1 ? Y

CP15 Data Memory Remap Register 1 Y - Registers in ARM1136 only

CP15 DMA Memory RemapRegister

1 Y -

CP15 Instruction Memory RemapRegister

1 Y -

CP15 (Secure) Peripheral PortMemory Remap Register

1 Y Y Secure version onARM1176




CP15 Data Cache LockdownRegister

1 Y Y Dormant Mode only; forShutdown Mode, on exit theOS must set up cachelockdown as required.CP15 Instruction Cache Lockdown

Register1 Y Y

CP15 Cache Behavior OverrideRegister

1 - Y TrustZone register

CP15 Data Cache Master ValidRegisters

1-8 Y Y Dormant Mode only. Numberof words is dependent on thedata cache size.

CP15 Instruction Cache MasterValid Registers

1-8 Y Y Dormant Mode only. Number of words is dependent on the instruction cache size.

CP15 Data SmartCache MasterValid Registers

0-8 ? - Registers in ARM1136 only. Dormant Mode only. Only required if the data TCM is enabled as SmartCache. Number of words is dependent on the data TCM size.

CP15 Instruction SmartCacheMaster Valid Registers

0-8 ? - Registers in ARM1136 only. Dormant Mode only. Only required if the instruction TCM is enabled as SmartCache. Number of words is dependent on the instruction TCM size.

CP15 Data TCM Region Register foreach data TCM

0-2 Y Y ARM1136 has 0 or 1 dataTCMs; ARM1176 has 0, 1or 2 data TCMs. ForARM1176, use CP15TCM Selection Register toselect a data TCM.




4.1 Dormant and Shutdown Mode Example Code

Example ARM assembler code files are provided in a zipped file accompanying this Application Note. They illustrate the Dormant and Shutdown Mode entry and exit procedures for ARM1136 and ARM1176 processors.

These files are provided as code examples only. They do not address all permutations of system configuration available. The files must be modified to match the specific system implementation of the user. Indications of required modifications are listed as comments within the example code.

The example code files are:

• arm1136-dormantMode-example_c.s

CP15 Instruction TCM RegionRegister for each instruction TCM

0-2 Y Y ARM1136 has 0 or 1 instruction TCMs; ARM1176 has 0, 1 or 2 instruction TCMs. For ARM1176, use CP15 TCM Selection Register to select an instruction TCM.

CP15 Data TCM Non-secure ControlAccess Register for each data TCM

0-2 - Y Registers in ARM1176 only. ARM1176 has 0, 1 or 2 data TCMs. Use CP15 TCM Selection Register to select a data TCM.

CP15 Instruction TCM Non-secureControl Access Register for eachinstruction TCM

0-2 - Y Registers in ARM1176only. ARM1176 has 0, 1or 2 instruction TCMs.Use CP15 TCM SelectionRegister to select aninstruction TCM.

CP15 Main TLB Master Valid Registers 0 or 2 ? - Registers in ARM1136 only. Dormant Mode only. Only required if the Main TLB RAMs are powered up during Dormant Mode.

Memory address at which state information is saved

1 Y Y Save this at a known fixed address.




• arm1136-shutdownMode-example_c.s

• arm1176-dormantMode-example_c.s

• arm1176-shutdownMode-example_c.s.


understanding arm11 processor power saving modes...

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