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UNIT 1 Part (a)INTRODUCTION

HARDWARE DESCRIPTION LANGUAGES (HDLs)(i). ABEL(ii). VHDL(iii). Verilog HDL

HDL is a way of design entry. In this, the hardware for complete design is described and isgiven to computer in the form of programs. These are used to describe the hardware for thepurpose of

(i). Simulation(ii). Modeling(iii). Testing(iv). Design(v). Documentation

These languages provide a convenient and compact format for the hierarchical representationof functional and wiring details of digital systems. Some HDL consists of a simple set ofsymbols and notations that replace schematic diagrams of digital circuits, while others aremore formally defined and may present the network at one or more levels of abstraction.Available software for HDLs include simulations and network synthesis programs. Asimulation program can be used for design verification, while a synthesizer is used forautomatic network generation. A test generation program may depend on a HDL forproviding it with a netlist format, test applications test bench and fault inspection.

VHDL

V stands for (VHSIC) Very High Speed Integrated Circuit and HDL stands for HardwareDescription Language. VHDL is a hardware description language that can be used to model adigital system. The digital system can be as simple as a logic gate or as complex as acomplete electronic system or anything in between. The VHDL language can be regarded asan integrated amalgamation of the following languages:

(i). Sequential Language(ii). Concurrent Language(iii). Net List Language(iv). Timing Specification(v). Waveform Generation Language

Therefore, the language has constructs that enable you to explain the concurrent or sequentialbehavior of a digital system with or without timing. It also allows to model the system as aninterconnection of components. Test waveforms can also be generated using the sameconstructs. All these constructs may be combined to provide a comprehensive description ofthe system in a single model. The language not only defines the syntax but also defines veryclear simulation semantics for each language constructs. VHDL is a strongly typed languagethat can be used to verify the models.

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HISTORYFor the designing of large digital systems, much engineering time is spent in changingformats for using various design aids and simulators. As the design process advances,additional details are added to the initial description of part. These details enables thesimulation and testing of system at various levels of abstraction. By the last stage of design,the initial description has evolved into a detailed description which can be used by a programcontrolled machine for generation of final hardware in the form of layout, printed circuitboard (PCB) or gate arrays.

This ideal design process can exist only if a language exist to describe network at variouslevels so that it can be understood by the users, designers, testers, simulators and machines.The IEEE standard VHDL is such a language.

VHDL was defined because a need existed for an integrated design and documentationlanguage to communicate design data between various levels of abstraction.

VHDL Initiation

Many different HDLs were used in different IC manufacturing companies in late 1970s andbeginning of 1980s. Due to this, different vendors could not exchange designs with oneanother and different vendors provided Department of Defense (DoD), USA with descriptionof chips in different HDLs. So the reprocurement and reuse of chip design was a big issue.So, DoD realized the need of a standardized HDL for the design, documentation andverification of the digital systems. This came to be known as VHSIC program.

1981: In the summer of 1981, a workshop on HDLs was sponsored by Department ofDefense (DoD), USA. The main topics of study in this workshop arranged by Institute ofDefense Analysis (IDA) were:

(i). Study of various hardware description methods(ii). Need for a standard language(iii). Features required by this standard language

1983: In 1983, DoD established requirements for a standard VHSIC HardwareDescription Language (VHDL), based on the recommendations of the workshop held in1981. The contract for development of VHDL language, its environment and its softwarewas awarded to three companies IBM, Texas Instruments and Intermetrices to completethe specification and implementation.

Release of VHDL 2.0: It was released only 6 months after project began. This versionallowed only concurrent statements, not the sequential statements i.e. it lacked thecapability to describe hardware in a sequential software like fashion. Language wassignificantly improved and other shortcomings were corrected.

1984: VHDL 6.0 was released in December of 1984. Hence forth, development of VHDLbased tools began in 1984.

1985: Till 1984, VHDL programs were under control of ITAR (International Traffic andArms Regulation), USA. But in 1985, VHDL related software and VHDL 7.2 LanguageReference Manual (LRM) copyright was transferred to IEEE for further development andstandardization. This led to development of IEEE 1076/A VHDL LRM, which was

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released in May of 1987. VHDL 7.2 was first publicly available version. After thisrelease, it was again realized that the language must be an industrial standard.

1986: The copyrights of language were transferred to IEEE for standardization in 1986. 1987: Later in 1987, Version 8 of LRM was developed and approved by REVCOM (a

committee of the IEEE standards board). VHDL 1076 1987 formally become the IEEEstandard HDL in December of 1987. This standard is virtually the basis for everysimulation and synthesis products add today.

1993: VHDL standards 1076 1993 was released for review. 1994: VHDL was released for the public use. The present VHDL standard is formally

referred to as VHDL 1076 1993.

WHY USE VHDL? or VHDL ADVANTAGES orCAPABILITIESWith VHDL, every design engineer in the electronics industry can quickly describe andsynthesize circuit of n number of gates. Equivalent designs described with schematics orBoolean equations at the Register Transfer Level (RTL) can require several months of workby one person. In addition, VHDL provides the capabilities described below:

(1). Power and Flexibility:(i). VHDL is one language for design and simulation.(ii). VHDL has powerful language constructs with which we can write brief code

description of complex logic circuits very well.(iii). It supports design libraries and creation of reusable components.(iv). It provides design hierarchy to create modular designs.

(2). Device Independent Design:(i). VHDL permits us to create a design without having to first choose a device for

implementation.(ii). User does not need to become immediately familiar with devices architecture

in order to optimize our design for resource utilization or performance.(iii). With one design description, we can target many device architectures.(iv). VHDL permits multiple styles of design description e.g. a 2 bit comparator

(a). aeqb

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(4). ASIC Migration: (Application Specified Integrated Circuit)(i). The efficiency that VHDL generates allow the product to hit the market

quickly if the design is synthesize on CPLD and FPGA.(ii). When the production reach appropriate levels, VHDL facilitates the

development of an ASIC.(iii). The same VHDL code that was being used for CPLD / FPGA is usable for

ASICs.(5). Quick Time to Market and Low Cost:

(i). VHDL and programmable logic pair well together facilitates speedy designprocess.

(ii). VHDL and programmable logic devices combine as a powerful vehicle tobeing the products in market in record time.

(6). VHDL supports both synchronous and asynchronous circuits.(7). IEEE Standard: Model described using this language are portable.(8). Reusability of design.(9). Documentation.(10). Description Styles: VHDL language supports three basic different description

styles namely(i). Dataflow(ii). Behavioral(iii). Structural A design may also be expressed in any combination of these three

descriptive styles.(iv).

HARDWARE DESIGN CONSTRUCTIONThe design of a digital system is a process that starts from the specification of requirementsand produce a functional design that is eventually refined through a sequence of steps to aphysical implementation. An initial design idea goes through several transformation, thedesigner checks the result of last transformation, adds more information to it, and passes itthrough the next step of transformation. Both simulation and synthesis are complementaryactivities employed in design process although the specific relationship is a function of targetimplementation. Certain steps in the development cycle must be performed if the finalproduct is to meet the specified objectives.

The flow chart shows the process. Most obvious requirements are that the product mustfunction properly that it must meet an expected level of performance and that its cost shouldnot exceed a given target.

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Figure 2. Flowchart for Development Process.

Design Process:

Step I: Behavioral Design:Initially, a hardware designer starts with a design idea. A technically complete definition ofthe intended hardware is developed from the initial design idea. Therefore, it is necessary forthe designer to generate a behavioral definition of the system under design. The result of thisdesign stage is a flowchart or graphs or a truth table. The designer specifies the overallfunctionality and Input / Output mapping without giving architecture / hardware details of thesystems.

Step II: Datapath Design:The next step in the design process is the design of datapath system. The designer herespecifies the registers and logic units required for the implementation of the system.According to the behavior of the system, the component may be interconnected using eitherbidirectional or unidirectional buses. These connections are known as datapath. Datacomponents in the data part of a circuit communicate with system buses and the controlprocedure control flow of data between these components.Figure shows a possible result of the data path design phase. No information about theimplementation of the controller e.g. hardwired, encoding technique or micro programmedis given in this step.

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Figure 3. Result of Datapath Design Phase.

Step III: Logic Design:Logic design phase involves the use of primitives gates and flip flops for theimplementation of data registers, logic units and their controlling hardware. The result of thisdeign stage is a netlist of gates and flip flops. Components used and their interconnectionare specified in this netlist. Gate technology and gate - level details of flip flops are notincluded in the netlist.

Step IV: Phase Design or Transistor Layout:It transforms the netlist of the previous stage into a transistor list or layout. This involves thereplacement of gates and flip flops with their transistor equivalents or library cells. Thisstage considers loading and timing requirements in its cell or transistor selection process.

Step V: Manufacturing:This step uses the transistor list or layout obtained in step 4 to burn fuses of a FPGA deviceor to generate masks for integrated circuit (IC) fabrication.In the design process, much of the work of transforming a design from one form to another istedious and can be done much faster by a machine than a human being.

Figure 4. Design Process.

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DESIGN LEVELS OR LEVELS OF ABSTRACTIONSIt is also known as styles of modeling or levels of abstraction. A hardware designer models acircuit using any available tools. The level of abstraction for the modeling depends on thepurpose for which the model is intended. If the model is to be used for documenting thefunctionality of a circuit at a very abstract behavioral level, a relatively simple abstract modelis necessary, on the other hand, if the model is to be used for verification of the timing of thecircuit, a more detailed description is needed.There are various levels of abstraction of hardware in VHDL:

(1). Behavioral Level(2). Dataflow Level(3). Structural Level

(1). Behavioral Level: In this modeling style, the behavior of the entity is expressed using sequentially

executed, procedural code, which is very similar in syntax and semantics to thatof a high level programming language like C or Pascal.

Behavioral description is the most abstract description. It describes the function of the design in a software like procedure form &

provides no details as to how the design is to be implemented. The behavioral level of abstraction is most appropriate for fast simulation of

complex hardware units, verification and functional simulation of design ideas,modeling standard components & documentation.

For simulation and functional analysis, a behavioral model is useful since thedetails of the hardware, which may not be known to the user of the components,are not required. Such descriptions present an I / O mapping according to thedata sheet specification provided by the manufacturer.

Description at this level can be accessible to non engineers as well as to the endusers of a hardware components and can also serve as a good documentationmedia. The operation of large systems can also be modeled at this level for endusers.

(2). Dataflow Level: A dataflow model specifies the functionality of the entity without explicitly

specifying its structure. This functionality shows the flow of informationthrough the entity, which is expressed primarily using concurrent signalassignment statements.

Dataflow description is a concurrent representation of the flow of control andmovement of data.

The level of hardware detail involved in dataflow description is great enoughthat such descriptions can not serve as an end user or non technicaldocumentation media.

The level of description is abstract enough for a technically oriented designer todescribe the components to be synthesized.

Simulation of these descriptions involves the movement of the data throughregisters and buses and therefore is slower than the I / O mapping of behavioraldescription.

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(3). Structural Level: In this style of modeling an entity is modeled as a set of components connected

by signals. Structural description is the lowest and most detailed level of description. It is simplest to synthesize into hardware. It includes a list of concurrently active components and their interconnections. The hardware is implied by these description and a simple printed circuit

board layout generator can easily produce the described hardware. Structural description that describes the wiring of logic gates is said to be the

hardware description at gate level. A gate level description provides input fordetailed timing simulation.

HDLs HARDWARE SIMULATIONHDLs are modeling tools for creating hardware model, one such phenomenon is hardwaresimulation. Simulation is the act of exercising a model of an actual component for analyzingthe conduct under a given set of conditions and / or stimuli.

A simulator sun requires a model of the object being simulated and a set of stimuli foractivating or stimulating the conduct of the object being studied. In a hardware designenvironment, a hardware description uses component models and definitions from asimulation library to form a simulatable hardware model.

In the figure, hardware description model is the program that the user has written andcomponent library tells the inclusion of previously described components. These are includedinto one program and passed as one input to the simulation engine or simulator. The secondinput to the simulator is the stimuli or the test data. The output of the simulator indicates theconduct of the hardware component for given set of test data.

Figure 5. Hardware Simulation.

Output of the Simulation Engine or Simulator:A simulator may be capable of producing detailed timing and analog voltages, or it may beable to produce high level function information. The output generated by this simulatoractually depends on the level of details of the hardware model presented to it.Depending on the levels of designing, there are two kinds of simulation:

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(1). Functional Simulation(2). Timing Simulation(1). Functional Simulation:

When the output of the simulator covers most of the logical errors in the design, it issaid to be functional simulation.

This simulation ignores the detailed timing characteristics of design at the upper levelsof design process, simulation provides information regarding the functionality of systemunder design. Simulators for this purpose normally undergo a very quick run on theirhost computers. Simulation at lower level of design process, e.g. gate level, runs muchmore slowly but provides more detailed information about timing and functionality ofthe circuit.

To avoid the high cost of low level simulation runs, simulators should be used todetect design flows as early in the design process as possible.

(2). Timing Simulation:When the designer moves on to the implementation phase and the design has beensynthesized into some lower level, technology specific representation (such as FPGA /ASIC netlist), the design needs to be simulated again using the timing details as input.Simulation at this level is known as timing simulation and can help in identifying errorsrelated to actual timing delays and can also verify to a high degree of accuracy that thefinal chip will work in the circuit. At this level, the simulator runs much more slowlybut provides more detailed information about the timing and functionality of the circuit.

Regardless of the level of designing, the digital system simulators have been divided into twocategories:(1). Oblivious Simulation(2). Event driven Simulation(1). Oblivious Simulation:

In this type of simulation, each circuit component is evaluated at fixed time points. Thistakes place in two phases:

(i). Phase I: Initialization Phase:This phase converts the input circuit description to a machine readable tabularform. This table contains information regarding the circuit components and theirinterconnections, as well as the initial values for all the nodes of the circuit.

Consider an example of XOR gate ( BABA + )

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Logical diagram for XOR gate:

Test Data:

Tabular Representation of XOR gate:Gate Function Input 1 Input 2 Value

at T = 0Value

at T = 51 Input A - 0 12 Input B - 0 13 NOT 2 - 1 04 NOT 1 - 1 05 AND 1 3 0 06 AND 2 4 0 07 OR 5 6 0 0

(ii). Phase II:After initialization, this method reads input values at fixed time intervals, applyingthem to the internal tabular representation of the circuit.

At time Ti, input values of A and B are read from an input file. These valuesreplace the old values of A and B in value column. Using these new values, theoutput values of all circuit components will be re evaluated and changes will bemade to the value column of the affected components.

(2). Event Driven Simulation:Event driven simulation is more complex than oblivious simulation. It is a moreefficient method of digital system simulation. In this type of simulation, a component isevaluated only when one of its inputs changes. In event driven simulation, when an

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input is changed, only those nodes that are affected are re evaluated. Event is a changein input value from 0 to 1 or from 1 to 0. This simulation takes place in two phases:

(i). Phase I:This phase converts the circuit description to a linked list data structure.

Link List:

The link list for XOR gate is as shown below:

(ii). Phase II:In the 2nd phase, a change on an input triggers only those nodes of the linked listfor which an input changes, e.g. at T = 2, A changes from 0 to 1, this node feeds3 and 6, therefore they will also evaluated and so on.

Event driven simulation does not evaluate circuit nodes until there is a change ininput, when an event occurs on an input, affected nodes only are re evaluatedand all other nodes values will be unchanged.

Since activities occur only on relatively small portions of digital circuits,evaluation of all nodes at all times; as done in oblivious simulation is necessary.

Event driven simulation is more suitable method for digital systems. The speedof this method justifies its more complex data structure and algorithm.

HDLs HARDWARE SYNTHESISA design aid that automatically transforms a design description from one form to another iscalled a synthesis tool. HDLs are useful media for input and output of hardware synthesis.Synthesis is a design process that operates on three types of information:(1). Model of the circuit, which in our case is a VHDL model.(2). Set of constraints on the resulting circuit such as speed and area.(3). Set of components that are to be used to construct the circuit.

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Synthesis compilers must operate with these three pieces of information. Figure shows ablock diagram of a register transfer level synthesis tool.

Figure 6. Synthesis Process.

Synthesize Hardware Description is a FPGA program file formats that can be fed to aprogrammer, synthesis engine concentrate on resource sharing, logic optimization andbinding.

Logic unit performing register transfer level operations are resources that can be sharedbetween multiple instances of the same operation. If the same operation is used with the sameinputs, the sharing is simple and the output of the logic unit will be used in severaldestinations. An operation used in several instances with different inputs requires the use ofmultiplexers for providing it with appropriate sets of inputs.

Resource sharing may be directed by a synthesis tool user through synthesis directives. Forexample as shown in figure, an add operation on register outputs A and B, placing theresult on bus C, in one instance and other operation adding the same inputs and placing theresults on bus D, can share the same adder unit without any hardware overhead. On theother hand, if the two instances of add operations use different inputs e.g. A and B in oneinstance and X and Y in another, multiplexers should be used for adder unit inputselections.

Figure 7. Resource Sharing.

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In the logic optimization, Boolean expressions are manipulated for better utilization of FPGAcells or chip area. The binding phase in a synthesis tool maps operations of an intermediatedata structure (often in the form of Binary Decision Diagram (BDD)), to predefined binarycells of a target hardware.

USING VHDL FOR DESIGN SYNTHESISOne of the best uses of the VHDL is to synthesize ASIC FPGA device. Synthesis is anautomatic method of converting higher level of abstraction to a lower level of abstraction.

The current synthesis tools available convert Register transfer Level (RTL) descriptions togate level netlist. These gate level netlist consists of interconnected gate level macro cells.

The design process can be broken into the six steps:1. Define the design requirements2. Describe the design in VHDL (formulate and code the design)3. Simulate the source code4. Synthesize, optimize and fit (place and route) the design5. Simulate the post layout (fit) design model6. Program the device

1. Define the Design Requirements:

Before launching into writing code for the design, we have to clear the idea of designobjectives, requirements, function of the design, required setup, clock cycle, maximumfrequency of operation etc. Having a clear idea of the requirements may help to choose adesign methodology and the device architecture to which we will initially synthesize ourdesign.

2. Describe the Design in VHDL:a). Formulate the Design:

By having the design requirements, we will tend to write the code efficiently. Thereare three methodologies for creating a design:

(i). Top down(ii). Bottom up

(iii). Flat

The first two methods involve creating design hierarchies, the last method involvesdescribing the circuit as a monolithic design.

The top down approach divide the design into functional components, eachcomponents having specific inputs and outputs and performing a particular function.

A top level module is created to tie the design components together, as is a netlist,then the components themselves are designed.

The bottom up approach involves just the opposite i.e. defining and designing theindividual components, then bringing the pieces together to form the overall design.

A flat design is one in which the details of functional components are defined at thesame level as the interconnection of those functional components, flat designs workwell for small designs.

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Hierarchical schemes use in large designs consisting of multiple complex functionalcomponents.

b). Code the Design:After deciding the design methodology, we can code the design using dataflow andstate diagram. The dataflow and state diagrams uses syntax and semantics forcoding the design.

A syntax in any programming language is a set of grammatical rules that governshow a model is written, where as semantics governs the meaning of a program.

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UNIT I Part(b)PROGRAMMABLE LOGIC DEVICE

WHY USE PROGRAMMABLE LOGIC?Logic devices can be classified into two broad categories fixed and programmable. As thename suggests, the circuits in a fixed logic device are permanent, they perform one functionor set of functions once manufactured, they cannot be changed. On the other hand,programmable logic devices (PLDs) are standard, off the shelf parts that offer customers awide range of logic capacity, features, speed and voltage characteristics and these devices canbe changed at any time to perform any number of functions.With fixed logic devices, the time required to go from design, to prototypes, to a finalmanufacturing run can take from several months to more than a year, depending on thecomplexity of the devices. And, if the device does not work properly, or if the requirementschange, a new design must be developed. The up front work of designing and verifyingfixed logic devices involves substantial non recurring engineering costs or NRE. NRErepresents all the costs customers incur before the final fixed logic device emerges from asilicon foundry, including engineering resources, expensive software design tools, expensivephotolithography mask sets for manufacturing the various metal layers of the chip and thecost of initial prototype devices. These NRE costs can run from a few hundred thousand toseveral million dollars.With programmable logic devices, designers use inexpensive software tools to quicklydevelop, simulate and test their designs. Then a design can be quickly programmed into adevice and immediately tested in a live circuit. The PLD that is used for this prototyping isthe exact same PLD that will be used in the final production of a piece of an equipment, suchas a network router a DSL (Digital Subscriber Line), Modem, a DVD Player, or anautomotive navigation system. There are no NRE costs and the final design is completedmuch faster than that of a custom, fixed logic device.Another key benefit of using PLDs is that during the design phase customers can change thecircuitry as often as they want until the design operates to their satisfaction. Thats becausePLDs are based on re-writable technology to change the design, the device is simplyreprogrammed. Once the design is final, the customers can go into immediate production bysimply programming as many PLDs as they need with the final software design file.In brief, PLDs have following advantages and disadvantages over fixed logic.Advantages

Short design cycle Low production cost High density Easy programming

Disadvantages Reduction in board space requirements Reduction in power requirements Design security Comapct circuitry Higher switching speed

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PROGRAMMABLE LOGIC DEVICE (PLD)The function provided by each of the 7400-series parts is fixed and cannot be tailored to suita particular design situation. This fact, coupled with the limitation that each chip containsonly a few logic gates, makes these chips inefficient for building large logic circuits. It ispossible to manufacture chips that contain relatively large amounts of logic circuitry with astructure that is not fixed. Such chips were first introduced in the 1970s and are calledprogrammable logic devices (PLDs).

A PLD is a general-purpose chip for implementing logic circuitry. It contains a collection oflogic circuit elements that can be customized in different ways, A PLD can be viewed as a"black box" that contains logic gates and programmable switches, as illustrated in Figure 1.below. The programmable switches allow the logic gates inside the PLD to be connectedtogether to implement whatever logic circuit is needed.

Figure 1. Programmable Logic Device as a Black Box.

1.1. PROGRAMMABLE LOGIC ARRAYS (PLA)Several types of PLDs are commercially available. The first developed was the programmablelogic array (PLA). The general structure of a PLA is depicted in Figure 2. Based on the ideathat logic functions can be realized in sum-of-products form, a PLA comprises a collection ofAND gates that feeds a set of OR gates. As shown in the Figure 2, the PLA's inputs x1, x2, ..,xn pass through a set of buffers (which provide both the true value and complement of eachinput) into a circuit block called an AND plane, or AND array. The AND plane produces a setof product terms P1, P2, .., Pk. Each of these terms can be configured to implement any ANDfunction of x1, x2, .., xn. The product terms serve as the inputs to an OR plane, whichproduces the outputs f1, f2, .., fm. Each output can be configured to realize any sum of P1, P2,.., Pk and hence any sum-of-products function of the PLA inputs.

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Figure 2. General Structure of a PLA.

A more detailed diagram of a small PLA is given in Figure 3, which shows a PLA with threeinputs, four product terms, and two outputs. Each AND gate in the AND plane has sixinputs, corresponding to the true and complemented versions of the three input signals. Eachconnection to an AND gate is programmable; a signal that is connected to an AND gate isindicated with a wavy line, and a signal that is not connected to the gate is shown with abroken line. The circuitry is designed such that any unconnected AND-gate inputs do notaffect the output of the AND gate. In commercially available PLAs, several methods ofrealizing the programmable connections exist.In Figure 3, the AND gate that produces P1 is shown connected to the inputs x1 and x2 .Hence P1 = x1 x2 . Similarly, P2 = x1 , P3 = x3 , and P4 = x1 x3. Programmableconnections also exist for the OR plane. Output f1 is connected to product terms P1, P2 , andP3. It therefore realizes the function f1 = x1 x2 + x1 + x3 . Similarly, output f2 =x1 x2 + x3 + x1 x3. Although Figure 3, depicts the PLA programmed to implementthe functions described above, by programming the AND and OR planes differently, each ofthe outputs f1 and f2 could implement various functions of x1 , x2 and x3 . The onlyconstraint on the functions that can be implemented is the size of the AND plane because itproduces only four product terms. Commercially available PLAs come in larger sizes.Typical parameters are 16 inputs, 32 product terms, and eight outputs.

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Figure 3. Gate Level Diagram of a PLA.

Although Figure 3, illustrates clearly the functional structure of a PLA, this style of drawingis awkward for larger chips. Instead, it has become customary in technical literature to usethe style shown in Figure 4. Each AND gate is depicted as a single horizontal line attached toan AND-gate symbol. The possible inputs to the AND gate are drawn as vertical lines thatcross the horizontal line. At any crossing of a vertical and horizontal line, a programmableconnection, indicated by an X, can be made. Figure 4 shows the programmable connectionsneeded to implement the product terms in Figure 3. Each OR gate is drawn in a similarmanner, with a vertical line attached to an OR-gate symbol. The AND-gate outputs crossthese lines, and corresponding programmable connections can be formed. The figureillustrates the programmable connections that produce the functions f1 and f2 from Figure 3.

The PLA is efficient in terms of the area needed for its implementation on an integratedcircuit chip. For this reason, PLAs are often included as part of larger chips, such asmicroprocessors. In this case a PLA is created so that the connections to the AND and ORgates are fixed, rather than programmable.

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Figure 4. Customary Schematic for the PLA in Figure 3.

1.2. PROGRAMMABLE ARRAY LOGIC (PAL)In a PLA both the AND and OR planes are programmable. Historically, the programmableswitches presented two difficulties for manufacturers of these devices: they were hard tofabricate correctly, and they reduced the speed-performance of circuits implemented in thePLAs. These drawbacks led to the development of a similar device in which the AND planeis programmable, but the OR plane is fixed. Such a chip is known as a programmable arraylogic (PAL) device. Because they are simpler to manufacture, and thus less expensive thanPLAs, and offer better performance, PALs have become popular in practical applications.

An example of a PAL with three inputs, four product terms, and two outputs is given inFigure 5. The product terms P1 and P2 are hardwired to one OR gate, and P3 and P4 arehardwired to the other OR gate. The PAL is shown programmed to realize the two logicfunctions f1 = x1 x2 + x2 x3 , and f2 = + x1 x2 x3 . In comparison to the PLA inFigure 4, the PAL offers less flexibility; the PLA allows up to four product terms per ORgate, whereas the OR gates in the PAL have only two inputs. To compensate for the reducedflexibility, PALs are manufactured in a range of sizes, with various numbers of inputs andoutputs, and different numbers of inputs to the OR gates.

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Figure 5. An example of a PAL.

So far we have assumed that the OR gates in a PAL, as in a PLA, connect directly to theoutput pins of the chip. In many PALs extra circuitry is added at the output of each OR gateto provide additional flexibility. It is customary to use the term macrocell to refer to the ORgate combined with the extra circuitry. An example of the flexibility that may be provided ina macrocell is given in Figure 6. The symbol labeled flip-flop represents a memory element.It stores the value produced by the OR gate output at a particular point in time and can holdthat value indefinitely. The flip-flop is controlled by the signal called clock. When clockmakes a transition from logic value 0 to 1, the flip-flop stores the value at its D input at thattime and this value appears at the flip-flop's Q output. Flip-flops are used for implementingmany types of logic circuits.

Figure 6. Extra Circuitry Added to OR Gate Outputs from Figure 5.

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In Figure 6, a 2-to-l multiplexer selects as an output from the PAL either the OR-gate outputor the flip-flop output. The multiplexer's select line can be programmed to be either 0 or 1.Figure 6 shows another logic gate, called a tri-state buffer, connected between the multiplexerand the PAL output. Finally, the multiplexer's output is "fed back" to the AND plane in thePAL. This feedback connection allows the logic function produced by the multiplexer to beused internally in the PAL, which allows the implementation of circuits that have multiplestages, or levels, of logic gates.

1.3. COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLD)

PLAs and PALs are useful for implementing a wide variety of small digital circuits. Eachdevice can be used to implement circuits that do not require more than the number of inputs,product terms, and outputs that are provided in the particular chip. These chips are limited tofairly modest sizes, typically supporting a combined number of inputs plus outputs of notmore than 32. For implementation of circuits that require more inputs and outputs, eithermultiple PLAs or PALs can be employed or else a more sophisticated type of chip, called acomplex programmable logic device (CPLD), can be used.

A CPLD comprises multiple circuit blocks on a single chip, with internal wiring resources toconnect the circuit blocks. Each circuit block is similar to a PLA or a PAL; we will refer tothe circuit blocks as PAL-like blocks. An example of a CPLD is given in Figure 7. below. Itincludes four PAL-like blocks that are connected to a set of interconnection wires. EachPAL-like block is also connected to a subcircuit labeled I/O block, which is attached to anumber of the chip's input and output pins.

Figure 7. Structure of Complex Programmable Logic Device (CPLD).

Figure 7. shows an example of the wiring structure and the connections to a PAL-like blockin a CPLD. The PAL-like block includes 3 macrocells (real CPLDs typically have about 16macrocells in a PAL-like block), each consisting of a four-input OR gate (real CPLDsusually provide between 5 and 20 inputs to each OR gate). The OR-gate output is connected

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to another type of logic gate that we have not yet introduced. It is called an Exclusive-OR(XOR) gate. The behavior of an XOR gate is the same as for an OR gate except that if bothof the inputs are 1, the XOR gate produces a 0. One input to the XOR gate in Figure 8, canbe programmably connected to 1 or 0; if 1, then the XOR gate complements the OR-gateoutput, and if 0, then the XOR gate has no effect. The macrocell also includes a flip-flop, amultiplexer, and a tri-state buffer. The flip-flop is used to store the output value produced bythe OR gate. Each tri-state buffer is connected to a pin on the CPLD package. The tri-statebuffer acts as a switch that allows each pin to be used either as an output from the CPLD oras an input. To use a pin as an output, the corresponding tri-state buffer is enabled, acting asa switch that is turned on. If the pin is to be used as an input, then the tri-state buffer isdisabled, acting as a switch that is turned off. In this case an external source can drive asignal onto the pin, which can be connected to other macrocells using the interconnectionwiring.

The interconnection wiring contains programmable switches that are used to connect thePAL-like blocks. Each of the horizontal wires can be connected to some of the vertical wiresthat it crosses, but not to all of them. Extensive research has been done to decide how manyswitches should be provided for connections between the wires. The number of switches ischosen to provide sufficient flexibility for typical circuits without wasting many switches inpractice. One detail to note is that when a pin is used as an input, the macrocell associatedwith that pin cannot be used and is therefore wasted. Some CPLDs include additionalconnections between the macrocells and the interconnection wiring that avoids wastingmacrocells in such situations.

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Figure 8. A Section of CPLD

Commercial CPLDs range in size from only 2 PAL-like blocks to more than 100 PAL- likeblocks. They are available in a variety of packages, including the PLCC package. Figure 9(a)shows another type of package used to house CPLD chips, called a quadflat pack (QFP). Likea PLCC package, the QFP package has pins on all four sides, but whereas the PLCC's pinswrap around the edges of the package, the QFP's pins extend outward from the package, witha downward-curving shape. The QFP's pins are much thinner than those on a PLCC, whichmeans that the package can support a larger number of pins; QFPs are available with morethan 200 pins, whereas PLCCs are limited to fewer than 100 pins.

Figure 9. CPLD Packaging and Programming

Most CPLDs contain the same type of programmable switches that are used in SPLDs.Programming of the switches may be accomplished using the technique in which the chip isplaced into a special- Purpose programming unit. However, this programming method israther inconvenient for large CPLDs for two reasons. First, large CPLDs may have more than200 pins on the chip package, and these pins are often fragile and easily bent. Second, to beprogrammed in a programming unit, a socket is required to hold the chip. Sockets for largeQFP packages are very expensive; they sometimes cost more than the CPLD device itself.For these reasons, CPLD devices usually support the ISP technique. A small connector isincluded on the PCB that houses the CPLD, and a cable is connected between that connectorand a computer system. The CPLD is programmed by transferring the programminginformation generated by a CAD system through the cable, from the computer into theCPLD. The circuitry on the CPLD that allows this type of programming has beenstandardized by the IEEE and is usually called a JTAGport. It uses four wires to transferinformation between the computer and the device being programmed. The term JTAG standsfor Joint Test Action Group. Figure 9(b) illustrates the use of a JTAG port for programming

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two CPLDs on a circuit board. The CPLDs are connected together so that both can beprogrammed using the same connection to the computer system. Once a CPLD isprogrammed, it retains the programmed state permanently, even when the power supply forthe chip is turned off. This property is called nonvolatile programming.

CPLDs are used for the implementation of many types of digital circuits. In industrial designsthat employ some type of PLD device, CPLDs are used often, while SPLDs are becomingless common. A number of companies offer competing CPLDs.

1.4. FIELD PROGRAMMABLE GATE ARRAY (FPGA)

The types of chips like 7400 series, SPLDs, and CPLDs, are useful for implementation of awide range of logic circuits. Except for CPLDs, these devices are rather small and aresuitable only for relatively simple applications. Even for CPLDs, only moderately large logiccircuits can be accommodated in a single chip. For cost and performance reasons, it isprudent to implement a desired logic circuit using as few chips as possible, so the amount ofcircuitry on a given chip and its functional capability are important. One way to quantify acircuit's size is to assume that the circuit is to be built using only simple logic gates and thenestimate how many of these gates are needed. A commonly used measure is the total numberof two-input NAND gates that would be needed to build the circuit; this measure is oftencalled the number of equivalent gates.

Using the equivalent-gates metric, the size of a 7400-series chip is simple to measurebecause each chip contains only simple gates. For SPLDs and CPLDs the typical measureused is that each macrocell represents about 20 equivalent gates. Thus a typical PAL that haseight macrocells can accommodate a circuit that needs up to about 160 gates, and a largeCPLD that has 500 macrocells can implement circuits of up to about 10,000 equivalentgates.

By modern standards, a logic circuit with 10,000 gates is not large. To implement largercircuits, it is convenient to use a different type of chip that has a larger logic capacity. Afield-programmable gate array (FPGA) is a programmable logic device that supportsimplementation of relatively large logic circuits. FPGAs are quite different from SPLDs andCPLDs because FPGAs do not contain AND or OR planes. Instead, FPGAs provide logicblocks for implementation of the required functions. The general structure of an FPGA isillustrated in Figure 10(a). It contains three main types of resources: logic blocks, I/O blocksfor connecting to the pins of the package, and interconnection wires and switches. The logicblocks are arranged in a two-dimensional array, and the interconnection wires are organizedas horizontal and vertical routing channels between rows and columns of logic blocks. Therouting channels contain wires and programmable switches that allow the logic blocks to beinterconnected in many ways. Figure 10(a) shows two locations for programmable switches;the blue boxes adjacent to logic blocks hold switches that connect the logic block input andoutput terminals to the interconnection wires, and the blue boxes that are diagonally betweenlogic blocks connect one interconnection wire to another (such as a vertical wire to ahorizontal wire). Programmable connections also exist between the I/O blocks and theinterconnection wires. The actual number of programmable switches and wires in an FPGAvaries in commercially available chips.

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Figure 10. A FPGA

FPGAs can be used to implement logic circuits of more than a million equivalent gates insize. FPGA chips are available in a variety of packages, including the PLCC and QFPpackages described earlier. Figure 10(b) depicts another type of package, called a pin gridarray (PGA). A PGA package may have up to a few hundred pins in total, which extendstraight outward from the bottom of the package, in a grid pattern. Yet another packagingtechnology that has emerged is known as the ball grid array (BGA). The BGA is similar tothe PGA except that the pins are small round balls, instead of posts. The advantage of BGApackages is that the pins are very small; hence more pins can be provided on a relativelysmall package. Each logic block in an FPGA typically has a small number of inputs andoutputs. A variety of FPGA products are on the market, featuring different types of logicblocks. The most commonly used logic block is a lookup table (LUTwhich contains storagecells that are used to implement a small logic function. Each cell is capable of holding asingle logic value, either 0 or 1. The stored value is produced as the output of the storagecell. LUTs of various sizes may be created, where the size is defined by the number of

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inputs. Figure 11(a) shows the structure of a small LUT. It has two inputs, x1 and x2, andone output f. It is capable of implementing any logic function of two variables. Because atwo variable truth table has four rows, this LUT has four storage cells. One cell correspondsto the output value in each row of the truth table. The input variables x1 and x2 are used asthe select inputs of three multiplexers, which, depending on the valuation of x1 and x2, selectthe content of one of the four storage cells as the output of the LUT.

Figure 11. A Two Input Look Up Table (LUT).To see how a logic function can be realized in the two-input LUT, consider the truth table inFigure 11(b). The function f1 from this table can be stored in the LUT as illustrated in Figure11(c). The arrangement of multiplexers in the LUT correctly realizes the function f1. Whenx1 = x2 = 0, the output of the LUT is driven by the top storage cell, which represents theentry in the truth table for x1 x2 = 00. Similarly, for all valuations of x1 and x2, the logicvalue stored in the storage cell corresponding to the entry in the truth table chosen by theparticular valuation appears on the LUT output. Providing access to the contents of storagecells is only one way in which multiplexers can be used to implement logic functions.PALs usually have extra circuitry included with their AND-OR gates. The same is true forFPGAs, which usually have extra circuitry, besides a LUT, in each logic block. Figure 12,shows how a flip-flop may be included in an FPGA logic block. The flip-flop is used to storethe value of its D input under control of its clock input.

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Figure 12. Inclusion of a Flip Flop in an FPGA Logic Block.For a logic circuit to be realized in an FPGA, each logic function in the circuit must be smallenough to fit within a single logic block. In practice, a user's circuit is automaticallytranslated into the required form by using CAD tools. When a circuit is implemented in anFPGA, the logic blocks are programmed to realize the necessary functions and the routingchannels are programmed to make the required interconnections between logic blocks. Thestorage cells in the LUTs in an FPGA are volatile, which means that they lose their storedcontents whenever the power supply for the chip is turned off. Hence the FPGA has to beprogrammed every time power is applied. Often a small memory chip that holds its datapermanently, called a programmable read-only memory (PROM), is included on the circuitboard that houses the FPGA. The storage cells in the FPGA are loaded automatically fromthe PROM when power is applied to the chips.

ALSO REFER FILE 2

unit-1

Documents

vhdl language

integrated design

language constructs

design data

design verification

complete design

stage of design

hardwaredescription