unit 5(dsp processor)
TRANSCRIPT
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UNIT-5
INTRODUCTION DIGITAL SIGNAL
PROCESSORS AND ITS
APPLICATION
DSP/ISP division
School of Electronics Engineering
VIT University
Vellore -632 014
DSP DIVISION 1DSP PROCESSOR
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OBJECTIVE
• Understand the DSP Architecture, fixed and
floating point processor differences
• Able to understand how pipelining and
parallelism supports in the DSP Architecture.
• Know how to implement convolution,
correlation, DFT & Filter design using Texas
instruments DSP processor.
DSP DIVISION DSP PROCESSOR 2
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Introduction
• DSP processors can be divided into two
broad categories:» General Purpose
» Special Purpose
• Further DSP processors include » Fixed point devices
» Floating point devices
DSP DIVISION 3DSP PROCESSOR
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Examples of Fixed and Floating• Low End Fixed Point
– TMS320C2XX, ADSP21XX, Motorola (DSP56XXX)
• High End Fixed Point
– TMS320C55XX, DSP16XXX,
– ADSP215XX, DSP56800
• Floating Point
– TMS320C3X, C67XX, ADSP210XX(SHARC processor), DSP96000, DSP32XX
DSP DIVISION 4DSP PROCESSOR
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Fixed Point Vs Floating Point– fixed point processor are :
• cheaper
• smaller
• less power consuming
• Harder to program
– Watch for errors: truncation, overflow, rounding
• Limited dynamic range
• Used in 95% of consumer products
– floating point processors• have larger accuracy
• are much easier to program
• can access larger memory
DSP DIVISION 5DSP PROCESSOR
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Fixed Point Vs Floating Point
Floating Point Fixed Point
Applications
•Modems
•Digital Subscriber Line (DSL)
•Wireless Basestations
•Central Office Switches
•Private Branch Exchange (PBX)
•Digital Imaging
•3D Graphics
•Speech Recognition
•Voice over IP
Applications
•Portable Products
•2G, 2.5G and 3G Cell Phones
•Digital Audio Players
•Digital Still Cameras
•Electronic Books
•Voice Recognition
•GPS Receivers
•Headsets
•Biometrics
•Fingerprint Recognition
DSP DIVISION 6DSP PROCESSOR
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Special purpose hardware
• Hardware designed for efficient execution of specific DSP algorithms such as digital filter, FFT. [ Algorithm-specific digital signal processor]
• Hardware designed for specific application, for example telecommunications, digital audio, or control applications.[ Application -specific digital signal processor]
DSP DIVISION 7DSP PROCESSOR
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Computer Architecture for Signal
Processing
Techniques
• Harvard Architecture
• Pipelining
• Fast, dedicated hardware multiplier/Accumulator
• Special instruction dedicated to DSP
• Replication
• On-chip memory/cache
• Extended parallelism- SIMD, VLIW and static
superscalar processing DSP DIVISION 8DSP PROCESSOR
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DSP DIVISION 9DSP PROCESSOR
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X data bus
Y data bus
Z data bus
I/O
devices Shifter
ALU Multiplier
Accumulator
X data
memory
Y data
memory
Program
memory
Memory units
Basic generic hardware architecture for signal processing
DSP DIVISION 10DSP PROCESSOR
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Harvard
Architecture
DSP DIVISION 11DSP PROCESSOR
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Hardware Multiply and
accumulate
DSP DIVISION 12DSP PROCESSOR
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DSP DIVISION 13DSP PROCESSOR
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DSP DIVISION 14DSP PROCESSOR
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Pipelining
• A technique which allows two or more
operations to overlap during execution.
• It is used extensively in DSP to increase speed.
• The simultaneous functions going on are:
• instruction fetch
• instruction decode
• instruction execution
DSP DIVISION 15DSP PROCESSOR
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Stages of pipelining
DSP DIVISION 16DSP PROCESSOR
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• In a Harvard architecture (DSP processor with pipelining) :
• The program instructions and data lie in separate memory spaces.
• Due to this the fetching of the next instruction can overlap the execution of the current instruction.
• Each of the step is known as pipeline stage
DSP DIVISION 17DSP PROCESSOR
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REGISTERS
• In TMS320 number of registers are used to achieve pipelining.
• Pre-fetch counter: holds the address of the next instruction to be fetched.
• Instruction register: holds the instruction to be executed.
• Queue instruction register: stores the instruction to be executed if the current is still in process of execution.
• Program counter: contains the address of the next instruction to be executed
DSP DIVISION 18DSP PROCESSOR
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•Throughput is determined by the number of
instructions through the pipe per unit time.
•In a perfect pipeline the average time per
instruction is given by( Hennesy and
Patterson,1990)
time per instruction(non-pipeline)
number of pipe stages
Average instruction time (nonpipeline)
•Speedup=
Average instruction time (pipeline)
Parameters used in pipelining
DSP DIVISION 19DSP PROCESSOR
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ADVANTAGESThe cycle time of the processor is reduced, thus increasing
instruction bandwidth in most cases.
DISADVANTAGESThe design is complex due to addition of extra flip flops.
The manufacture cost is high.
The performance of a pipelined processor is much harder
to predict and may vary more widely between different
programs due to unstable instruction bandwidth.
DSP DIVISION 20DSP PROCESSOR
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Examples (pipelining)• Multiply and accumulate operations typified by the following
equation
• a0x(n)+a1x(n-1)+a2x(n-2)+…..+AN-1x(N-1)
• Non pipeline of the above equation
DSP DIVISION 21DSP PROCESSOR
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MAC Pipeline operation
DSP DIVISION 22DSP PROCESSOR
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DSP DIVISION 23DSP PROCESSOR
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Parallelism
• To achieve increased computational
performance
• Three techniques used to achieve
parallelism are
• SIMD
• VLIW
• Superscalar processing
DSP DIVISION 24DSP PROCESSOR
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SIMD (Single instruction multiple
data)
• Used to increase number of operation performed per instruction
• Multiple data path and multiple execution unit
• Single instruction may be issued to multiple execution unit to process the block of data simultaneously and in this way number of operation performed in one cycle is increased
DSP DIVISION 25DSP PROCESSOR
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SIMD
DSP DIVISION 26DSP PROCESSOR
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DSP DIVISION 27DSP PROCESSOR
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DSP DIVISION 28DSP PROCESSOR
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VLIW (Very Long Instruction Word)
• Substantially increasing the number of
instruction that are processed per cycle
• Essentially a concatenation of several
short instruction and require multiple
execution units running in parallel to carry
out the instructions in a single cycle
DSP DIVISION 29DSP PROCESSOR
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DSP DIVISION 30DSP PROCESSOR
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Features of VLIW
• The cpu contain two data paths and eight independent
execution units, organized in two sets –(L1,S1,M1,D1)
and (L2,S2,M2,D2)
• Each short instruction is 32 bits wide and eight of these
are linked together to form a very long instruction word
packed which may be executed in parallel.
• VLIW architecture is clearly designed to support
instruction level parallelism, together with fast clock
speeds-200MHz
DSP DIVISION 31DSP PROCESSOR
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Super scalar processing
• Increasing the instruction rate of a DSP processor (the
number of instruction processed in a cycle) by exploiting
instruction-level parallelism.
• Super scalar- computer architecture that enable multiple
instruction to be executed in one cycles
• It is widely used in general purpose processor such as
power PC, and Pentium processor
• Best known super scalar processor is the Analog
devices Tiger SHARC
DSP DIVISION 32DSP PROCESSOR
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DSP DIVISION 33DSP PROCESSOR
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General Purpose Digital Signal
processor
• It is a High speed microprocessor with hardware
architecture
• Instruction sets are optimized for DSP
operations
• Extensive use of parallelism, Harvard
architecture, pipelining and dedicated hardware,
shifting, scaling, multiplication and so on
DSP DIVISION 34DSP PROCESSOR
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Fixed point Digital Signal Processors
DSP DIVISION 35DSP PROCESSOR
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DSP DIVISION 36DSP PROCESSOR
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DSP DIVISION 37DSP PROCESSOR
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DSP DIVISION 38DSP PROCESSOR
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DSP DIVISION 39DSP PROCESSOR
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DSP DIVISION 40DSP PROCESSOR
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DSP DIVISION 41DSP PROCESSOR
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DSP DIVISION 42DSP PROCESSOR
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DSP DIVISION 43DSP PROCESSOR
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DSP DIVISION 44DSP PROCESSOR
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Fixed point Digital Signal
processors
DSP DIVISION 45DSP PROCESSOR
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Floating Point Processors
DSP DIVISION 46DSP PROCESSOR
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Selecting the Digital Signal
Processor
• Architectural features• Size of on chip memory
• Special Instruction
• I/O capability
• Execution speed• Clock speed of the processor(MHz)
• Number of instruction performed (MIPS) &
(MFLOPS)
DSP DIVISION 47DSP PROCESSOR
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• Type of Arithmetic
– Fixed point arithmetic
– Floating point arithmetic
• Word Length
– 24 bit word length for audio processing
– Longer data word length lower the error
DSP DIVISION 48DSP PROCESSOR
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Implementation of DSP algorithm
on general purpose Digital Signal
Processor
• FIR Digital filtering
DSP DIVISION 49DSP PROCESSOR
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DSP DIVISION 50DSP PROCESSOR
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DSP DIVISION DSP PROCESSOR 51
References:
1. Emmanuel C.Ifeachor, “ Digital Signal Processing A Practical Approach” 2nd
edition, Pearson Education, 2001.
2. Lawrence R Rabiner and Bernard Gold, “Theory and Application of Digital
Signal Processing” , PHI 1992