KCE/DEPT.OF.EEE/E-Material Subject Code/Name: EE6503/Power Electronics

UNIT I

POWER SEMI-CONDUCTOR DEVICES

INTRODUCTION

Power Electronics is a field which combines Power (electric power), Electronics and Control systems. Power engineering deals with the static and rotating power equipment for the generation, transmission and distribution of electric power. Electronics deals with the study of solid state semiconductor power devices and circuits for Power conversion to meet the desired control objectives (to control the output voltage and output power). Power electronics may be defined as the subject of applications of solid state power semiconductor devices (Thyristors) for the control and conversion of electric power.

Topic

Study of Switching Devices

Sub Topics

Brief History of Power Electronics, Power Electronic Applications, Power Semiconductor Devices

1. STUDY OF SWITCHING DEVICES

1.1 Brief History of Power Electronics

The first Power Electronic Device developed was the Mercury Arc Rectifier during the year 1900. Then the other Power devices like metal tank rectifier, grid controlled vacuum tube rectifier, ignitron, phanotron, thyratron and magnetic amplifier, were developed & used gradually for power control applications until 1950. The first SCR (silicon controlled rectifier) or Thyristor was invented and developed by Bell Labs in 1956 which was the first PNPN triggering transistor. The second electronic revolution began in the year 1958 with the development of the commercial grade Thyristor by the General Electric Company (GE). Thus the new era of power electronics was born. After that many different types of power semiconductor devices & power conversion techniques have been introduced. The power electronics revolution is giving us the ability to convert, shape and control large amounts of power.

1.2 Power Electronic Applications

a) Commercial Applications

Heating Systems Ventilating, Air Conditioners, Central Refrigeration, Lighting, Computers and Office equipments, Uninterruptible Power Supplies (UPS), Elevators, and Emergency Lamps.

b) Domestic Applications

Cooking Equipments, Lighting, Heating, Air Conditioners, Refrigerators & Freezers, Personal Computers, Entertainment Equipments, UPS.

c) Industrial Applications

Pumps, compressors, blowers and fans. Machine tools, arc furnaces, induction furnaces, lighting control circuits, industrial lasers, induction heating, welding equipments.

d) Aerospace Applications

Space shuttle power supply systems, satellite power systems, aircraft power systems.

e) Telecommunications

Battery chargers, power supplies (DC and UPS), mobile cell phone battery chargers.

f) Transportation

Traction control of electric vehicles, battery chargers for electric vehicles, electric locomotives, street cars, trolley buses, automobile electronics including engine controls.

1.3 POWER SEMICONDUCTOR DEVICES

The power semiconductor devices are used as on/off switches in power control circuit. These

devices are classified as follows

Part-A Question

1. What are the applications of Power Electronics?

2. What are the classification of power devices?

(Topic Power Semiconductor- DiodesSub Topics Structure, Ton-Toff , V-I Characteristics of Diode )

2. (a) POWER SEMICONDUCTOR- DIODES

Introduction

Power semiconductor diode is the power level counter part of the low power signal diodes with which most of us have some degree of familiarity. These power devices, however, are required to carry up to several KA of current under forward bias condition and block up to several KV under reverse biased condition. These extreme requirements call for important structural changes in a power diode which significantly affect their operating characteristics. These structural modifications are generic in the sense that the same basic modifications are applied to all other low power semiconductor devices (all of which have one or more p-n junctions) to scale up their power capabilities. It is, therefore, important to understand the nature and implication of these modifications in relation to the simplest of the power devices, i.e., a power semiconductor diode.

2.(a).1 Construction and Characteristics of Power Diodes

As mention in the introduction Power Diodes of largest power rating are required to conduct several kilo amps of current in the forward direction with very little power loss while blocking several kilo volts in the reverse direction. Large blocking voltage requires wide depletion layer in order to restrict the maximum electric field strength below the impact ionization level. Space charge density in the depletion layer should also be low in order to yield a wide depletion layer for a given maximum Electric fields strength. These two requirements will be satisfied in a lightly doped p-n junction diode of sufficient width to accommodate the required depletion layer. Such a construction, however, will result in a device with high resistively in the forward direction. Consequently, the power loss at the required rated current will be unacceptably high. On the other hand if forward resistance (and hence power loss) is reduced by increasing the doping level, reverse break down voltage will reduce. This apparent contradiction in the requirements of a power diode is resolved by introducing a lightly doped drift layer of required thickness between two heavily doped p and n layers as shown in Fig (c),Fig (a) and Fig (b) shows the circuit symbol and the photograph of a typical power diode respectively.

Diagram of a power; (a) circuit symbol (b) photograph (c) schematic cross section.

To arrive at the structure shown in Fig (c) a lightly doped n- epitaxial layer of specified width (depending on the required break down voltage) and donor atom density (NdD) is grown on a heavily doped n+ substrate (NdK donor atoms.Cm -3) which acts as the cathode. Finally the p-n junction is formed by defusing a heavily doped (NaA acceptor atoms.Cm-3) p+ region into the epitaxial layer. This p type region acts as the anode. Impurity atom densities in the heavily doped cathode (Ndk .Cm -3) and anode (NaA.Cm -3) are approximately of the same order of magnitude (10 19 Cm -3) while that of the epitaxial layer (also called the drift region) is lower by several orders of magnitude (NdD ~ 10 14 Cm 3). In a low power diode this drift region is absent.

2.(a).2 Switching Characteristics of Power Diodes

Power Diodes take finite time to make transition from reverse bias to forward bias condition (switch ON) and vice versa (switch OFF). Behavior of the diode current and voltage during these switching periods are important due to the following reasons.

Severe over voltage / over current may be caused by a diode switching at different points in the circuit using the diode.

Voltage and current exist simultaneously during switching operation of a diode. Therefore, every switching of the diode is associated with some energy loss. At high switching frequency this may contribute significantly to the overall power loss in the diode. Observed Turn ON behavior of a power Diode: Diodes are often used in circuits with di/dt limiting inductors. The rate of rise of the forward current through the diode during Turn ON has significant effect on the forward voltage drop characteristics. A typical turn on transient is shown in Fig.

Forward current and voltage waveforms of a power diode during Turn On Operation.

It is observed that the forward diode voltage during turn ON may transiently reach a significantly higher value Vfr compared to the steady slate voltage drop at the steady current IF. In some power converter circuits (e.g voltage source inverter) where a freewheeling diode is used across an asymmetrical blocking power switch (i.e GTO) this transient over voltage may be high enough to destroy the main power switch.VFr (called forward recovery voltage) is given as a function of the forward di/dt in the manufacturers data sheet. Typical values lie within the range of 10-30V. Forward recovery time (tfr) is typically within 10 us.

Observed Turn OFF behavior of a Power Diode:

Fig.shows a typical turn off behavior of a power diode assuming controlled rate of decrease of the forward current.

Reverse Recovery characteristics of a power diode

Salient features of this characteristic are:

The diode current does not stop at zero, instead it grows in the negative direction to Irr called peak reverse recovery current which can be comparable to IF. In many power electronic circuits (e.g. choppers, inverters) this reverse current flows through the main power switch in addition to the load current. Therefore, this reverse recovery current has to be accounted for while selecting the main switch.

Voltage drop across the diode does not change appreciably from its steady state value till the diode current reaches reverse recovery level. In many power electric circuits (choppers, inverters) this may create an effective short circuit across the supply, current being limited only by the stray wiring inductance. Also in high frequency switching circuits (e.g, SMPS) if the time period t4 is comparable to switching cycle qualitative modification to the circuit behavior is possible.

Towards the end of the reverse recovery period if the reverse current falls too sharply, (low value of S), stray circuit inductance may cause dangerous over voltage (Vrr) across the device. It may be required to protect the diode using an RC snubber.

During the period t5 large current and voltage exist simultaneously in the device. At high switching frequency this may result in considerable increase in the total power loss. Important parameters defining the turn off characteristics are, peak reverse recovery current (Irr), reverse recovery time (trr), reverse recovery charge (Qrr) and the snappiness factor S. Of these parameters, the snappiness factor S depends mainly on the construction of the diode (e.g. drift region width, doping lever, carrier life time etc.). Other parameters are interrelated and also depend on S. Manufacturers usually specify these parameters as functions of diF/dt for different values of IF. Both Irr and Qrr increases with IF and diF/dt while trr increases with IF and decreases with diF/dt.

2.(a). 3 Review of Basic p-n Diode Characteristics

A p-n junction diode is formed by placing p and n type semiconductor materials in intimate contact on an atomic scale. This may be achieved by diffusing acceptor impurities in to an n type silicon crystal or by the opposite sequence.

In an open circuit p-n junction diode, majority carriers from either side will defuse across the junction to the opposite side where they are in minority. These diffusing carriers will leave behind a region of ionized atoms at the immediate vicinity of the metallurgical junction. This region of immobile ionized atoms is called the space charge region. This process continues till the resultant electric field (created by the space charge density) and the potential barrier at the junction builds up to sufficient level to prevent any further migration of carriers. At this point the p-n junction is said to be in thermal equilibrium condition. Variation of the space charge density, the electric field and the potential along the device is shown in Fig (a).

Space change density the electric field and the electric potential inside a p-n junction under (a) thermal equilibrium condition, (b) reverse biased condition, (c) forward biased condition.

When an external voltage is applied with p side move negative then the n side the junction is said to be under reverse bias condition. This reverse bias adds to the height of the potential barrier. The electric field strength at the junction and the width of the space change region (also called the depletion region because of the absence of free carriers) also increases. On the other hand, free minority carrier densities (n-p in the p side and pn in the n side) will be zero at the edge of the depletion region on either side (Fig(b)). This gradient in minority carrier density causes a small flux of minority carriers to defuse towards the deletion layer where they are swept immediately by the large electric field into the electrical neutral region of the opposite side. This will constitute a small leakage current across the junction from the n side to the p side. There will also be a contribution to the leakage current by the electron hole pairs generated in the space change layer by the thermal ionization process. These two components of current together is called the reverse saturation current Is of the diode. Value of Is is independent of the reverse voltage magnitude (up to a certain level) but extremely sensitive to temperature variation. When the applied reverse voltage exceeds some threshold value (for a given diode) the reverse current increases rapidly. The diode is said to have undergone reverse break down. Reverse break down is caused by "impact ionization" as explained below. Electrons accelerated by the large depletion layer electric field due to the applied reverse voltage may attain sufficient knick energy to liberate another electron from the covalent bonds when it strikes a silicon atom. The liberated electron in turn may repeat the process. This cascading effect (avalanche) may produce a large number of free electrons very quickly resulting in a large reverse current. The power dissipated in the device increases manifold and may cause its destruction. Therefore, operation of a diode in the reverse breakdown region must be avoided.

When the diode is forward biased (i.e., p side more positive than n side) the potential barrier is lowered and a very large number of minority carriers are injected to both sides of the junction. The injected minority a carrier eventually recombines with the majority carries as they defuse further into the electrically neutral drift region. The excess free carrier density in both p and n side follows exponential decay characteristics. The characteristic decay length is called the "minority carrier diffusion length" Carrier density gradients on either side of the junction are supported by a forward current IF (flowing from p side to n side) which can be expressed as

IF = IS(exp (qv/kT )-1 (1.1)

Where, Is = Reverse saturation current ( Amps)

v = Applied forward voltage across the device (volts)

q = Change of an electron

k = Boltzmans constant

T = Temperature in Kelvin

Volt-Ampere ( i-v ) characteristics of a p-n junction diode

From the foregoing discussion the i-v characteristics of a p-n junction diode can be drawn as shown in Fig. While drawing this characteristic the ohmic drop in the bulk of the semiconductor body has been neglected.

(Topic Power Semiconductor- ThyristorsSub Topics Structure, Ton-Toff , V-I Characteristics of Thyristors)

2.(b).POWER SEMICONDUCTOR-THYRISTORS

Although the large semiconductor diode was a predecessor to thyristors, the modern power electronics area truly began with advent of thyristors. One of the first developments was the publication of the P-N-P-N transistor switch concept in 1956 by J.L. Moll and others at Bell Laboratories, probably for use in Bells Signal application. However, engineers at General Electric quickly recognized its significance to power conversion and control and within nine months announced the first commercial Silicon Controlled Rectifier in 1957. This had a continuous current carrying capacity of 25A and a blocking voltage of 300V. Thyristors (also known as the Silicon Controlled Rectifiers or SCRs) have come a long way from this modest beginning and now high power light triggered thyristors with blocking voltage in excess of 6kv and continuous current rating in excess of 4kA are available. They have reigned supreme for two entire decades in the history of power electronics. Along the way a large number of other devices with broad similarity with the basic thyristor (invented originally as a phase control type device) have been developed. They include, inverter grade fast thyristor, Silicon Controlled Switch (SCS), light activated SCR (LASCR), Asymmetrical Thyristor (ASCR) Reverse Conducting Thyristor (RCT), Diac, Triac and the Gate turn off thyristor (GTO).

From the construction and operational point of view a thyristor is a four layer, three terminal, minority carrier semi-controlled device. It can be turned on by a current signal but can not be turned off without interrupting the main current. It can block voltage in both directions but can conduct current only in one direction. During conduction it offers very low forward voltage drop due to an internal latch-up mechanism. Thyristors have longer switching times (measured in tens of s) compared to a BJT. This, coupled with the fact that a thyristor can not be turned off using a control input, has all but eliminated thyristors in high frequency switching applications involving a DC input (i.e., choppers, inverters). However in power frequency ac applications where the current naturally goes through zero, thyristor remain popular due to its low conduction loss its reverse voltage blocking capability and very low control power requirement. In fact, in very high power (in excess of 50 MW) AC DC (phase controlled converters) or AC AC (cyclo-converters) converters, thyristors still remain the device of choice.

2.(b).1.Constructional Features of a Thyristor

Fig. Shows the circuit symbol, schematic construction and the photograph of a typical thyristor.

Constructional features of a thyristor

(a) Circuit Symbol (b) Schematic Construction (c) Photograph

As shown in Fig.(b) the primary crystal is of lightly doped n- type on either side of which two p type layers with doping levels higher by two orders of magnitude are grown. As in the case of power diodes and transistors depletion layer spreads mainly into the lightly doped n- region. The thickness of this layer is therefore determined by the required blocking voltage of the device. However, due to conductivity modulation by carriers from the heavily doped p regions on both side during ON condition the ON state voltage drop is less. The outer n+ layers are formed with doping levels higher then both the p type layers. The top p layer acts as the Anode terminal while the bottom n+ layers acts as the Cathode. The Gate terminal connections are made to the bottom p layer.

As it will be shown later, that for better switching performance it is required to maximize the peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions are finely distributed between gate contacts of the p type layer. An Involute structure for both the gate and the cathode regions is a preferred design structure.

Basic operating principle of a thyristor

The underlying operating principle of a thyristor is best understood in terms of the two transistor analogy as explained below.

Two transistor analogy of a thyristor construction.

(a) Schematic Construction, (b) Schematic division in component transistor

(c) Equivalent circuit in terms of two transistors.

Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode positive with respect to the cathode and the gate terminal open. With this voltage polarity J1 & J3 are forward biased while J2 reverse biased.

Under this condition.

ic1=1IA+Ico1 (1.2)

ic2=2Ik+Ico2 (1.3)

Where 1 & 2 are current gains of Q1 & Q2 respectively while Ico1 & Ico2 are reverse saturation currents of the CB junctions of Q1 & Q2 respectively.

Now from Fig 1.6 (c).

ic1 +ic2 =IA (1.4)

& IA=Ik ( IG=0) (1.5)

Combining Eq 1.2 & 1.5

(1.6)

Where Ico Ico1 +Ico2 is the total reverse leakage current of J2

Now as long as VAK is small Ico is very low and both 1 & 2 are much lower than unity. Therefore, total anode current IA is only slightly greater than Ico. However, as VAK is increased up to the avalanche break down voltage of J2, Ico starts increasing rapidly due to avalanche multiplication process. As Ico increases both 1 & 2 increase and 1 + 2 approaches unity. Under this condition large anode current starts flowing, restricted only by the external load resistance. However, voltage drop in the external resistance causes a collapse of voltage across the thyristor. The CB junctions of both Q1 & Q2 become forward biased and the total voltage drop across the device settles down to approximately equivalent to a diode drop. The thyristor is said to be in ON state.

Just after turn ON if Ia is larger than a specified current called the Latching Current IL, 1 and 2 remain high enough to keep the thyristor in ON state. The only way the thyristor can be turned OFF is by bringing IA below a specified current called the holding current (IH) where upon 1 & 2 starts reducing. The thyristor can regain forward blocking capacity once excess stored charge at J2 is removed by application of a reverse voltage across A & K (ie, K positive with respect A).

It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to cathode) without increasing the forward voltage across the device up to the forward break-over level. With a positive gate current equation 1.5 can be written as

IK=IA+IG (1.7)

Combining with Eqns. 1.2 to 1.4

(1.8)

Obviously with sufficiently large IG the thyristor can be turned on for any value of Ico (and hence VAK). This is called gate assisted turn on of a Thyristor. This is the usual method by which a thyristor is turned ON.

When a reverse voltage is applied across thyristor (i.e, cathode positive with respect to anode.) junctions J1 and J3 are reverse biased while J2 is forward biased. Of these, the junction J3 has a very low reverse break down voltage since both the n+ and p regions on either side of this junction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported by junction J1. The maximum value of the reverse voltage is restricted by

a) The maximum field strength at junction J1 (avalanche break down)

b) Punch through of the lightly doped n- layer.

Since the p layers on either side of the n- region have almost equal doping levels the avalanche break down voltage of J1 & J2 are almost same. Therefore, the forward and the reverse break down voltage of a thyristor are almost equal. Up to the break down voltage of J1 the reverse current of the thyristor remains practically constant and increases sharply after this voltage. Thus, the reverse characteristics of a thyristor are similar to that of a single diode.

If a positive gate current is applied during reverse bias condition, the junction J3 becomes forward biased. In fact, the transistors Q1 & Q2 now work in the reverse direction with the roles of their respective emitters and collectors interchanged. However, the reverse 1 & 2 being significantly smaller than their forward counterparts latching of the thyristor does not occur. However, reverse leakage current of the thyristor increases considerably increasing the OFF state power loss of the device.

If a forward voltage is suddenly applied across a reverse biased thyristor, there will be considerable redistribution of charges across all three junctions. The resulting current can become large enough to satisfy the condition 1 + 2 = 1 and consequently turn on the thyristor. This is called dv/dt turn on of a thyristor and should be avoided.

2.(b).2.Switching Characteristics of a Thyristor

During Turn on and Turn off process a thyristor is subjected to different voltages across it and different currents through it. The time variations of the voltage across a thyristor and the current through it during Turn on and Turn off constitute the switching characteristics of a thyristor.

Turn on Switching Characteristics

A forward biased thyristor is turned on by applying a positive gate voltage between the gate and cathode as shown in Fig.

Turn on characteristics of a thyristor.

Fig. shows the waveforms of the gate current (ig), anode current (iA) and anode cathode voltage (VAK) in an expanded time scale during Turn on. The reference circuit and the associated waveforms are shown in the inset. The total switching period being much smaller compared to the cycle time, iA and VAK before and after switching will appear flat.

As shown in Fig. there is a transition time tON from forward off state to forward on state. This transition time is called the thyristor turn of time and can be divided into three separate intervals namely, (i) delay time (td) (ii) rise time (tr) and (iii) spread time (tp). These times are shown in Fig. for a resistive load.

Delay time (td): After switching on the gate current the thyristor will start to conduct over the portion of the cathode which is closest to the gate. This conducting area starts spreading at a finite speed until the entire cathode region becomes conductive. Time taken by this process constitute the turn on delay time of a thyristor. It is measured from the instant of application of the gate current to the instant when the anode current rises to 10% of its final value (or VAK falls to 90% of its initial value). Typical value of td is a few micro seconds.

Rise time (tr): For a resistive load, rise time is the time taken by the anode current to rise from 10% of its final value to 90% of its final value. At the same time the voltage VAK falls from 90% of its initial value to 10% of its initial value. However, current rise and voltage fall characteristics are strongly influenced by the type of the load. For inductive load the voltage falls faster than the current. While for a capacitive load VAK falls rapidly in the beginning. However, as the current increases, rate of change of anode voltage substantially decreases.

If the anode current rises too fast it tends to remain confined in a small area. This can give rise to local hot spots and damage the device. Therefore, it is necessary to limit the rate of rise of the ON state current (dia/dt) by using an inductor in series with the device. Usual values of maximum allowable dia/dt is in the range of 20-200 A/s.

Spread time (tp): It is the time taken by the anode current to rise from 90% of its final value to 100%. During this time conduction spreads over the entire cross section of the cathode of the thyristor. The spreading interval depends on the area of the cathode and on the gate structure of the thyristor.

Turn off Switching Characteristics

Once the thyristor is on, and its anode current is above the latching current level the gate loses control. It can be turned off only by reducing the anode current below holding current. The turn off time tq of a thyristor is defined as the time between the instant anodes current becomes zero and the instant the thyristor regains forward blocking capability. If forward voltage is applied across the device during this period the thyristor turns on again. During turn off time, excess minority carriers from all the four layers of the thyristor must be removed. Accordingly tq is divided in to two intervals, the reverse recovery time (trr) and the gate recovery time (tqr). Fig. Shows the variation of anode current and anode cathode voltage with time during turn off operation on an expanded scale.

Turn off characteristics of a thyristor

The anode current becomes zero at time t1 and starts growing in the negative direction with the same diA/dt till time t2. This negative current removes excess carriers from junctions J1 & J3. At time t2 excess carriers densities at these junctions are not sufficient to maintain the reverse current and the anode current starts decreasing. The value of the anode current at time t2 is called the reverse recovery current (Irr). The reverse anode current reduces to the level of reverse saturation current by t3. Total charge removed from the junctions between t1 & t3 is called the reverse recovery charge (Qrr). Fast decaying reverse current during the interval t2 t3 coupled with the di/dt limiting inductor may cause a large reverse voltage spike (Vrr) to appear across the device. This voltage must be limited below the VRRM rating of the device. Up to time t2 the voltage across the device (VAK) does not change substantially from its on state value. However, after the reverse recovery time, the thyristor regains reverse blocking capacity and VAK starts following supply voltage vi. At the end of the reverse recovery period (trr) trapped charges still exist at the junction J2 which prevents the device from blocking forward voltage just after trr. These trapped charges are removed only by the process of recombination. The time taken for this recombination process to complete (between t3 & t4) is called the gate recovery time (tgr). The time interval tq = trr + tgr is called device turn off time of the thyristor.

No forward voltage should appear across the device before the time tq to avoid its inadvertent turn on. A circuit designer must provide a time interval tc (tc > tq) during which a reverse voltage is applied across the device. tc is called the circuit turn off time.

The reverse recovery charge Qrr is a function of the peak forward current before turn off and its rate of decrease diA/dt. Manufacturers usually provide plots of Qrr as a function of diA/dt for different values of peak forward current. They also provide the value of the reverse recovery current Irr for a given IA and diA/dt. Alternatively Irr can be evaluated from the given Qrr characteristics following similar relationships as in the case of a diode.

As in the case of a diode the relative magnitudes of the time intervals t1 t2 and t2 t3 depends on the construction of the thyristor. In normal recovery converter grade thyristor they are almost equal for a specified forward current and reverse recovery current. However, in a fast recovery inverter grade thyristor the interval t2 t3 is negligible compared to the interval t1 t2. This helps reduce the total turn off time tq of the thyristor (and hence allow them to operate at higher switching frequency). However, large voltage spike due to this snappy recovery will appear across the device after the device turns off. Typical turn off times of converter and inverter grade thyristors is in the range of 50-100 s and 5-50 s respectively. As has been mentioned in the introduction thyristor is the device of choice at the very highest power levels. At these power levels (several hundreds of megawatts) reliability of the thyristor power converter is of prime importance. Therefore, suitable protection arrangement must be made against possible overvoltage, over current and unintended turn on for each thyristor. At the highest power level (HVDC transmission system) thyristor converters operate from network voltage levels in excess of several hundreds of kilo volts and conduct several tens of kilo amps of current. They usually employ a large number of thyristors connected in series parallel combination. For maximum utilization of the device capacity it is important that each device in this series parallel combination share the blocking voltage and on state current equally. Special equalizing circuits are used for this purpose.

2.(b).3.Static output i-v characteristics of a thyristor

Static output characteristics of a Thyristor

The circuit symbol in the left hand side inset defines the polarity conventions of the variables used in this figure. With ig = 0, VAK has to increase up to forward break over voltage VBRF before significant anode current starts flowing. However, at VBRF forward break over takes place and the voltage across the thyristor drops to VH (holding voltage). Beyond this point voltage across the thyristor (VAK) remains almost constant at VH (1-1.5v) while the anode current is determined by the external load.

The magnitude of gate current has a very strong effect on the value of the break over voltage as shown in the figure. The right hand side figure in the inset shows a typical plot of the forward break over voltage (VBRF) as a function of the gate current (Ig)

After Turn ON the thyristor is no more affected by the gate current. Hence, any current pulse (of required magnitude) which is longer than the minimum needed for Turn ON is sufficient to effect control. The minimum gate pulse width is decided by the external circuit and should be long enough to allow the anode current to rise above the latching current (IL) level. The left hand side of Fig 1.7 shows the reverse i-v characteristics of the thyristor. Once the thyristor is ON the only way to turn it OFF is by bringing the thyristor current below holding current (IH). The gate terminal has no control over the turn OFF process. In ac circuits with resistive load this happens automatically during negative zero crossing of the supply voltage. This is called natural commutation or line commutation. However, in dc circuits some arrangement has to be made to ensure this condition. This process is called forced commutation.

During reverse blocking if ig = 0 then only reverse saturation current (Is) flows until the reverse voltage reaches reverse break down voltage (VBRR). At this point current starts rising sharply. Large reverse voltage and current generates excessive heat and destroys the device. If ig > 0 during reverses bias condition the reverse saturation current rises as explained in the previous section. This can be avoided by removing the gate current while the thyristor is reverse biased.

Part-A Question

1. What is the difference between power diode and signal diode?

2. What is the turn-off time for converter grade SCRs and inverter grade SCRs?

3. Define circuit turn off time.

4. Define latching current.

5. Define holding current.

Part-B Question

1. Explain the operation of SCR using two transistor analogy.

2. Briefly discuss the V-I characteristics of SCR.

3. Draw and explain the switching characteristics of SCR.

4. Explain the basic structure and V-I characteristics of power diodes with neat diagram.

(Topic Power Semiconductor- TriacSub Topics Structure, Ton-Toff , V-I Characteristics of Triac)

3. POWER SEMICONDUCTOR- Triac

The Triac is a member of the thyristor family. But unlike a thyristor which conducts only in one direction (from anode to cathode) a triac can conduct in both directions. Thus a triac is similar to two back to back (anti parallel) connected thyristosr but with only three terminals. As in the case of a thyristor, the conduction of a triac is initiated by injecting a current pulse into the gate terminal. The gate looses control over conduction once the triac is turned on. The triac turns off only when the current through the main terminals become zero. Therefore, a triac can be categorized as a minority carrier, a bidirectional semi-controlled device. They are extensively used in residential lamp dimmers, heater control and for speed control of small single phase series and induction motors.

3.1 Construction and operating principle

Fig. (a) and (b) show the circuit symbol and schematic cross section of a triac respective. As the Triac can conduct in both the directions the terms anode and cathode are not used for Triacs. The three terminals are marked as MT1 (Main Terminal 1), MT2 (Main Terminal 2) and the gate by G. As shown in Fig.(b) the gate terminal is near MT1 and is connected to both N3 and P2 regions by metallic contact. Similarly MT1 is connected to N2 and P2 regions while MT2 is connected to N4 and P1 regions.

Circuit symbol and schematic construction of a Triac

(a) Circuit symbol (b) Schematic construction.

Since a Triac is a bidirectional device and can have its terminals at various combinations of positive and negative voltages, there are four possible electrode potential combinations as given below

1. MT2 positive with respect to MT1, G positive with respect to MT1

2. MT2 positive with respect to MT1, G negative with respect to MT1

3. MT2 negative with respect to MT1, G negative with respect to MT1

4. MT2 negative with respect to MT1, G positive with respect to MT1

The triggering sensitivity is highest with the combinations 1 and 3 and are generally used. However, for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2 and 3 are used. Trigger mode 4 is usually averred. Fig (a) and (b) explain the conduction mechanism of a triac in trigger modes 1 & 3 respectively.

Conduction mechanism of a triac in trigger modes 1 and 3

(a) Mode 1(b) Mode 3 .

In trigger mode-1 the gate current flows mainly through the P2 N2 junction like an ordinary thyristor. When the gate current has injected sufficient charge into P2 layer the triac starts conducting through the P1 N1 P2 N2 layers like an ordinary thyristor. In the trigger mode-3 the gate current Ig forward biases the P2 P3 junction and a large number of electrons are introduced in the P2 region by N3. Finally the structure P2 N1 P1 N4 turns on completely.

3.2 Steady State Output Characteristics and Ratings of a Triac

Steady state V I characteristics of a Triac

From a functional point of view a triac is similar to two thyristors connected in anti parallel. Therefore, it is expected that the V-I characteristics of Triac in the 1st and 3rd quadrant of the V-I plane will be similar to the forward characteristics of a thyristors. As shown in Fig., with no signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak value is lower than the break over voltage (VBO) of the device. However, the turning on of the triac can be controlled by applying the gate trigger pulse at the desired instance. Mode-1 triggering is used in the first quadrant where as Mode-3 triggering is used in the third quadrant. As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current). However, in a triac the two conducting paths (from MT1 to MT2 or from MT1 to MT1) interact with each other in the structure of the triac. Therefore, the voltage, current and frequency ratings of triacs are considerably lower than thyristors. At present triacs with voltage and current ratings of 1200V and 300A (rms) are available. Triacs also have a larger on state voltage drop compared to a thyristor. Manufacturers usually specify characteristics curves relating rms device current and maximum allowable case temperature as shown in Fig . Curves relating the device dissipation and RMS on state current are also provided for different conduction angles.

RMS ON state current Vs maximum case temperature.

Part-A Question

1. Distinguish between SCR and TRIAC.

2. What are the applications of TRAIC?

Part-B Question

1. Explain the construction and V-I characteristics of TRIAC with neat diagram.

(Topic Power Semiconductor- GTOSub Topics Structure, Ton-Toff , V-I Characteristics of GTO)

4.(a) POWER SEMICONDUCTOR- Gate Turn Off Thyristor (GTO)

4.(a).1Constructional Features of a GTO

Fig shows the circuit symbol and two different schematic cross section of a GTO.

Circuit symbol and schematic cross section of a GTO (a) Circuit Symbol,

(b) Anode shorted GTO structure, (c) Buffer layer GTO structure.

Like a thyristor, a GTO is also a four layer three junction p-n-p-n device. In order to obtain high emitter efficiency at the cathode end, the n+ cathode layer is highly doped. Consequently, the break down voltage of the function J3 is low (typically 20-40V). The p type gate region has conflicting doping requirement. To maintain good emitter efficiency the doping level of this layer should be low, on the other hand, from the point of view of good turn off properties, resistively of this layer should be as low as possible requiring the doping level of this region to be high. Therefore, the doping level of this layer is highly graded. Additionally, in order to optimize current turn off capability, the gate cathode junction must be highly interdigitated. A 3000 Amp GTO may be composed of up to 3000 individual cathode segments which are a accessed via a common contact. The most popular design features multiple segments arranged in concentric rings around the device center.

The maximum forward blocking voltage of the device is determined by the doping level and the thickness of the n type base region next. In order to block several kv of forward voltage the doping level of this layer is kept relatively low while its thickness is made considerably higher (a few hundred microns). Beyond the maximum allowable forward voltage either the electric field at the main junction (J2) exceeds a critical value (avalanche break down) or the n base fully depletes, allowing its electric field to touch the anode emitter (punch through).

The junction between the n base and p+ anode (J1) is called the anode junction. For good turn on properties the efficiency of this anode junction should be as high as possible requiring a heavily doped p+ anode region. However, turn off capability of such a GTO will be poor with very low maximum turn off current and high losses. There are two basic approaches to solve this problem.

In the first method, heavily doped n+ layers are introduced into the p+ anode layer. They make contact with the same anode metallic contact. Therefore, electrons traveling through the base can directly reach the anode metal contact without causing hole injection from the p+ anode. This is the classic anode shorted GTO structure as shown in Fig (b). Due to presence of these anode shorts the reverse voltage blocking capacity of GTO reduces to the reverse break down voltage of junction J3 (20-40 volts maximum). In addition a large number of anode shorts reduces the efficiency of the anode junction and degrades the turn on performance of the device. Therefore, the densities of the anode shorts are to be chosen by a careful compromise between the turn on and turn off performance.

In the other method, a moderately doped n type buffer layer is juxtaposed between the n- type base and the anode. As in the case of a power diode and BJT this relatively high density buffer layer changes the shape of the electric field pattern in the n- base region from triangular to trapezoidal and in the process, helps to reduce its width drastically. However, this buffer layer in a conventional anode shorted GTO structure would have increased the efficiency of the anode shorts. Therefore, in the new structure the anode shorts are altogether dispensed with and a thin p+ type layer is introduce as the anode. The design of this layer is such that electrons have a high probability of crossing this layer without stimulating hole injection. This is called the Transparent emitter structure and is shown in Fig (c).

4. (a).2.Switching Characteristics of a GTO

Switching characteristics of a GTO.

Fig. shows the switching characteristics of a GTO and refers to the resistive dc load switching circuit shown on the right hand side. When the GTO is off the anode current is zero and VAK = Vd. To turn on the GTO, a positive gate current pulse is injected through the gate terminal. A substantial gate current ensures that all GTO cathode segments are turned on simultaneously and within a short time. There is a delay between the application of the gate pulse and the fall of anode voltage, called the turn on delay time td. After this time the anode voltage starts falling while the anode current starts rising towards its steady value IL. Within a further time interval tr they reach 10% of their initial value and 90% of their final value respectively. tr is called the current rise time (voltage fall time). Both td and maximum permissible on state diA/dt are very much gate current dependent. High value of IgM and dig/dt at turn on reduces these times and increases maximum permissible on state diA/dt . It should be noted that large value of ig (IgM) and dig/dt are required during td and tr only. After this time period both vg and ig settles down to their steady value. A minimum ON time period tON (min) is required for homogeneous anode current conduction in the GTO. This time is also necessary for the GTO to be able to turn off its rated anode current.

To turn off a GTO the gate terminal is negatively biased with respect to the cathode. With the application of the negative bias the gate current starts growing in the negative direction. However, the anode voltage, current or the gate voltage does not change appreciably from there on state levels for a further time period called the storage time (ts). The storage time increases with the turn off anode current and decrease with digQ/dt. During storage time the load current at the cathode end is gradually diverted to the gate terminal. At the end of the storage time gate current reaches its negative maximum value IgQ. At this point both the junctions J2 & J3 of the GTO starts blocking voltage. Consequently, both the gate cathode and the anode cathode voltage starts rising towards their final value while the anode current starts decreasing towards zero. At the end of current fall time tf the anode current reaches 10% of its initial value after which both the anode current and the gate current continues to flow in the form of a current tail for a further duration of ttail. A GTO is normally used with a R-C turn off snubber. Therefore, VAK does not start to rise appreciably till tf. At this point VAK starts rising rapidly and exceeds the dc voltage Vd (VdM) (due to resonance of snubber capacitor with didt limiting inductor) before setting down at its steady value Vd . A GTO should not be retriggered within a minimum off period off (min) to avoid the risk of failure due to localized turn ON. GTOs have typically low turn off gain in the range of 4-5.

4. (a).3.Steady state and dynamic characteristics of a GTO

Steady state characteristics of a GTO

(a) Output characteristics ;(b) Gate characteristics.

This characteristic in the first quadrant is very similar to that of a thyristor as shown in Fig.(a). However, the latching current of a GTO is considerably higher than a thyristor of similar rating. The forward leakage current is also considerably higher. In fact, if the gate current is not sufficient to turn on a GTO it operates as a high voltage low gain transistor with considerable anode current. It should be noted that a GTO can block rated forward voltage only when the gate is negatively biased with respect to the cathode during forward blocking state. At least, a low value resistance must be connected across the gate cathode terminal. Increasing the value of this resistance reduces the forward blocking voltage of the GTO. Asymmetric GTOs have small (20-30 V) reverse break down voltage. This may lead the device to operate in reverse avalanche under certain conditions. This condition is not dangerous for the GTO provided the avalanche time and current are small. The gate voltage during this period must remain negative.

Fig.(b) shows the gate characteristics of a GTO. The zone between the min and max curves reflects parameter variation between individual GTOs. These characteristics are valid for DC and low frequency AC gate currents. They do not give correct voltage when the GTO is turned on with high dia/dt and dIG/dt. VG in this case is much higher.

(Topic Power Semiconductor- Power Bipolar Junction Transistor (BJT)Sub Topics Structure, Ton-Toff , V-I Characteristics of BJT)

4.(b) POWER SEMICONDUCTOR- Power Bipolar Junction Transistor (BJT)

4.(b).1Constructional Features of a Power BJT

Power transistors face the same conflicting design requirements (i.e. large off state blocking voltage and large on state current density) as that of a power diode. Therefore, it is only natural to extend some of the constructional features of power diodes to power BJT. Following Section summarizes some of the constructional features of a Power BJT. Since Power Transistors are predominantly of the n-p-n type, in this section and subsequently only this type of transistor will be discussed.

A power BJT has vertically oriented alternating layers of n type and p type semiconductor materials as shown in Fig 1.17(a). The vertical structure is preferred for power transistors because it maximizes the cross sectional area through which the on state current flows. Thus, on state resistance and power lass is minimized.

In order to maintain a large current gain (and hence reduce base drive current) the emitter doping density is made several orders of magnitude higher than the base region. The thickness of the base region is also made as small as possible.

In order to block large voltage during OFF state a lightly doped collector drift region is introduced between the moderately doped base region and the heavily doped collector region. The function of this drift region is similar to that in a Power Diode. However, the doping density donation of the base region being moderate the depletion region does penetrate considerably into the base. Therefore, the width of the base region in a power transistor cannot be made as small as that in a signal level transistor. This comparatively larger base width has adverse effect on the current gain () of a Power transistor which typically varies within 5-20. As will be discusses later the collector drift region has significant effect on the output characteristics of a Power BJT.

Practical Power transistors have their emitters and bases interleaved as narrow fingers. This is necessary to prevent current crowding and consequent second break down. In addition multiple emitter structure also reduces parasitic ohmic resistance in the base current path. These constructional features of a Power BJT are shown schematically in

Fig.(a). Fig.(b) shows the photograph of some community available Power transistors in different packages.

Constructional Features of a Power Bipolar Junction Transistor

(a) Schematic of Construction,

(b) Photograph of commercial packages.

4.(b).2 Switching characteristics of a Power Transistor

Turn On characteristics of a Power Transistor

From the description of the basic operating principle of a power transistor presented in the previous sections it is clear that minority carriers must be moved across different regions of a power transistor in order to make it switch between cut off and saturation regions of operation. The time delay in the switching operation of a power transistor is due to the time taken by the minority carriers to reach appropriate density levels in different regions. The exact level of minority carrier densities (and depletion region widths) required for proper switching is determined by the collector current and biasing collector voltage during switching, both of which are determined by external circuits. The rate at which these densities are attained is determined by the base current waveform. Therefore, the switching characteristics of a power transistor are always specified in relation to the external load circuit and the base current waveform as shown in Fig. Which shows a clamped inductive switching circuit with a flat base drive.

Turn ON characteristics of a power transistor; (a) Switching circuit, (b) Switching wave forms

The switching wave forms shown in Fig.(b) are the expanded and to some extent idealized version of the actual waveforms that will be observed in a clamped inductive switching circuit as shown in Fig. (a). Some simplifying assumptions have been made to draw these waveforms. These are

The load inductor has been assumed to be large enough so that the load current does

not change during Turn ON period.

Reverse recovery characteristics of D has been ignored.

All parasitic elements have been ignored.

Before t = 0, the transistor (Q) was in the OFF state. In order to utilize the increased break down voltage (VCBO) the base-emitter junction of a Power Transistor is usually reverse biased during OFF state. Under this condition only negligible leakage current flows through the transistor. Power loss due to this leakage current is negligible compared to other components of power loss in a transistor. Therefore, it is not shown in Fig (b). The entire load current flows through the diode and VCE is clamped to VCC (approximately). To turn the transistor ON at t = 0, the base biasing voltage VBB changes to a suitable positive value. This starts the process of charge redistribution at the base-emitter junction. The process is akin to charging of a capacitor. Indeed, the reverse biased base emitter junction is often represented by a voltage dependent capacitor, the value of which is given by the manufacturer as a function of the base-emitter reverse bias voltage. The rising base current that flows during this period can be thought of as this capacitor charging current. Finally at t = td the BE junction is forward biased. The junction voltage and the base current settles down to their steady state values. During this period, called the Turn ON delay time no appreciable collector current flows. The values of iO and VCE remains essentially at their OFF state levels.

At the end of the delay time (td ON) the minority carrier density at the base region quickly approaches its steady state distribution and the collector current starts rising while the diode current (id) starts falling. At t = tdON + tri the collector current becomes equal to the load current (and id becomes zero) IL. At this point D starts blocking reverse voltage and VCE becomes unclamped. tri is called the current rise time of the transistor.

At the end of the current rise time the diode D regains reverse blocking capacity. The collector voltage VCE which has so far been clamped to VCC because of the conducting diode D starts falling towards its saturation voltage VCE (sat). The initial fall of VCE is rapid. During this period the switching trajectory traverses through the active region of the output characteristics of the transistor. At the end of this rapid fall (tfv1) the transistor enters quasi saturation region. The fall of VCE in the quasi saturation region is considerably slower. At the end of this slow fall (tfv2) the transistor enters hard saturation region and the collector voltage settles down to the saturation voltage level VCE (sat) corresponding to the load current IL. Turn ON process ends here. The total turn on time is thus, TSW (ON) = td (ON) + tri + tfv1 +tfv2.

Power loss occurs at all time during the operation of a power transistor. However, the collector leakage current is usually negligibly small and power loss due it can be safely neglected in comparison to the power loss during ON condition. Power loss occurs during Turning ON a Power transistor due to simultaneous existence of non-zero VCE and ic during tri, tfv1, and tfv2. The energy lost during these periods is called the Turn ON loss and given by the area under the Pl curve in Fig (b). The average Turn ON loss is obtained by dividing this area by (tri + tfv1 + tfv2). For safe Turn ON this average power loss must be less than the limit set on the maximum power dissipation in the FBSOA corresponding to a pulse width greater than tri + tfv1 + tfv2. Similar restriction with respect to second break down should also be observed.

Turn ON time can be reduced by increasing the base current. However large base current increases the quantity of excess carrier in the base and collector drift region which has to be removed during Turn Off. As will be seen later this increases the Turn OFF time. The Turn ON delay time can however be reduced by boosting the base current at the beginning of the Turn ON process. This can be achieved by connecting a small capacitance across RB. This increases the rate of rise of VBE & iB. Therefore, Turn ON delay time decreases. However, in steady state iB settle downs to a value determined by RB & VBB and no adverse effect on the Turn OFF time is observed.

In figure (b) the reverse recovery current of D has been neglected. If this current is not negligible then for safe Turn ON operation the sum of the load current and the diode reverse recovery current must be less than the ICM rating of the transistor. Thermal and second break down limits must also be observed.

It should be noted that there is some power loss at the BE junction as well. This power loss depends on the current gain of the transistor during hard saturation. Since current gain reduces during saturation (typically between 5 to 10) this power loss may become significant. Manufacturers usually provide the values of td (ON), tri, tfv as functions of ic for a given base current and case temperature.

Turn Off Characteristics of a Power Transistor

During Turn OFF a power transistor makes transition from saturation to cut off region of operation. Just as in the case of Turn ON, substantial redistribution of minority charge carriers is involved in the Turn OFF process. Idealized waveforms of several important variables in the clamped inductive switching circuit of Fig. (a) during the Turn OFF process of Q are shown in Fig (a)

Turn off characteristics of a BJT.

(a) Switching wave forms (b) Switching trajectory

The Turn OFF process starts with the base drive voltage going negative to a value -VBB. The base-emitter voltage however does not change from its forward bias value of VBE(sat) immediately, due to the excess, minority carriers stored in the base region. A negative base current starts removing this excess carrier at a rate determined by the negative base drive voltage and the base drive resistance. After a time ts called the storage time of the transistor, the remaining stored charge in the base becomes insufficient to support the transistor in the hard saturation region. At this point the transistor enters quasi saturation region and the collector voltage starts rising with a small slope. After a further time interval trv1 the transistor completes traversing through the quasi saturation region and enters the active region. The stored charge in the base region at this point is insufficient to support the full negative base current. VBE starts falling forward VBB and the negative base current starts reducing. In the active region, VCE increases rapidly towards VCC and at the end of the time interval trv2 exceeds it to turn on D. VCE remains clamped at VCC, thereafter by the conducting diode D. At the end of trv2 the stored base charge can no longer support the full load current through the collector and the collector current starts falling. At the end of the current fall time tfi the collector current becomes zero and the load current freewheels through the diode D. Turn OFF process of the transistor ends at this point. The total Turn OFF time is given by Ts (OFF) = ts + trv1 + trv2 + tfi

As in the case of Turn ON considerable power loss takes place during Turn OFF due to simultaneous existence of ic and VCE in the intervals trv1, trv2 and tfi. The last trace of Fig (a) shows the instantaneous power loss profile during these intervals. The total energy last per turn off operation is given by the area under this curve. For safe turn off the average power dissipation during trv1 + trv2 + tfi should be less than the power dissipation limit set by the FBSOA corresponding to a pulse width greater than trv1 + trv2 + tfi. Turn OFF time intervals of a power transistor are strongly influenced by the operating conditions and the base drive design. Manufacturers usually specify these values as functions of collector current for given positive and negative base current and case temperatures. Variations of these time intervals as function of the ratio of positive to negative base currents for different collector currents are also specified.

In this section and the precious one inductive load switching has been considered. However, if the load is resistive. The freewheeling diode D will not be used. In that case the collector voltage (VCE) and collector current (ic) will fall and rise respectively together during Turn ON and rise and fall respectively together during Turn OFF. Other characteristics of the switching process will remain same. The switching Power loss in this case will also be substantially lower.

4.(b).3 i-v characteristics of a Power Transistor

A typical output (iC Vs VCE) characteristics of an n-p-n type power transistor is shown in Fig . A power transistor exhibits Cut off, Active and Saturation regions of operation in its output characteristics similar to a signal level transistor. In fact output characteristics of a Power Transistor in the Cut off and Active regions are qualitatively identical to a signal level transistor. Certain quantitative restrictions apply, however, which are discussed next.

Output ( ic VCE ) characteristics of an n p n type Power Transistor

In the cut off region (iB 0) the collector current is almost zero. The maximum voltage between collector and emitter under this condition is termed Maximum forward blocking voltage with base terminal open (iB = 0) and is denoted by VCEO. For all practical purpose this is the maximum voltage that can be applied in the forward direction (C positive with respect to E) across a power transistor since a power transistor is expected to see any significant forward voltage only with iB = 0. This blocking voltage can however be increased to a value VCBO by keeping the emitter terminal open. In this case iB< 0. Actually VCBO is the breakdown voltage of the collector base junction. However, since the open base configuration is more common the value of VCEO is used by the manufacturers as the maximum voltage rating of power transistor. Power transistors have poor reverse voltage withstanding capability due to low break down voltage of the base-emitter junction. Therefore, reverse voltage (C negative with respect to E) should not appear across a power transistor.

In the active region the ratio of collector current to base current (DC current Gain ()) remains fairly constant up to certain value of the collector current after which it falls off rapidly. Manufacturers usually provide a graph showing the variation of as a function of the collector current for different junction temperatures and collector emitter voltages. This graph is useful for designing the base drive of a Power transistor. Typically, the value of the dc current gain of a Power transistor is much smaller compared to their signal level counterpart.

The maximum collector-emitter voltage that a power transistor can withstand in active region is determined by the Base collector avalanche break down voltage. This voltage, denoted by VSUS in Fig, is usually smaller than VCEO. The voltages VSUS can be attained only for relatively lower values of collector current. At higher collector current the limit on the total power dissipation defines the boundary of the allowable active region as shown in Fig .

At still higher levels of collector currents the allowable active region is further restricted by a potential failure mode called the Second break down. It appears on the output characteristics of the BJT as a precipitous drop in the collector-emitter voltage at large collector currents. The collector voltage drop is often accompanied by significant rise in the collector current and a substantial increase in the power dissipation. Most importantly this dissipation is not uniformly spread over the entire volume of the device but is concentrated in highly localized regions. This localized heating is a combined effect of the intrinsic non uniformity of the collector current density distribution across the cross section of the device and the negative temperature coefficient of resistively of minority carrier devices which leads to the formation of current filamements (localized areas of very high current density) by a positive feed-back mechanism. Once current filaments are formed localized thermal runaway quickly takes the junction temperature beyond the safe limit and the device is destroyed.

It is in the saturation region that the output characteristics of a Power transistor differ significantly from its signal level counterpart. In fact the saturation region of a Power transistor can be further subdivided into a quasi saturation region and a hard saturation region. Appearance of the quasi saturation region in the output characteristics of a power transistor is a direct consequence of introducing the drift region into the structure of a power transistor. In the quasi saturation region the base-collector junction is forward biased but the lightly doped drift region is not completely shorted out by excess minority carrier injection from the base. The resistivity of this region depends to some extent on the base current. Therefore, in the quasi saturation region, the base current still retains some control over the collector current although the value of decreases significantly. Also, since the resistivity of the drift region is still significant the total voltage drop across the device in this mode of operation is higher for a given collector current compared to what it will be in the hard saturation region.

In the hard saturation region base current looses control over the collector current which is determined entirely by the collector load and the biasing voltage VCC. This behavior is similar to what happens in a signal transistor except that the drift region of a power transistor continues to offer a small resistance even when it is completely shorted out (by excess carrier injection from the base). Therefore, for larger collector currents the collector-emitter voltage drop is almost proportional to the collector current. Manufacturers usually provide the plots of the variation of VCE (sat) vs. iC for different values of base current and junction temperature. Curves showing the variation of VCE (sat) with iB for different values of iC and junction temperature are also provided by certain manufacturers.

Applicable operating limits on a power transistors are compactly represented in two diagrams called the Forward Bias Safe Operating Area (FBSOA) and the Reverse Bias Safe Operating Area. (RBSOA) applicable to iB > 0 and iB 0 conditions respectively. Typical safe operating areas of power transistors are shown in Fig .

Safe operating areas of a Power Transistor. (a) FBSOA; (b) RBSOA.

The horizontal upper limit of the FBSOA is determined by the maximum allowable collector current (ICM) that should not be exceeded even as a pulse. Exceeding this current limit may cause bonding wire or metallization of the wafer to vaporize or otherwise fail. Since a power transistor does not have any appreciable reverse voltage blocking capacity they are usually not used in ac circuits. However, if the collector current, for some reason is not dc or a pulse, the rms value of the collector current waveform should not exceed this limit.

The next applicable limit in the FBSOA (green lines) corresponds to the restriction on the maximum allowable power dissipation and maximum junction temperature. Since FBSOA is shown on a log-log scale constant Power dissipation (Pd = VCE iC) limits appear as straight lines. This limit is different for dc and pulsed operation due to the thermal time constant of the device. The DC limit is applicable to the average power loss if the transistor remains continuously in the conduction state (active, quasi saturation or saturation). On the other hand the pulsed power dissipation limits are applicable to conduction duration up to the value marked on them (the figures on the right of Fig (a)). Pulsed power dissipation limits are specified for a low value (1%-2%) of duty cycle and are useful for shaping the switching trajectory of the transistor as will be seen later.

The third limit of the FBSOA (red line) arises due to the second break down failure mode of a Power transistor. It shows the limiting combinations of collector voltage and current so that second break down does not occur. On the log log scale of the FBSOA this limit also appears as a straight limit. Like the maximum power dissipation limit, the second break down limit is also different for DC and Pulsed operation of different pulse durations. The interpretation of the pulse duration (marked on the right side of Fig (a)) corresponding to a particular limit is also same.

The final limit of the FBSOA corresponds to the forward biased avalanche break down voltage (VSUS) of the transistor and appear as a vertical line in the FBSOA at VCE = VSuS

The FBSOA of a Power transistor is given at a specified case temperature. Both the maximum power dissipation limit and the second break down limits are to be rated as per the rating characteristics provided by the manufacturers when the case temperature exceeds the specified value.

In contrast to the FBSOA, the RBSOA (Fig (b)) is plotted on a linear scale and has a more rectangular shape. RBSOA is a switching SOA since a transistor cannot conduct current for any appreciable duration under reverse biased condition. It essentially shows the limiting permissible combinations of VCE & iC with base emitter junction reverse biased. The upper horizontal limit corresponds to the maximum allowable collector current (ICM) and is same as that in the FBSOA. The right hand side vertical limit corresponds the avalanche break down voltage of the transistor with reverse bias. If the base terminal is open (i,e, iB = 0) then this voltage is VCEO. If a negative voltage is applied across the BE junction the right hand side limit of the RBSOA increases somewhat to the value VCBO at low value of the collector current.

In addition to the applicable limits on the output characteristics as represented in the FBSOA and the RBSOA, limiting specification with respect to the base emitter junction is also provided by the manufacturer. Typical specifications that are provided are

VEBO : This is maximum allowable reverse bias voltage across the B-E junction

IB : Maximum allowable average base current at a given case temperature.

IBM : Maximum allowable peak base current at a given case temperature and of specified

pulse duration.

The input characteristics (iB Vs VBE) at a given case temperature is also provided.

Part-A Question

1. What are the advantages of GTO over SCR?

2. Compare Power MOSFET and BJT.

3. What are the drawbacks of GTO?

Part-B Question

1.Briefly discuss the V-I characteristics of BJT.

2.Draw and explain the switching characteristics of GTO.

(Topic Power Semiconductor- Insulated Gate Bipolar Transistor (IGBT)Sub Topics Structure, Ton-Toff , V-I Characteristics of IGBT)

5. POWER SEMICONDUCTOR- Insulated Gate Bipolar Transistor (IGBT)

5.1.Constructional Features of an IGBT

Vertical cross section of a n channel IGBT cell is shown in Fig . Although p channel IGBTs are possible n channel devices are more common and will be the one discussed in this lesson.

Vertical cross section of an IGBT cell.

The major difference with the corresponding MOSFET cell structure lies in the addition of a p+ injecting layer. This layer forms a pn junction with the drain layer and injects minority carriers into it. The n type drain layer itself may have two different doping levels. The lightly doped n- region is called the drain drift region. Doping level and width of this layer sets the forward blocking voltage (determined by the reverse break down voltage of J2) of the device. However, it does not affect the on state voltage drop of the device due to conductivity modulation as discussed in connection with the power diode. This construction of the device is called Punch Trough (PT) design. The Non-Punch Through (NPT) construction does not have this added n+ buffer layer. The PT construction does offer lower on state voltage drop compared to the NPT construction particularly for lower voltage rated devices. However, it does so at the cost of lower reverse break down voltage for the device, since the reverse break down voltage of the junction J1 is small. The rest of the construction of the device is very similar to that of a vertical MOSFET including the insulated gate structure and the shorted body (p type) emitter (n+ type) structure. The doping level and physical geometry of the p type body region however, is considerably different from that of a MOSFET in order to defeat the latch up action of a parasitic thyristor embedded in the IGBT structure. A large number of basic cells as shown in Fig. are grown on a single silicon wafer and connected in parallel to form a complete IGBT device.

Operating principle of an IGBT

Operating principle of an IGBT can be explained in terms of the schematic cell structure and equivalent circuit of Fig (a) and (c). From the input side the IGBT behaves essentially as a MOSFET. Therefore, when the gate emitter voltage is less than the threshold voltage no inversion layer is formed in the p type body region and the device is in the off state. The forward voltage applied between the collector and the emitter drops almost entirely across the junction J2. Very small leakage current flows through the device under this condition. In terms of the equivalent current of Fig 1.29(c), when the gate emitter voltage is lower than the threshold voltage the driving MOSFET of the Darlington configuration remains off and hence the output p-n-p transistor also remains off.

Parastic thyristor in an IGBT cell.

(a) Schematic structure (b) Exact equivalent circuit (c) Approximate equivalent circuit

When the gate emitter voltage exceeds the threshold, an inversion layer forms in the p type body region under the gate. This inversion layer (channel) shorts the emitter and the drain drift layer and electron current flows from the emitter through this channel to the drain drift region. This in turn causes substantial hole injection from the p+ type collector to the drain drift region. A portion of these holes recombine with the electrons arriving at the drain drift region through the channel. The rest of the holes cross the drift region to reach the p type body where they are collected by the source metallization.

From the above discussion it is clear that the n type drain drift region acts as the base of the output p-n-p transistor. The doping level and the thickness of this layer determine the current gain of the p-n-p transistor. This is intentionally kept low so that most of the device current flows through the MOSFET and not the output p-n-p transistor collector. This helps to reduce the voltage drop across the body spreading resistance shown in Fig (b) and eliminate the possibility of static latch up of the IGBT. The total on state voltage drop across a conducting IGBT has three components. The voltage drop across J1 follows the usual exponential law of a pn junction. The next component of the voltage drop is due to the drain drift region resistance. This component in an IGBT is considerably lower compared to a MOSFET due to strong conductivity modulation by the injected minority carriers from the collector. This is the main reason for reduced voltage drop across an IGBT compared to an equivalent MOSFET. The last component of the voltage drop across an IGBT is due to the channel resistance and its magnitude is equal to that of a comparable MOSFET.

5.2 Switching characteristics of IGBT

Switching characteristics of the IGBT will be analyzed with respect to the clamped inductive switching circuit shown in Fig .(a). The equivalent circuit of the IGBT shown in Fig .(b) will be used to explain the switching waveforms.

Fig. Inductive switching circuit using an IGBT

(a) Switching circuit (b) Equivalent circuit of the IGBT

The switching waveforms of an IGBT are, in many respects, similar to that of a Power MOSFET. This is expected, since the input stage of an IGBT is a MOSFET as shown in Fig (b). Also in a modern IGBT a major portion of the total device current flows through the MOSFET. Therefore, the switching voltage and current waveforms exhibit a strong similarity with those of a MOSFET. However, the output p-n-p transistor does have a significant effect on the switching characteristics of the device, particularly during turn off. Another important difference is in the gate drive requirement. To avoid dynamic latch up, (to be discussed later) the gate emitter voltage of an IGBT is maintained at a negative value when the device is off.

Fig. Switching waveform of an IGBT

The switching waveforms of an IGBT are shown in Fig 1.32. Similarity of these waveforms with those of a MOSFET is obvious. To turn on the IGBT the gate drive voltage changes from Vgg to +Vgg. The gate emitter voltage VgE follows Vgg with a time constant 1. Since the drain source voltage of the drive MOSFET is large the gate drain capacitor assumes the lower value CGD1. The collector current ic does not start increasing till VgE reaches the threshold voltage VgE (th). Thereafter, ic increases following the transfer characteristics of the device till VgE reaches a value VgE IL corresponding to ic = iL. This period is called the current rise time tri. The freewheeling diode current falls from IL to zero during this period. After ic reaches IL, VgE becomes clamped at VgE IL similar to a MOSFET. VCE also starts falling during this period. First VCE falls rapidly (tfv1) and afterwards the fall of VCE slows down considerably. Two factors contribute to the slowing down of voltage fall. First the gate-drain capacitance Cgd will increase in the MOSFET portion of the IGBT at low drain-source voltages. Second, the pnp transistor portion of the IGBT traverses the active region to its on state more slowly than the MOSFET portion of the IGBT. Once the pnp transistor is fully on after tfv2, the on state voltage of the device settles down to VCE (sat). The turn ON process ends here.

The turn off process of an IGBT follows the inverse sequence of turn ON with one major difference. Once VgE goes below VgE (th) the drive MOSFET of the IGBT equivalent circuit turns off. During this period (tfi1) the device current falls rapidly. However, when the drive MOSFET turns off, some amount of current continues of flow through the output p-n-p transistor due to stored charge in its base. Since there is no reverse voltage applied to the IGBT terminals that could generate a negative drain current, there is no possibility for removing the stored charge by carrier sweep-out. The only way these excess carriers can be removed is by recombination within the IGBT. During this recombination period (tfi2) the remaining current in the IGBT decays relatively slowly forming a current fail. A long tfi2 is undesirable, because the power dissipation in this interval will be large due to full collector-emitter voltage. tfi2 can be reduced by decreasing the excess carrier life time in the p-n-p transistor base. However, in the process, on state losses will increase. Therefore, judicious design tradeoffs are made in a practical IGBT to give minimum total loss.

5.3 Steady state characteristics of an IGBT

The i-v characteristics of an n channel IGBT is shown in Fig (a). They appear qualitatively similar to those of a logic level BJT except that the controlling parameter is not a base current but the gate-emitter voltage.

Static characteristics of an IGBT

(a) Output characteristics; (b) Transfer characteristics

When the gate emitter voltage is below the threshold voltage only a very small leakage current flow though the device whiles the collector emitter voltage almost equals the supply voltage (point C in Fig .(a)). The device, under this condition is said to be operating in the cut off region. The maximum forward voltage the device can withstand in this mode (marked VCES in Fig (a)) is determined by the avalanche break down voltage of the body drain p-n junction. Unlike a BJT, however, this break down voltage is independent of the collector current as shown in Fig .(a). IGBTs of Non-punch through design can block a maximum reverse voltage (VRM) equal to VCES in the cut off mode. However, for Punch through IGBTs VRM is negligible (only a few tens of volts) due the presence of the heavily doped n+ drain buffer layer.

As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the active region of operation. In this mode, the collector current ic is determined by the transfer characteristics of the device as shown in Fig (b). This characteristic is qualitatively similar to that of a power MOSFET and is reasonably linear over most of the collector current range. The ratio of ic to (VgE VgE (th)) is called the forward transconductance (gfs) of the device and is an important parameter in the gate drive circuit design. The collector emitter voltage, on the other hand, is determined by the external load line ABC as shown in Fig (a). As the gate emitter voltage is increased further ic also increases and for a given load resistance (RL) VCE decreases. At one point VCE becomes less than VgE VgE(th). Under this condition the driving MOSFET part of the IGBT (Fig (c)) enters into the ohmic region and drives the output p-n-p transistor to saturation. Under this condition the device is said to be in the saturation mode. In the saturation mode the voltage drop across the IGBT remains almost constant reducing only slightly with increasing VgE.

In power electronic applications an IGBT is operated either in the cut off or in the saturation region of the output characteristics. Since VCE decreases with increasing VgE, it is desirable to use the maximum permissible value of VgE in the ON state of the device. VgE (Max) is limited by the maximum collector current that should be permitted to flow in the IGBT as dictated by the latch-up condition discussed earlier. Limiting VgE also helps to limit the fault current through the device. If a short circuit fault occurs in the load resistance RL (shown in the inset of Fig. (a)) the fault load line is given by CF. Limiting VgE to VgE6 restricts the fault current corresponding to the operating point F. Most IGBTs are designed to with stand this fault current for a few microseconds within which the device must be turned off to prevent destruction of the device.

It is interesting to note that an IGBT does not exhibit a BJT-like second break down failure. Since, in an IGBT most of the collector current flows through the drive MOSFET with positive temperature coefficient the effective temperature coefficient of VCE in an IGBT are slightly positive. This helps to prevent second break down failure of the device and also facilitates paralleling of IGBTs.

Part-A Question

List the advantages of the IGBT.

Part-B Question

1.Explain the turn-on and turn-of characteristics of IGBT with neat waveforms.

2.Discuss in detail the static and switching characteristics of IGBT.

(Topic Power Semiconductor- Metal Oxide Semiconductor Field Effect Transistor (MOSFET)Sub Topics Structure, Ton-Toff , V-I Characteristics of MOSFET)

6. POWER SEMICONDUCTOR- MOSFET

6.1 Constructional Features of a Power MOSFET

As mentioned in the introduction section, Power MOSFET is a device that evolved from MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs were by redesigning lateral MOSFET to increase their voltage blocking capacity. The resulting technology was called lateral double defused MOS (DMOS). However it was soon realized that much larger breakdown voltage and current ratings could be achieved by resorting to a vertically oriented structure. Since then, vertical DMOS (VDMOS) structure has been adapted by virtually all manufacturers of Power MOSFET. A power MOSFET using VDMOS technology has vertically oriented three layer structure of alternating p type and n type semiconductors as shown in Fig (a) which is the schematic representation of a single MOSFET cell structure. A large number of such cells are connected in parallel (as shown in Fig (b)) to form a complete device.

Schematic construction of a power MOSFET

(a) Construction of a single cell. (b) Arrangement of cells in a device.

The two n+ end layers labeled Source and Drain are heavily doped to approximately the same level. The p type middle layer is termed the body (or substrate) and has moderate doping level (2 to 3 orders of magnitude lower than n+ regions on both sides). The n- drain drift region has the lowest doping density. Thickness of this region determines the breakdown voltage of the device. The gate terminal is placed over the n- and p type regions of the cell structure and is insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate oxide). The source and the drain region of all cells on a wafer are connected to the same metallic contacts to form the Source and the Drain terminals of the complete device. Similarly all gate terminals are also connected together. The source is constructed of many (thousands) small polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source regions, to some extent, influences the ON state resistance of the MOSFET.

Parasitic BJT in a MOSFET cell.

One interesting feature of the MOSFET cell is that the alternating n+ n- p n+ structure embeds a parasitic BJT (with its base and emitter shorted by the source metallization) into each MOSFET cell as shown in Fig. The nonzero resistance between the base and the emitter of the parasitic npn BJT arises due to the body spreading resistance of the p type substrate. In the design of the MOSFET cells special care is taken so that this resistance is minimized and switching operation of the parasitic BJT is suppressed. With an effective short circuit between the body and the source the BJT always remain in cut off and its collector-base junction is represented as an anti parallel diode (called the body diode) in the circuit symbol of a Power MOSFET.

Operating principle of a MOSFET

At first glance it would appear that there is no path for any current to flow between the source and the drain terminals since at least one of the p n junctions (source body and body-Drain) will be reverse biased for either polarity of the applied voltage between the source and th