UNIVERSITY OF SOUTHERN CALIFORNIA

DEPARTMENT OF ELECTRICAL ENGINEERING

EE 477 LAB NO 3 P2TOPIC: NEURAL NETWORK DESIGN

AUTHOR: Sriram Mukund

USC ID: 6327-1480-71

DATE: 12/07/2010

NEURAL NETWORK DESIGN =>The NEURAL network that we are designing uses the NEURON circuit that we have designed earlier.

This particular neural network has 14 neurons that are interconnected to for a network that recognizes a particular sequence of inputs.

The input signals are K1, K2, K3, K5. The sequence it recognizes is K3, K3, K3, 0, K3, K3, K3, 0, K3, K5, K1, K2, K3, 0. "0" means no inputs are high. The recognition neuron is AP14. Only one key can be pressed at a time.

The network was designed in 3 separate parts and then later connected together.

Part 1: This circuit used 3 neurons and its function is to recognize the K3 input.

Part 2: This circuit uses the circuit designed in Part 1 and 5 more neurons. Its function is to detect a repeated sequence of the input K3.

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Part 3: This circuit uses the circuit designed in Part 2 and 6 more neurons. Its function is to recognize the remaining inputs, including K3 (K1, K2, K3, K5) to make up the desired sequence.

NEURAL NETWORK CIRCUIT:(AREA & DELAY)

The dimensions of the layout design was found to be: 56.4 μm x 137.7 μm

The delay (clock period) of the of the layout design was found to be: 1.3 ns

Hence, the Area - Delay Product of the circuit is: 10096.164 x 1021 m2s

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SCHEMATICS =>I. NEURON:

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II. NEURAL NETWORK PART 1:

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III. NEURAL NETWORK PART 2:

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IV. NEURAL NETWORK PART 3:

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NEURAL NETWORK LAYOUT =>

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CIRCUIT SIMULATION =>The final circuit (consisting of 14 neurons) was simulated by giving various inputs for K1, K2, K3, K5.

Simulation 1:The first simulation was done according to the following input sequence given in the diagram below.

Simulation 2:The second simulation required the circuit to recognize a particular sequence of inputs, which is given below.

K3, K3, K3, 0, K3, K3, K3, 0, K3, K5, K1, K2, K3, 0.

For the second simulation, only the output signals AP1 and AP3 will fire and the remaining will not. This is because the circuit designed recognized only a particular sequence of inputs. It recognizes the K3 repetition in the beginning but later does not.

Neurons N1 and N2 have their inhibitory inputs I asserted (low), as do all the neurons in the entire network except N3. The 3 inputs shown to all neurons are for inputs A, B and C. Input D is tied low for all neurons. Control inputs C1, C4, C3 and C2 are tied as follows:  C1 = Vdd, C4 = Vdd, C2 = Vdd, C3 = 0.0v.

The clock period for which the circuit was functioning correctly was found. The values are different for the schematic and the extracted layout.

Clock Period (Schematic): ## # 1.0 nsClock Period (Extracted Layout): ## 1.3 ns

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SIMULATION RESULTS (WAVEFORMS) =>I. FOR SCHEMATIC (SIMULATION 1):

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II. FOR EXTRACTED LAYOUT (SIMULATION 1):

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III. FOR SCHEMATIC (SIMULATION 2):

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IV. FOR EXTRACTED LAYOUT (SIMULATION 2):

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CONCLUSION =>The neuron that we have designed earlier was used to create a neural network that recognizes a particular sequence of inputs, which is similar to the functioning of a STATE MACHINE.

After running two simulations for this circuit, we have seen the working of this circuit and this satisfies this requirement.

Due to the inclusion of capacitances in the extracted circuit, the clock period for the layout is more than the clock for the schematic.

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