Variation

2

Sources of Variation

1. Process (manufacturing) (physical) variations: Uncertainty in the parameters of fabricated devices and

interconnects − From die to die

− Within a particular die

2. Environmental (operating context) (temporal) (dynamic) variations: Uncertainty in the operating environment of a particular

device during its lifetime− Temperature

− Supply voltage

− Lifetime wear-out

3

Variation Classification

4

Supply Voltage Variation

5

Temperature Variation

Within die temperature variation

• Temperature Variation: Both the device and interconnect performance have

temperature dependence, − Higher temperature performance degradation.

6

Process Variation

• Process variation: Sample space: Set of manufactured dies Results in yield loss

− Y = # working die / # manuf. Die

A small portion of sample space is allowed to fail timing constraints

− CPU/GPU design: Speed/core binning: for different applications

− Lessens the requirement that all or very high percentage of die meets the fastest timing constraint

Process Variation

7

[Cadence]

8

Environmental Variation

• Environmental Variation: Sample space: Operational life of a chip A pessimistic analysis is required

− Should ensure correct operation throughout lifetime

Design that operates faster than necessary for much of its operational life

− loss in efficiency

One approach:− Runtime adaptivity of the design

• Environmental Variation: Treated by worst case analysis• Process variation: Treated statistically

9

Process Variation: Sources• PV Sources:

Var. in physical parameters (due to imperfect manufacturing):− Gate length or critical dimension (CD)− Gate oxide thickness− Channel doping concentration− Interconnect thickness− Interconnect width− …

− Dominant factors: CD and channel doping Var. in electrical parameters of components

− Vth

− Drive strength of transistors− Resistance of wires− Capacitance of wires− ….

Var. in circuit characteristics:− Delay − Power− Noise

10

Process Variation Sources

Leff2.3

2.2

2.1

1.9

1.8

50

100

0

2040

60

x 10-7

Wafer XWafer Y

2.0

[IBM, Intel and TSMC]

12

Process Variation

• A physical parameter variation may affect more than one electrical parameter: Wire width

− Wire capacitance

− Wire resistance

− Coupling noise

Gate oxide thickness − Drive current

− Vth

− Cg

13

Correlation

Must consider correlation between electrical parameters

If ignore correlation (Cw, Rw),

− In theory, both may be at worst–case values− Impossible in practice

• Correlation among physical parameters themselves An equipment variation (e.g. lens deviation) may impact

multiple physical parameter values (all metal layers and poly)

− Hard to model due to large number of equipment-related parameters

Most algorithms take physical parameters to be basic random variables

14

Classification• Types of physical-parameter variations:

1. Systematic (deterministic):− Show predictable variational trends across a chip

− Caused by known physical phenomena during manufacturing

− Can be predicted upfront by analyzing the designed layout

− Can be avoided in final stages − E.g. Metal fill, optical proximity effects

− But at early stages, common to be treated statistically

- Most of the time, not available to designers/CAD developers

- E.g.,regions with uniform metal densities have more uniform ILD thicknesses

15

Classification

• Types of physical-parameter variations:

2. Non-systematic (random):− Truly uncertain component of physical-parameter variations− Resulted from processes that are statistically independent of

the design implementation− Only the statistical characteristics are known at design time,− Must be modeled using RVs

• Common practice: In earlier stages, both systematic and nonsystematic

variations are modeled statistically As we move through the design process and more detailed

information is obtained, the systematic components can be modeled deterministically (if sufficient analysis capabilities are available)

Scaling Effect

A 4nm MOSFET predicted in mass production in 2020,

< 10 Si atoms are expected along the channel (IBM roadmap)

MOS transistors are rapidly becoming truly atomistic devices

Random variations are becoming dominant.

16

A 22nm MOSFET expected in mass production

50 Si atoms along the channel Large parameter

fluctuations

17

Classification

• Classification of variation:Die-to-die (inter-die) (global):

− Affects all devices on the same die in the same way

Within-die: WID (intra-die) (local) (on-chip: OCV):− Affects each device on the same die differently− E.g. some devices have larger/smaller CDs than nominal

D2D Variation

18

[Menezes07]

19

Classification• Types of within-die variation:

1. Spatially-correlated:− Many of the underlying processes that give rise to within-die variation change

gradually from one location to the next.

− Affect closely spaced devices in a similar manner

− Make them more likely to have similar characteristics than those placed far apart

2. Independent:− Statistically independent from all other devices

− Scaling Contribution of independent within-die variation is increasing

− With SC:− Leff,

− Temperature− Supply voltage

− No SC:− tox,

− Dopant concentration

20

Inter-die vs. Intra-die Variations

• Figures are courtesy of IBM, Intel and TSMC

Intra-die spatial Correlation

Inter-die global Correlation

Leff

References

• [Blaauw08] Blaauw, Chopra, Srivastava, Scheffer, “Statistical Timing Analysis: From Basic Principles to State of the Art,” IEEE Transactions on CAD, Vol. 27, No. 4, April 2008.

• [Forzan09] Forzan, Pandini, “Statistical static timing analysis: A survey,” Integration, The VLSI Journal, 42, 2009.

• [Menezes07] Menezes, “The Good, the Bad, and the Statistical,” Invited talk, ISPD 2007.

21