vectored interrupt controller 國立中山大學資訊工程系 嵌入式系統實驗室...
Post on 21-Dec-2015
243 views
TRANSCRIPT
Vectored Interrupt Controller
國立中山大學資訊工程系嵌入式系統實驗室
指導教授 : 黃英哲 教授研發人員 : 黃文凱 林易廷 陳俊璋
112/04/19 Vectored Interrupt Controller SIP 2
Outline
VIC IP 功能及特性 VIC IP 驗證及測試 VIC IP 之應用 IP Deliverables 之完整性
112/04/19 Vectored Interrupt Controller SIP 3
Outline
VIC IP 功能及特性 VIC IP 驗證及測試 VIC IP 之應用 IP Deliverables 之完整性
112/04/19 Vectored Interrupt Controller SIP 4
IP 功能介紹 本矽智產為一個相容於 AMBA(Advanced Microprocessor
Bus Architecture) 匯流排標準之向量化中斷控制器 (Vectored Interrupt Controller ,簡稱 VIC) 。
本 VIC 與傳統中斷控制器最大的不同點在於 VIC 能快速提供正確的中斷向量 (interrupt vector) 給 CPU 以節省掉許多辨識中斷源與查表的動作。
本 VIC 最多可以直接控制 32 個中斷源,在這 32 個中斷源中,最多可以有 16 個 IRQ 型態的中斷源被設定為向量化的中斷 (vectored interrupt) 。若系統中的中斷源大於 32 個,此 VIC 也提供了 daisy chain 介面供多個 VIC 串接以擴充中斷源的數目。
112/04/19 Vectored Interrupt Controller SIP 5
主要特色 功能完全相容於 ARM PrimeCell VIC (PL190)
I/O interface Interrupt priority logic Programmer’s model Programmer’s model for test Interrupt latency
提供完整的 AMBA simulation model 來協助使用者快速使用本 IP 來發展系統。
Coding style 確實通過 lint tools 之查核,以確保其 RTL code 為 100% 可合成碼。
功能驗證達到 100% code coverage 。
112/04/19 Vectored Interrupt Controller SIP 6
VIC Organization
Programmable interrupt detector
Non-vectored interrupt logic
Vectored interrupt 0
IRQ vector address and priority logic
Vectored interrupt 1
……
Vectored interrupt 15
IRQ0
IRQ1
IRQn
IRQ15
VectAddr0
VectAddr1
VectAddrn
VectAddr15
Daisy Chain Logic
IRQIN
VectAddrIn
VectAddrOut
FIQStatus
IRQStatus
IRQStatus
FIQIN
AHB slave interface
VICINTSOURCE
nVICIRQIN
nVICFIQIN
VICVECTADDRIN
VICVECTADDROUT
nVICFIQ
nVICIRQ
AHBsignals
AHBsignals
112/04/19 Vectored Interrupt Controller SIP 7
可組態資訊 (Configuration) 提供 ARM PrimeCell VIC 之基本可組態功能
向量化中斷源之指派、向量位址之設定 除此之外,本 VIC 還提供了使用者自行設定中斷偵測
機制 (programmable interrupt detection) 的功能 暫存器名稱 功能描述SenseType 選擇中斷源的觸發型態
0 = edge triggered, 1 = level sensitive
BothEdge 對於邊緣觸發的中斷源,設定其為單緣觸發或雙緣觸發0 = single edge, 1 = both edge
EventReg 選擇觸發準位或觸發緣0 = low level sensitive or falling edge triggered
1 = high level sensitive or rising edge triggered
112/04/19 Vectored Interrupt Controller SIP 8
電路合成結果 合成環境
Synthesizer : Synopsys Design Compiler Ver. 2000.11-SP2 Cell library : TSMC 0.35um provided by CIC (cb35os142.d
b) Operating conditions : Worst case Input delay : 30% of cycle time Output delay : 70% of cycle time
合成結果Version Speed Area
Performance-oriented 125 MHz 15,632 gates
Cost-oriented 50 MHz 12,831 gates
112/04/19 Vectored Interrupt Controller SIP 9
Coding Style Check: Lint Tools
本 IP 使用 nLint 進行 coding style 檢查,以提升 RTL code 之可合成性與合成效率
錯誤訊息視窗
錯誤碼之位置提示
112/04/19 Vectored Interrupt Controller SIP 10
Example of Bad Codesalways @(posedge clk or rst) begin if( rst ) dout <= 1’b0; else dout <= din; end
always @(posedge clk or posedge rst) begin if( rst ) dout <= 1’b0; else dout <= din; end
112/04/19 Vectored Interrupt Controller SIP 11
Outline
VIC IP 功能及特性 VIC IP 驗證及測試 VIC IP 之應用 IP Deliverables 之完整性
112/04/19 Vectored Interrupt Controller SIP 12
IP 驗證方法
Verification strategy
① Macro functional verification
② Real application verification
③ FPGA prototyping
Macro functional verification
Real application verification
FPGA protyping
112/04/19 Vectored Interrupt Controller SIP 13
Macro Functional Verification
針對 VIC 此顆 IP 進行功能驗證,要點包含: Programmer’s model Bus model Interrupt priority logic Interrupt latency
Test pattern generation 考慮各種 corner case ,以人工產生的方式來達到各種 code coverage 的 100% 。
112/04/19 Vectored Interrupt Controller SIP 14
Coverage Measurement: Use Verification Navigator
112/04/19 Vectored Interrupt Controller SIP 15
Report of the Measurement
112/04/19 Vectored Interrupt Controller SIP 16
Check for the Omitted Test Case
針對這些未測試到之 RTL statement 來產生對應的 test pa
ttern
112/04/19 Vectored Interrupt Controller SIP 17
Final Objective: 100% Code Coverage
112/04/19 Vectored Interrupt Controller SIP 18
Coverage Summary of ModelSim
112/04/19 Vectored Interrupt Controller SIP 19
Real Application Verification
ARM7TM like
Arbiter&
DecoderBIU
MemoryController
VectoredInterruptController
Adjust SystemClock Frequency
LCDPanel
LEDModule
KEYPAD
RS232Circuit
DIPSwitch System Clock resetn
BIU
AHB/APBBridge
APB Bus
UART
B I U
Keyboardinterface
B I U
LCDController
B I ULED
Displayswitch
B I U
AHB Bus
SRAM
nIRQnFIQ
Peripheral Interrupt Requests
Interrupt Request(to ARM7TM)
112/04/19 Vectored Interrupt Controller SIP 20
FPGA PrototypingVirtex
XCV2000EBG560
32K x 32bitROM
Emulator
LCD Display
LED Displa
y
Control System Clock
8 MHzClock
Generator
KeyPad
Receive Program(*.axf)
Receive and
Transmit Data
112/04/19 Vectored Interrupt Controller SIP 21
FPGA 合成結果 合成環境
Xilinx Foundation Series 4.1i
FPGA Demo system 合成結果Device XCV2000E, Package BG560, Speed -4
Number of Slices:
Total Number Slice Registers:
AMBA Platform based design
2,521 out of 38,400 6%
4,446 out of 19,200 23%
Total Number 4 input LUTs:
Maximum frequency:
Number of Block RAMs:
7,429 out of 38,400 19%
32 out of 160 20%
13.465MHz
112/04/19 Vectored Interrupt Controller SIP 22
Outline
VIC IP 功能及特性 VIC IP 驗證及測試 VIC IP 之應用 IP Deliverables 之完整性
112/04/19 Vectored Interrupt Controller SIP 23
IP 應用方法 : Connectivity (1) Standalone VIC connectivity
Daisychain
interface
VIC
nVICIRQ
nVICFIQ
nIRQ
nFIQ
CPU
VICINTSOURCE
nVICIRQIN
nVICFIQIN
VICVECTADDROUT
VICVECTADDRIN
tiedHIGH
tiedLOW
peripherals
AHB interface AHB interface
AHB
112/04/19 Vectored Interrupt Controller SIP 24
IP 應用方法 : Connectivity (2) Daisy-chained VIC connectivity
Daisychain
interface
VIC
nVICIRQ
nVICFIQ
nIRQ
nFIQ
CPU
VICINTSOURCE
nVICIRQIN
nVICFIQIN
VICVECTADDROUT
VICVECTADDRIN
AHB interface AHB interface
AHB
Daisychain
interface
VIC
VICINTSOURCE
nVICIRQIN
nVICFIQIN
VICVECTADDROUT
VICVECTADDRIN
tiedHIGH
tiedLOW
AHB interface
nVICIRQ
nVICFIQ
112/04/19 Vectored Interrupt Controller SIP 25
Outline
VIC IP 功能及特性 VIC IP 驗證及測試 VIC IP 之應用 IP Deliverables 之完整性
112/04/19 Vectored Interrupt Controller SIP 26
IP Deliverables (1) Design source codes
Verilog RTL codes Gate-level netlists
Files for verification Testbench files Test patterns for 100% code coverage Encrypted fast cycle-accurate-model of VIC Simulation scripts Waveform examples
112/04/19 Vectored Interrupt Controller SIP 27
IP Deliverables (2) Files for synthesis
Scripts for automatic synthesis Scripts for scan insertion and ATPG for 100% f
ault coverage Timing and area constraints
Files for integration Encrypted AMBA models for system-level simul
ation AHB decoder/arbiter, AHB/APB bridge, an 32-bit ARM
7-compitable processor, SRAM models, several peripherals and corresponding BIUs
112/04/19 Vectored Interrupt Controller SIP 28
IP Deliverables (3) Documentations
IP contest report One-page summary Functional specification Datasheet Verification guide Integration guide Application Notes Software code examples
Readme file
112/04/19 Vectored Interrupt Controller SIP 29
Directory Structures目錄 說明
./document 存放所有 IP 相關文件
./rtl 本 IP 的所有 synthesizable RTL code 皆存放於此
./gate 合成完所產生的 gate level netlist 會自動存放於此( 包含相關 timing 檔 )
./example 此目錄放有我們事先幫使用者製作好的訊號檔 (*.rc) ,使用者作完 simulation 後可以使用這些訊號檔來閱讀所產生的波型。
./simulation 跟 simulation 相關的檔案皆存放於此。包括 testbench 、provided models 、 file list for simulation (*.f)
./synthesis 放置合成用的 script file ,合成完所自動產生的 report檔也存放於此
./waveform 使用者執行 RTL simulation 時,所產生的波形檔會自動存放至此目錄下。