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Abstract—The alpha-power law developed by Takayasu Sakurai presents a simple yet useful characterization of MOSFET, which considers the velocity saturation effects of carriers and applies to recent submicrometer technology. The model can be verified in various environments: such as thru variations of supply voltage (VDD) and size of the CMOS inverter chain. Our analysis concluded that the alpha-power law predicts propagation delay within 5% of the measured delay, however, it is not applicable to a near-threshold operation region or a large circuit where the delay is greater. Thus, a new analytical model for a subthreshold and near-threshold region is needed for simulations and analytical treatment of circuit behavior.

Index Terms—alpha power law, delay, inverter chain, CMOS, low power designs, near-threshold.

I. INTRODUCTION imple yet practical models for MOSFETs are useful for analytical expression of circuit behavior and simulations.

The historical Shockley model has been used extensively; however, its application on recent short-channel submicrometer MOSFETs does not consider the velocity saturation effects of a carrier [1]. Thus, as a new approach to overcome these limitations, the alpha-power law MOSFET model developed by Takayasu Sakurai defines the voltage-current characteristics of MOSFETs and derives simple analytical expressions for the drain current, short-circuit power, logic threshold voltage, and propagation delay. CMOS inverter delay was first characterized by Burns [4], but more research on circuit behavior is needed that considers the submicrometer region, parasitic delay, voltage dependence, and gate-source capacitance [5].

In this paper, Section II compares the conventional Shockley model and the alpha-power law model. Section III provides a summary of the alpha-power law, focusing on the analytical representation of CMOS propagation delay. Section IV provides a methodology to extract necessary device parameters. Verification and analysis of the alpha-power law and a new analytical expression for the delay of CMOS inverters specifically for a near-threshold operation region are presented in Section V and VI. Section VII gives the conclusion and offers direction for future research.

II. COMPARISON WITH SHOCKLEY MODEL

A. Shockley Model The Shockley model expresses drain current as follows:

𝐼! =  

0                                                              ,𝑉!" ≤ 𝑉!!  (𝑐𝑢𝑡𝑜𝑓𝑓  𝑟𝑒𝑔𝑖𝑜𝑛)𝐾 𝑉!" − 𝑉!! 𝑉!" − 0.5𝑉!"!                                                                                                                                ,𝑉!" < 𝑉!"#$  (𝑙𝑖𝑛𝑒𝑎𝑟  𝑟𝑒𝑔𝑖𝑜𝑛)𝐾2𝑉!" − 𝑉!! !                                                                                                                      

                                     , (𝑉!" ≥ 𝑉!"#$  (𝑠𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛  𝑟𝑒𝑔𝑖𝑜𝑛)

where K is a drivability factor, and VDSAT is drain saturation voltage.

Fig. 1. Measured VDS-ID characteristics and the Shockley model [1]

The Shockley model does not accurately predict drain saturation voltage as it fails to consider the velocity saturation effects found in short-channel MOSFETs.

B. Alpha-Power Law Model The alpha-power law model expresses drain current by the following:

𝐼! =  

0                                                                  ,𝑉!" ≤ 𝑉!!  (𝑐𝑢𝑡𝑜𝑓𝑓  𝑟𝑒𝑔𝑖𝑜𝑛)𝐼!!!

𝑉!!!𝑉!"                          ,𝑉!" < 𝑉!"#$  (𝑙𝑖𝑛𝑒𝑎𝑟  𝑟𝑒𝑔𝑖𝑜𝑛)

𝐼!!!                                  ,𝑉!" ≥ 𝑉!"#$  (𝑠𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛  𝑟𝑒𝑔𝑖𝑜𝑛)

Sungil Kim, Undergraduate Student, Auburn University, Dr. Vishwani D. Agrawal, James J. Danaher Professor, Auburn University

Verification of the Alpha-Power Law by a CMOS Inverter Chain

S

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where

𝐼!!! =   𝐼!!𝑉!" − 𝑉!"𝑉!! − 𝑉!"

!

𝑉!!! =  𝑉!!𝑉!" − 𝑉!"𝑉!! − 𝑉!"

!/!

From the above expressions, the 𝛼-power law depends on VTH (threshold voltage), 𝛼  (velocity saturation index), VD0 (drain saturation voltage), and ID0 (drain current).

Fig. 2. 𝛼–power law MOS model [1]

The alpha-power law does not characterize a subthreshold (below threshold) or near-threshold region as shown in. 2.

III. DEVICE CHARACTERIZATION

A. Drain Current The alpha-power law model characterizes the drain current as the following equation. K is the device constant.

𝐼!" = 𝐾 𝑉!! − 𝑉!! !                            …                                  (3.1)

B. Delay From the alpha-power law MOS model, the delay is inversely dependent on 𝑉𝐷𝐷 − 𝑉𝑡ℎ

𝛼 [2]. To express equation 3.2 as an equality, device constant K, different from the K in equation 3.1, can be used as a multiplier.

𝐷𝑒𝑙𝑎𝑦   ∝     !!!!!!!!!! !  

                           …                                  (3.2)

C. Frequency The expression for frequency can be obtained from the delay.

𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦   ∝     !!!!!!!!

!!!                …                        (3.3)

IV. DEVICE PARAMETERS To verify the alpha-power law model, several parameters (𝐾, 𝑉𝑡ℎ, and 𝛼) were extracted using HSPICE and MATLAB. First, I-V Characteristics for a 45 nm BSIM bulk CMOS library from an ASU PTM model [3] were obtained through HSPICE as shown in Fig. 3. Then, necessary data was extracted: Vgs 0.5V to 1.0V for NMOS and Vgs 0V to 0.5V for PMOS (Vds was set to 0.5V). The data for these values were most consistent.

Fig. 3. I-V Characteristics for NMOS (top) and PMOS (bottom)

Using MATLAB, the best fits for 11 samples were found for NMOS (Fig. 4) and PMOS (Fig. 5). According to the alpha-power law, the drain current can be expressed using equation 3.1. For a NMOS device, a threshold voltage (Vth) of 0.25 and alpha of 1.3 best fitted the samples. Also, when the threshold increased, the drain current was underestimated. When alpha decreased, the slope of the curve increases. For a PMOS device, a threshold voltage (Vth) of 0.80 and alpha of 1.5 best fitted the samples. Also, when the threshold increased, the slope of the curve increased. When alpha increased to 1.5, the curve moved closer to the best fit.

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Fig. 4. Curve Fitting for NMOS

Fig. 5. Curve Fitting for PMOS

V. RESULTS

A. Inverter The CMOS inverter was designed with the Mentor

Graphics CAD tool (Design Architect). Using a 45 nm BSIM bulk CMOS library from the ASU PTM model [3], transient analysis was done using HSPICE. An input pulse wave was applied to check its timing and functionality as shown in Fig. 7. Then, the propagation delay was measured. The results are shown in Fig. 8.

Fig. 6. CMOS Inverter

Fig. 7. Verification of Inverter

Fig. 8. Delay for various VDD

B. Inverter Chain (Size = 5) An inverter chain with a size of 5 was created by repeating

the previously designed inverter with a capacitor of 10 pF five times using HSPICE. A 10 pF capacitor was used since average propagation delay (tPAVG), low-to-high delay (tPHL), and high-to-low delay (tPLH) were measured as shown in Table 2.

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Fig. 9. Inverter Chain of Size 5

Table 1. Delay of CMOS Inverter Chain for various VDD

VDD tPHL (ns) tPLH (ns) tPAVG (ns) 3.0 0.95 4.60 2.77 2.9 1.02 4.86 2.94 2.8 1.09 5.13 3.11 2.7 1.16 5.40 3.28 2.6 1.25 5.66 3.45 2.5 1.32 5.90 3.61 2.4 1.39 6.14 3.76 2.3 1.46 6.34 3.90 2.2 1.52 6.51 4.02 2.1 1.58 6.66 4.12 2.0 1.63 6.82 4.23 1.9 1.67 6.99 4.33 1.8 1.72 7.17 4.45 1.7 1.76 7.40 4.58 1.6 1.80 7.71 4.76 1.5 1.84 7.97 4.90 1.4 1.88 8.36 5.12 1.3 1.95 8.85 5.40 1.2 2.03 9.47 5.75 1.1 2.14 10.29 6.21 1.0 2.29 11.42 6.86 0.9 2.53 13.02 7.77 0.8 2.87 15.55 9.21 0.7 3.44 19.43 11.43 0.6 4.77 23.26 14.01 0.5 8.83 7.56 8.20

When NMOS is discharging the output capacitors, the effect of PMOS can be ignored. The predicted delay of tPHL and the measure delay of the inverter chain are shown in Fig. 10. A case where PMOS is charging the output capacitors is shown in Fig. 11. For the delay when the circuit is operating at a near-threshold or subthreshold region, the alpha-power law does not accurately characterize the delay. The Vth for NMOS was 0.25, and Vth for PMOS was 0.8. For PMOS where VDD equals Vth, the delay was predicted to be extremely large because VDD-Vth approaches to zero. Thus, the prediction for the near-threshold region is not accurate for PMOS as shown in Fig. 11.

Fig. 10. TPHL at various VDD

Fig. 11. TPLH at various VDD

The absolute error between the predicted and measured delay is shown in Fig. 12. For near-threshold or a VDD approaching 3V, the percent error is 46.12% and 33.10% respectively. In between those extreme points, the percent error is less than 10%. Thus, the alpha-power law closely characterizes the propagation delay for regions other than those near-threshold or for a large supplies voltage.

Fig. 12. Percent Error between measured and predicted delay

C. Inverter Chain (Various Sizes) To compare the results with different sizes of an inverter chain, a total of five different sizes of an inverter chain were simulated via HSPICE. A supply voltage of 2.4V, 2.5V, and 2.6V were chosen because a minimal percent error was found at these operation regions

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Table 2. Absolute Error for Various Inverter Chain Size and VDD

Size VDD = 2.4 VDD = 2.5 VDD = 2.6

Delay (ns)

Error (%)

Delay (ns)

Error (%)

Delay (ns)

Error (%)

5 1.39 0.21 1.32 3.69 1.25 7.92 10 1.38 3.53 1.31 0.2 1.23 4.01

100 1.24 3.99 1.17 0.07 1.10 4.41 1000 1.03 6.94 0.94 0.06 0.85 8.00

10,000 0.97 23.67 0.72 0.13 0.49 44.68 The error becomes larger as the size of the inverter chain increases as shown in Fig. 13. It was observed that the predicted delay is not accurate for the circuit when the delay was too small or too large. When an output capacitor of 100 fF was used, the delay was too small, such that the dependence on delay according to the alpha-power law was not clearly observed.

Fig. 13. Percent Error for Various Size of Inverter Chain

VI. CONCLUSION AND FUTURE RESEARCH The alpha-power law provides a simple yet practical analytical model for MOSFET. As the size of inverter chain increases, the error of the predicted delay increases. Average error is less than 5% for an above-threshold operation region unless the delay is significantly large or small. When the size of the inverter exceeds 1,000, the error becomes larger and approaches 25%. When the circuit is operating at a near-threshold or subthreshold region, the error is as large as 50%. As the alpha-power law does not accurately characterize the circuit behavior for a subthreshold or near-threshold operation region, further research is needed to characterize propagation delay for a near-threshold region.

ACKNOWLEDGMENTS The author would like to acknowledge Dr. Vishwani

Agrawal for the opportunity to study the alpha-power law with him and his inspiration for its practical application in my honors thesis. His support and outstanding lectures on low-power electronics were key to building my fundamental knowledge in low power electronics and VLSI design.

REFERENCES [1] Sakurai, T., Newton, A.R., "Alpha-Power Law MOSFET Model and its

Application to CMOS Inverter Delay and Other Formulas." IEEE J. Solid-State Circuits, Vol. 25, No. 2, pp. 584-594. 1990.

[2] T. Sakurai, “Alpha-Power Law MOS Model,” IEEE Solid-State Circuits Society Newsletter, Vol. 9, No. 4, pp. 4–5, Oct. 2004.

[3] PTM: Predictive techonology model. In: Nanoscale Integration and Modeling (NIMO) Group. Arizona State University, Arizona.

[4] J. R. Burns, “Switching response of complementary-symmetry MOS transistor logic circuits,” RCA Rev., vol. 25, pp. 627-661, Dec. 1964.

[5] N. Hedenstierna and K. O. Jeppson, “CMOS circuit speed and buffer optimization,” IEEE Trans. Computer-Aided Design, vol. CAD-6, no. 2. Pp. 270-280, Mar. 1987.