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1Bioelectromagnetics Lab
Verilog

1.
2. Verilog
3. Verilog
4. MAX+plus II
5.
6.
7.
8.
9. 10. 11.

1.
Verilog
(Flexibility)
(Portability)
C

2. Verilog
Verilog (model) (switch level) (transistor)
(gate level) (data flow)
(register transfer level) (behavioral)

2.1
// 2-input AND gatemodule and2(in1, in2, out);input in1, in2;output out;
and u1(out, in1, in2);
endmodule

2.2
// 2-input AND gatemodule and2(in1, in2, out);input in1, in2;output out;
assign out = in1 & in2;
endmodule

2.3
Verilog HDL
// 2-input AND gatemodule and2(in1, in2, out);input in1, in2;output out;reg out;
always@(in1 or in2)begin
out = in1 & in2;end
endmodule

3. Verilog
Verilog (module) (assign) (functions) (task)

3.1 // include & define
module module_name(port list);
Port // input, output, inout
// wire, reg,
function task
endmodule

3.2
C Verilog
Verilog

3.3 Verilog
Verilog (token) (whitespace) (comment) (keyword) (identifier) (operator) (number)

3.3 Verilog
Verilog
// (end_of_line)
/* */

3.3 Verilog
always negedge posedgebegin end assign wireinteger function endfunctionmodule endmodulefor if elseinout input outputand buf nand nornot or xnor xor

3.3 Verilog
Verilog (instance)
( _ ) ($)

3.3 Verilog
Binary bit-wise operators: ~, &, |, ^, ~^, ^~ Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~ Logical operators: !, &&, || 2s complement operators: +, -, *, /, % Relational operators: >, =, >,

3.3 Verilog
bit BODH 1B0, 4O7, 8HF, 10D9
bit HDL
h89ab, 128, O377, b1001

4. MAX+plus II MAX+plus II Verilog
Verilog v
Verilog
scf

4. MAX+plus II
MAX+plus II Verilog module Module task IEEE
MAX+plus II Verilog on-line help

5.
Verilog wire wandWired-AND
MAX+plus II worWired-OR
MAX+plus II reg
integer, real,
MAX+plus II integer for

5.1
Verilog (value level) 0
0, Zero, False, Low, Logic Low, Ground, VSS, Negative Assertion
1 1, One, True, High, Logic High, Power, VDD, VCC,
Positive Assertion X
Unknown value Z
High impedance, Floating state, Tri-state, Disable driver

5.2 wire
wire
wire Z
wire a, b, c;
assign c = a & b;

5.3 reg
reg
reg X
reg a, b, c;
always@()c = a & b;

5.4 wire reg
wire assign always (l-value)
reg always

5.5
(vector) wire reg
wire [0:3] in;wire [0:3] out;wire [3:0] a, b;
reg [0:3] c;reg [3:0] d, e;

5.6
wirereginteger 1
MAX+plus II
wire in[0:100];reg out[0:100];

5.7
wire [7:0] a, b, c;
assign c[0] = a[0] & b[0];
wire [7:0] a, b, c;
assign c[3:0] = a[5:2]& b[7:4];
assign c[0:3] = a[3:0]; // X

6.
Verilog (input)
(output)
(inout)

6.1 module and_2_1(in1, in2, out);input in1, in2;output out;
assign out = in1 & in2;endmodule

6.2 module bidir(rw, din, da, iop);input rw, din, da;inout iop;
assign iop = rw ?((din) ? da : iop): 1'bZ;
endmodule
rw
din
da
iop
* MAX+plus II

6.3
Verilog wire
reg

7.
Verilog
and, nand, or, nor, xor, xnor MAX+plus II 12 xorxnor
buf, not
bufif0, bufif1, notif0, notif1

7.1 - 1module test(in, out);input [2:0] in;output out;
and u1(out, in[0], in[1], in[2]);endmodule

7.1 - 2module test(in, out);input [2:0] in;output out;
nor u1(out, in[0], in[1], in[2]);endmodule

7.2 - 1module test(in, out);input in;output [1:0] out;
not u1(out[0], out[1], in);endmodule

7.2 - 2module test(in, out);input in;output [1:0] out;
buf u1(out[0], out[1], in);endmodule

7.3 - 1module test(in, out, en);input in, en;output out;
bufif1 u1(out, in, en);endmodule

7.3 - 2module test(in, out, en);input in, en;output out;
notif0 u1(out, in, en);endmodule

8.
assign wirewandwor tri
assign a = b + a;

8.1
X = AC D + B C + B D + C DY = A + B + C
module boolean(a, b, c, d, x, y);input a, b, c, d;output x, y;
assign x = (a & c & (!d))| (b & (!c)) | (b & d) | (c & d);
assign y = (!a) | b | c;endmodule

8.2
Binary bit-wise operators ~NOT &AND |OR ^XOR ~^, ^~XNOR
module test(in1, in2, out);input in1, in2;output [0:4] out;
assign out[0] = ~in1;assign out[1] = in1 & in2;assign out[2] = in1 | in2;assign out[3] = in1 ^ in2;assign out[4] = in1 ~^ in2;
endmodule

8.2
Unary reduction operators &AND ~&NAND |OR ~|NOR ^XOR ~^, ^~XNOR
module test(in, out);input [0:3] in;output [0:5] out;
assign out[0] = &in;assign out[1] = ~&in;assign out[2] = | in;assign out[3] = ~| in;assign out[4] = ^ in;assign out[5] = ~^ in;
endmodule

8.2
Logical operators !NOT &&AND ||OR module test(in1, in2, out);
input in1, in2;output [0:2] out;
assign out[0] = ! in1;assign out[1] = in1 && in2;assign out[2] = in1 || in2;
endmodule

8.2
2's complement arithmetic +Add -Subtract *Multiply /Divide %Module
module test(i1, i2, o1, o2, o3);input i1, i2;output [0:1] o1, o2, o3;
assign o1 = i1 + i2;assign o2 = i1 - i2;assign o3 = i1 * i2;
endmodule

8.2
Relational operators > < >= b);assign eq = (a == b);assign le = (a < b);
endmodule

8.2
Logical shift operators >> 1;
endmodule
* MAX+plus II

8.2
Conditional operator ?:
module test(a, b, sel, out);input a, b, sel;output out;
assign out = sel ? a : b;endmodule

8.2
Duplication operator {{}}
Concatenation operator {}
module test(in, out1, out2);input [0:7] in;output [0:7] out1, out2;
assign out1 = {2{4'b1100}} + in;assign out2 = {{3{2'b10}}, 2'b00} + in;
endmodule

9.
Verilog (event-based timing control)

9.1 always
always
always
statement
alwaysbegin
statementsend
always@(event_expression)statement
always@(event_expression)begin
statementsend

9.1 always@
always@() (event expression)
(level trigger)
or (level trigger)
posedge negedge

9.1 always@
module test(in, out);input in;output out;reg out;
always@(in)out = ~ in;
endmodule

9.1 always@
module test(a, b, out);input a, b;output out;reg out;
always@(a or b)begin
out = a | b;end
endmodule

9.1 always@
posedge
module test(a, ck, out);input a, ck;output out;reg out;
always@(posedge ck)begin
out = ~ a;end
endmodule

9.1 always@
negedge
module test(a, ck, out);input a, ck;output out;reg out;
always@(negedge ck)begin
out = ~ a;end
endmodule

9.2 if
if
if (expression)statement
if (expression)begin
statementsend

9.2 if module test(reset, in, out);input reset, in;output out;reg out;
alwaysbegin
if (reset == 1b1) // out = 0;
if (reset == 1b0) // out

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