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  • Verilog through designing real circuits. 3 - Verilog... · 1 This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware
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1 This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital electronics. Therefore, I will NOT be going through Verilog as in a programming course - it would have been extremely boring for both you and me if I did. Instead, you will learn about Verilog through examples. I will then point out various language features along the way. What it means is that the treatment of Verilog is NOT going to be systematic – there will be lots of features you won’t know about Verilog. However, you will learn enough to specify reasonably sophisticated digital circuits, and you should gain enough confidence to learn the rest by yourself. There are many useful online resources available on the details of Verilog syntax etc.. Look it up as you need to and you will learn how to design digital circuit using Verilog through designing real circuits. The problem sheets are mostly about circuits and concepts, with occasional Verilog exercises. You will be doing lots of Verilog coding during the four weeks of Lab Experiment in the second half of the term.

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Page 1: Verilog through designing real circuits. 3 - Verilog... · 1 This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware

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ThisandthenextlecturesareaboutVerilogHDL,which,togetherwithanotherlanguageVHDL,arethemostpopularhardwarelanguagesusedinindustry.

Verilogisonlyatool;thiscourseisaboutdigitalelectronics.Therefore,IwillNOTbegoingthroughVerilogasinaprogrammingcourse- itwouldhavebeenextremelyboringforbothyouandmeifIdid.Instead,youwilllearnaboutVerilogthroughexamples.Iwillthenpointoutvariouslanguagefeaturesalongtheway.WhatitmeansisthatthetreatmentofVerilogisNOTgoingtobesystematic– therewillbelotsoffeaturesyouwon’tknowaboutVerilog.However,youwilllearnenoughtospecifyreasonablysophisticateddigitalcircuits,andyoushouldgainenoughconfidencetolearntherestbyyourself.

TherearemanyusefulonlineresourcesavailableonthedetailsofVerilogsyntaxetc..LookitupasyouneedtoandyouwilllearnhowtodesigndigitalcircuitusingVerilogthroughdesigningrealcircuits.

Theproblemsheetsaremostlyaboutcircuitsandconcepts,withoccasionalVerilogexercises.YouwillbedoinglotsofVerilogcodingduringthefourweeksofLabExperimentinthesecondhalfoftheterm.

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Hereisalistoflectureobjectives.Theyareprovidedforyoutoreflectonwhatyouaresupposedtolearn,ratherthananintroductiontothislecture.Iwant,bytheendofthislecture,togiveyousomeideaaboutthebasicstructure andsyntax ofVerilog.IwanttoconvinceyouthatschematiccaptureisNOTagoodwaytodesigndigitalcircuits.Finally,IwantyoutoappreciatehowtouseVerilogtospecifyapieceofhardwareatdifferentlevelsofabstraction.

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Youareveryfamiliarwithschematiccapture.HowevermoderndigitaldesignmethodsingeneralDONOTuseschematics.Insteadanengineerwouldspecifythedesignrequirementorthealgorithmtobeimplementedinsomeformofcomputerlanguagespeciallydesignedtodescribehardware.Thesearecalled“HardwareDescriptionLanguages” (HDLs).

ThemostimportantadvantagesofHDLasameansofspecifyingyourdigitaldesignare:1)Youcanmakethedesigntakeonparameters(suchasnumberofbitsinanadder);2)itismucheasiertousecompilationandsynthesistoolswithatextfilethanwithschematic;3)itisverydifficulttoexpressanalgorithmindiagramform,butitisveryeasywithacomputerlanguage;4)youcanusevariousdatapathoperatorssuchas+,*etc.;5)youcaneasilyedit,storeandtransmitatextfile,andmuchhardwarewithaschematicdiagram.

Fordigitaldesigns,schematicisNOTanoption.AlwaysuseHDL.Inthislecture,Iwilldemonstratetoyouwhywithanexample.

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IhavechosentouseVerilogHDLasthehardwaredescriptionlanguageforthismodule.VerilogisverysimilartotheClanguage,whichyoushouldalreadyknowfromlastyear.However,youmustalwaysrememberthatYOUAREUSINGITTODESCRIBEHARDWAREANDNOTASACOMPUTERPROGRAMME.

YoucanuseVerilogtodescribeyourdigitalhardwareinthreedifferentlevelofabstraction:1) BehaviouralLevel – youonlydescribehowthehardwareshouldbehavewithoutANYreferencetodigitalhardware.2) Register-Transfer-Level(RTL)– Herethedescriptionassumestheexistenceofregistersandtheseareclockedbyaclocksignal.Thereforedigitaldataistransferredfromoneregistertothenextonsuccessiveclockcycles.Timing(intermsofclockcycles)isthereforeexplicitlydefinedintheVerilogcode.Thisisthelevelofdesignweusemostfrequentlyinthiscourse.3) GateLevel– thisisthelowestleveldescriptionwhereeachgateanditsinterconnectionareexplicitlyspecified.VerilogisnotonlyaspecificationlanguagewhichtellstheCADsystemwhathardwareissupposetodo,italsoincludesacompletesimulationenvironment.AVerilogcompilerdoesmorethanmappingyourcodetohardware,italsocansimulate (orexecute)yourdesigntopredictthebehaviourofyourcircuit.Itisthepredominantlanguageusedforchipdesign.YouwilllearnVerilogthroughexamplesandexercises,notthroughlecture.However,IwillspendjusttwolecturestocoverthebasicsofVerilog.

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ThisisaVerilogmodulethatspecifiesa2-to-1multiplexer.ItisrathersimilartoaCfunction(exceptforthemodule keyword).

ItisimportanttorememberthebasicstructureofaVerilogmodule.Thereisamodulename:mux2to1.Thereisalistofinterfaceports:3inputsa,b andsel,and2outputsout andoutbar.Alwaysusemeaningfulnamesforbothmodulenameandvariablenames.

Youmustspecifywhichportisinputandwhichportisoutput,similartothedatatypedeclarationinaCprogramme.

Finally,the2-to-1multiplexingfunctionisspecifiedintheassign statementwithaconstructthatisfoundinC.Thisisabehaviouraldescriptionofthemultiplexer– nogatesareinvolved.

Thelaststatementspecifiestherelationshipbetweenout andoutbar.ItisimportanttorememberthatVerilogdescribesHARDWAREnotinstructioncode.Thetwoassign statementsspecifyhardwarethat“execute” orperformthetwohardwarefunctionsinparallel.Thereforetheirorderdoesnotmatter.

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Continuousassignmentspecifiescombinationalcircuits– outputiscontinuouslyreflectingtheoperationsappliedtotheinput,justlikehardware.Rememberthatunlikeaprogramminglanguage,thetwocontinuousassignmentstatementshereAREspecifyinghardwareinPARALLEL,notinseries.HerewealsoseetheconditionalstatementthatisfoundinC.Thismapsperfectlytothefunctionofa2-to-1multiplexerinhardwareandiswidelyusedinVerilog.Furthermore,therearemanyotherBooleanandarithmeticoperatorsdefinedinVerilog(asinC).HereisaquicksummaryofalltheVerilogoperators(usedinanexpression).(Whatis“reductionand&”?Iwantyoutofindthisyourselfonline.)

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WhilethepreviousVerilogcodeforthe2-to-1muxonlyspecifies“behaviour”,hereisonethatspecifiesagateimplementationofthesamecircuit.Threetypesofgatesareused:and,or andnot gates.Thereareinternalnets(declaredaswire)whichmustalsobedeclaredandareusedtoconnectgatestogether.

Keywordssuchasand,or andxor arespecial– theyspecifyactuallogicgates.Theyarealsospecialinthatthenumberofinputstotheand-gatecanbe2,3,4,…..Anylength!

NotethatthismoduleusesTWOANDgates,andtheyhavedifferentnames:a1anda2.TheseareTWOseparate instances oftheANDgate.Insoftware,“calling” afunctionsimpleexecutethesamepieceofprogrammecode.Herethetwostatements”anda1(out1,…” and“anda2(out2…” producetwoseparatepieceofhardware.Wesaythateachlineis“instantiating” anANDgate.

Wiringupthegatesisthroughtheuseofportsandwires,anddependsonthepositionsofthese“nets”.Forexample,out1 istheoutputnetoftheANDgatea1,anditisconnectedtotheinputoftheOR gateitbyvirtualofitslocationinthegateportlist.

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SofarwehaveusedVeriloginveryhardwarespecificway.“assign” andusinggatespecificationarespecialtoVerilog.YoudonotfindtheseinC.

HereissomethingthatismorelikeC– anditiscalled“proceduralassignment”.Typicallyweusesomethingcalled“always” blocktospecifya“procedure”,i.e.acollectionofsequentialstatementswhicharesandwichedbetweenthebegin-endconstruct.

Thealways blockneedsasensitivitylist– alistofsignalswhich,ifANYofthesesignalschanges,thealways blockwillbeinvoked.Youmayreadthisblockas:

“alwaysatanychangesinnetsa,b orsel,dothebitsbetweenbeginand end”.Actually,ifyouaredefiningacombinationalcircuitmodule,anevenbetterwaytodefinethealwaysblockistouse:

…..always@*....//alwaysatanychangewithanyinputsignal

Insidethebegin-endblock,youareallowedtouseC-likestatements.Inthiscase,weusetheif-elsestatement.Allstatementsinsidethebegin-endblockareexecuted sequentially.

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NotethatVerilogkeywordreg doesnotimpliesthatthereisaregistercreatedinthehardware.Itismuchmorelikedeclaringavariablethatholdsavalue.ItisaruleinVerilogthatifyouperformanassignmenttoavariableINSIDEanalwaysblock,thatvariableMUSTbedeclaredreg,andNOTanet(wire).ThisisoneofthefewpeculiaritiesofVerilogthatcanbeconfusingtostudents.

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ThisslideshowshowtheproceduralstatementismappedtothebasicMUXcircuit.ThecontinuousassignmentstatementcorrespondstotheNOTgate.

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ThisisyetanotherwaytospecifytheMUXcircuit.Itisstillaproceduralassignmentwiththealways block.However,wereplacetheif-elsestatementwitha“case”statement.Thecasevariableissel.Sincesel isa1-bitsignal(ornet),itcanonlytakeon0or1.

Notethatthevariouscasevaluescanbeexpressedindifferentnumberformatsasshownintheslide.Forexample,consider2’b10.The2isthenumberofbitsinthisnumber.‘bmeansitisspecifiedinbinaryformat.Thevalueofthisnumberis10 inbinary.

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Thisslidedemonstrateswhylanguagespecificationofhardwareissomuchbetterthanschematicdiagram.Bysimplydeclaringthesignalsasamulti-bitbus(8bits[7:0]),wechangethismoduletoonethatspecifies8separate2-to-1multiplexers.

Anotherusefulwaytospecifyabusisusingtheconcatenationoperator:{….}asshownabove.

Theconcatenationoperatorisparticularlyusefulinconvertingdigitalsignalsfromonewordlength(i.e.numberofbitsinaword)toanother.Forexample,toconvertan8-bitunsignednumbera[7:0]toa13-bitunsignednumberb[12:0],youcansimpledothis:

assign b[12:0] = {5’b0, a[7:0]};

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Hereisasimpleexample:thedesign ofa4-bithexcodeto7segmentdecoder.Youcanexpressthefunctionofthis7-segmentdecoderinthreeforms:1)asatruthtable(notethatthesegmentsarelowactive);2)as7separateK-maps(shownhereisforout[6] segmentonly);3)asBooleanequations.ThisisprobablythelasttimeyouseeK-maps.Inpracticaldigitaldesign,youwouldrelyheavilyonCADtools.Inwhichcase,logicsimplificationsaredoneforyouautomatically– youneverneedtouseK-mapstodoBooleansimplificationmanually!

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Hereisatediousimplementationintheformofschematicdiagramofthe7segmentdecoderasinterconnectedgates.Veryhardtodoandverypronetoerrors.

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OnecouldtakeagroupofgatesandspecifythegatesinVeriloggateprimitivessuchasand,or etc.Stillverytedious.Hereistheimplementationfortheout[6] output.

Page 16: Verilog through designing real circuits. 3 - Verilog... · 1 This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware

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Insteadofspecifyingeachgateseparately,hereisusingcontinuousassignmentstatement,mappingtheBooleanequationdirectiontoasingleVerilogstatement.Thisisbetter.

Page 17: Verilog through designing real circuits. 3 - Verilog... · 1 This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware

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Hereisthecompletespecificationofthehex_to_7segmoduleusingcontinuousassignment statements.ItshowshowoneshouldwriteVerilogcodewithgoodcommentsandcleardocumentationofinputandoutputports.

Page 18: Verilog through designing real circuits. 3 - Verilog... · 1 This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware

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Finallythe4th methodisthebest.Weusethecase constructtospecifythebehaviourofthedecoder.Hereonedirectlymapsthetruthtabletothecasestatement – easyandelegant.

Insteadofusing:always@(in),youcouldalsousealways@*

Page 19: Verilog through designing real circuits. 3 - Verilog... · 1 This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware

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HowisaVerilogdescriptionofahardwaremoduleturnedintoFPGAconfiguration?ThisflowdiagramshowsthevariousstepstakeninsidetheQuartusPrimeCADsystem.

Page 20: Verilog through designing real circuits. 3 - Verilog... · 1 This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware

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