vhdl assignment 1 (batch 11)
DESCRIPTION
A few VHDL programs in ModelsimTRANSCRIPT
8/30/2013 ASSIGNMENT 1BATCH 11
RAJITH MROSHAN RAJUVL500
1. Design and simulate a 4 input NOR Gate program using dataflow modeling in VHDL.
--4 input nand
library ieee;
use ieee.std_logic_1164.all;
entity nand4input is
port (
a,b,c,d: in std_logic;
y: out std_logic);
end nand4input;
architecture dataflow of nand4input is
begin
y <= not(a and b and c and d);
end dataflow;
SIMULATION SNAPSHOTS :
2. Design and simulate a 4 input NAND Gate program using dataflow modeling in VHDL.
--4 input nand
library ieee;
use ieee.std_logic_1164.all;
entity nand4input is
port (
a,b,c,d: in std_logic;
y: out std_logic);
end nand4input;
architecture dataflow of nand4input is
begin
y <= not(a and b and c and d);
end dataflow;
SIMULATION SNAPSHOTS :
3. Design and simulate a 3 input AND Gate program using dataflow modeling in VHDL.
--3 input and
library ieee;
use ieee.std_logic_1164.all;
entity and3input is
port (
a,b,c: in std_logic;
y: out std_logic);
end and3input;
architecture dataflow of and3input is
begin
y <= a and b and
c; end dataflow;
SIMULATION SNAPSHOTS :
4. Design and simulate a 3 input XOR Gate program using dataflow modeling in VHDL.
--3 INPUT XOR
library ieee;
use ieee.std_logic_1164.all;
entity xor3in is
port(
a,b,c : in std_logic;
y : out std_logic);
end xor3in;
architecture dataflow of xor3in is
begin
y <= a xor b xor
c; end dataflow;
SIMULATION SNAPSHOTS :
5. Design and simulate a 2 input EX-NOR Gate program using dataflow modeling in VHDL.
--3 input xnor
library ieee;
use ieee.std_logic_1164.all;
entity xnor2in is
port (
a,b: in std_logic;
c: out std_logic);
end xnor2in;
architecture dataflow of xnor2in is
begin
c<=a xnor b;
end dataflow;
SIMULATION SNAPSHOTS :
6. Design and simulate a 3 input OR Gate program using dataflow modeling in VHDL.
--3 input or
library ieee;
use ieee.std_logic_1164.all;
entity or3input is
port (
a,b,c: in std_logic;
y: out std_logic);
end or3input;
architecture dataflow of or3input
is begin
y <= a or b or
c; end dataflow;
SIMULATION SNAPSHOTS :
7. Design and simulate a 3 input NAND Gate program using dataflow modeling in VHDL.
--3 input nand
library ieee;
use ieee.std_logic_1164.all;
entity nand3input is
port (
a,b,c: in std_logic;
y: out std_logic);
end nand3input;
architecture dataflow of nand3input is
begin
y <= (a nand b) nand
c; end dataflow;
SIMULATION SNAPSHOTS :
8. Design and simulate a 3 input NOR Gate program using dataflow modeling in VHDL.
--3 input nor
library ieee;
use ieee.std_logic_1164.all;
entity nor3input is
port (
a,b,c: in std_logic;
y: out std_logic);
end nor3input;
architecture dataflow of nor3input
is begin
y <= a nor (b nor
c) ; end dataflow;
SIMULATION SNAPSHOTS :
9. Design and simulate a half adder in VHDL using dataflow-modeling style.
library ieee;
use ieee.std_logic_1164.all;
entity hadder is
port (
a,b: in std_logic;
s,co: out std_logic);
end hadder;
architecture dataflow of hadder
is begin
s <= a xor b;
co <= a and b;
end dataflow;
SIMULATION SNAPSHOTS :
10. Design and simulate a full adder in VHDL using dataflow-modeling style.
-- Full Adder
library ieee;
use ieee.std_logic_1164.all;
entity fadder is
port (
a,b,ci: in std_logic;
s,co: out std_logic);
end fadder;
architecture dataflow of fadder
is begin
s <= a xor b xor ci;
co <= (a and b) or (b and ci) or (a and
ci); end dataflow;
SIMULATION
SNAPSHOTS :
11. Design and simulate a 2-1 Mux in VHDL using dataflow-modeling style.
-- 2 to 1 mux
entity mux2to1 is
port (
a,b,s: in bit; c:
out bit); end
mux2to1;
architecture dataflow of mux2to1
is begin
c<= (not s and a) or (s and b);
end dataflow;
SIMULATION
SNAPSHOTS :
12. Design and simulate a 4-1 Mux in VHDL using dataflow-modeling style.
-- 4 to 1 mux
entity mux4to1 is
port (
a,b,c,d,s0,s1: in bit;
y: out bit);
end mux4to1;
architecture dataflow of mux4to1
is begin
y <= (not s0 and not s1 and a) or ( not s0 and s1 and b) or (s0 and not s1 and c) or (s0 and s1 and d);
end dataflow;
SIMULATION SNAPSHOTS :
13. Design and simulate an 8-1 Mux in VHDL using dataflow-modeling style.
-- 8 to 1 mux
entity mux8to1 is
port (
a,b,c,d,e,f,g,h,s0,s1,s2: in bit;
y: out bit);
end mux8to1;
architecture dataflow of mux8to1 is
begin
y <= (not s0 and not s1 and not s2 and a) or ( not s0 and not s1 and s2 and b) or ( not s0 and s1 and not s2 and c) or ( not s0 and s1 and s2 and d) or ( s0 and not s1 and not s2 and e) or ( s0 and not s1 and s2 and f) or (s0 and s1 and not s2 and g) or (s0 and s1 and s2 and h);
end dataflow;
SIMULATION SNAPSHOTS :
14. Design and simulate a 16-1 Mux in VHDL using dataflow-modeling style.
-- 16 to 1 mux
entity mux16to1 is
port (
a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,s0,s1,s2,s3: in bit;
y: out bit);
end mux16to1;
architecture dataflow of mux16to1 is
begin
y <= (not s0 and not s1 and not s2 and not s3 and a) or ( not s0 and not s1 and not s2 and s3 and b) or ( not s0 and not s1 and s2 and not s3 and c) or ( not s0 and not s1 and s2 and s3 and d) or ( not s0 and s1 and not s2 and not s3 and e) or (not s0 and s1 and not s2 and s3 and f) or ( not s0 and s1 and s2 and not s3 and g) or ( not s0 and s1 and s2 and s3 and h)or( s0 and not s1 and not s2 and not s3 and i) or ( s0 and not s1 and not s2 and not s3 and j) or ( s0 and not s1 and not s2 and s3 and k) or ( s0 and not s1 and not s2 and s3 and l) or ( s0 and not s1 and s2 and not s3 and m) or (s0 and not s1 and s2 and not s3 and n) or ( s0 and not s1 and s2 and s3 and
o) or (s0 and not s1 and s2 and s3 and p);
end dataflow;
SIMULATION SNAPSHOTS :
15. Design and simulate a 1 to 2 De- Mux in VHDL using dataflow modeling style.
-- 1 to 2 demux
entity demux1to2 is
port (
a,s: in bit;
y0,y1: out bit);
end demux1to2;
architecture dataflow of demux1to2 is
begin
y0<= a and not s;
y1<= a and s;
end dataflow;
SIMULATION SNAPSHOTS :
16. Design and simulate a 2-to-4-line decoder/demultiplexer in VHDL using dataflowmodelingstyle.
-- 2 to 4 decoder
entity decoder2to4 is
port (
x,y: in bit;
a,b,c,d: out bit);
end decoder2to4;
architecture dataflow of decoder2to4 is
begin
a<= not x and not y;
b<= not x and y;
c<= x and not y;
d<= x and y;
end dataflow;
SIMULATION SNAPSHOTS :
17. Design and simulate a 3-to-8-line decoder/demultiplexer in VHDL using dataflowmodelingstyle.-- 3 to 8 decoder
entity decoder3to8 is
port (
x,y,z: in bit;
y0,y1,y2,y3,y4,y5,y6,y7: out bit);
end decoder3to8;
architecture dataflow of decoder3to8 is
begin
y0<= not x and not y and not z;
y1<= not x and not y and z;
y2<= not x and y and not z;
y3<= not x and y and z;
y4<= x and not y and not z;
y5<= x and not y and z;
y6<= x and y and not z;
y7<= x and y and z;
end dataflow;
SIMULATION SNAPSHOTS :
19. Realize a circuit for the following function in VHDL using data flow modeling. F1= _m (0, 3, 5, 6, 9, 10, 12, 15)
--Q:19 k map
library ieee;
use ieee.std_logic_1164.all;
entity q19kmap is
port (
a,b,c,d: in std_logic;
y: out std_logic);
end q19kmap;
architecture dataflow of q19kmap is
begin
y <= (not a and not b and not c and not d )or(not a and not b and c and d)or(not a and b and not c and d)or (not a and b and c and not d)or(a and not b and not c and d)or(a and not b and c and not d)or(a and b and not c and not d)or(a and b and c and d) ;
end dataflow;
SIMULATION SNAPSHOTS :
20. Design a circuit with two outputs has to implement the following functions. F(A,B,C,D)= _m (0, 2,4,6,7,9)+D(10,11)G (A,B,C,D)= _m (2,4,9,10,15)+D(0,13,14)
--Q:20 k map
library ieee;
use ieee.std_logic_1164.all;
entity q20kmap is
port (
a,b,c,d: in std_logic;
f,g: out std_logic);
end q20kmap;
architecture dataflow of q20kmap
is begin
f <= (not a and not d)or( not a and b and c )or(a and not b and d);
g <= (not a and not b and not d) or(not a and not c and not d)or (a and not c and d)or(a and b and d)or (a and c and not d);
end dataflow;
SIMULATION SNAPSHOTS :
21. Design and simulate a half -Subtractor in VHDL using dataflow-modeling style.
-- Half Subtractor
library ieee;
use ieee.std_logic_1164.all;
entity hsub is
port (
a,b: in std_logic;
diff,bo: out std_logic);
end hsub;
architecture dataflow of hsub
is begin
diff <= a xor b;
bo <=(not a) and b;
end dataflow;
SIMULATION SNAPSHOTS :
22. Design and simulate a Full -Subtractor in VHDL using dataflow-modeling style.
--Full Subtractor
library ieee;
use ieee.std_logic_1164.all;
entity fsub is
port (
a,b,bi: in std_logic;
d,bo: out std_logic);
end fsub;
architecture dataflow of fsub
is begin
d <= a xor b xor bi;
bo <= ( not a and b) or (b and bi) or (not a and bi);
end dataflow;
SIMULATION SNAPSHOTS :
23. Design a BCD to 7-Segment Decoder in VHDL using dataflow-modeling style.
library ieee;use ieee.std_logic_1164.all;entity bcdto7seg isport( w,x,y,z : in std_logic;a,b,c,d,e,f,g : out std_logic);end bcdto7seg;architecture dataflow of bcdto7seg isbegina <= ((not x) and (not z))or(x and z ) or ( y and z) or w;b <= (not x) or ((not y) and ( not z)) or (y and z);c <= x or (not y) or (not z);d <= ((not x) and (not z)) or (y and (not z)) or ((not x) and y) or (x and (not y) and z);e <= ((not x) and (not z)) or (y and (not z));f <= w or ((not y) and ( not z)) or (x and (not y)) or (x and (not z));g <= w or (x and ( not y)) or ((not x) and y) or (y and (not z));end dataflow;
SIMULATION SNAPSHOTS :
24. Realize a circuit for the following function in VHDL using data flow modeling. F1= _m (0, 3, 5, 6, 9, 10, 12, 15)+ D (2,14)
--Q:24 k map
library ieee;
use ieee.std_logic_1164.all;
entity q24kmap is
port (
a,b,c,d: in std_logic;
y: out std_logic);
end q24kmap;
architecture dataflow of q24kmap is
begin
y <= ( c and not d )or(not a and not b and c )or( a and b and c )or (not a and not b and not d)or( not a and b and not c and d)or(a and b and not c and not d)or(a and not b and not c and d);
end dataflow;
SIMULATION SNAPSHOTS :
25. Realize a circuit for the following function in VHDL using data flow modeling. F1= _m (0, 1, 2, 3, 11, 12, 14, 15)
--Q:25 k map
library ieee;
use ieee.std_logic_1164.all;
entity q25kmap is
port (
a,b,c,d: in std_logic;
y: out std_logic);
end q25kmap;
architecture dataflow of q25kmap
is begin
y <= (not a and not b)or( a and b and c )or(a and c and d)or ( a and b and not d);
end dataflow;
SIMULATION SNAPSHOTS :
26. Realize a BCD to Excess 3 code converter using minimum number of NAND gates in VHDL using Dataflow Modeling.
--Q:BCD TO EXCESS 3
CONVERTER library ieee;
use ieee.std_logic_1164.all;
entity bcdtoexcessthree is
port (
a,b,c,d: in std_logic;
w,x,y,z: out std_logic);
end bcdtoexcessthree;
architecture dataflow of bcdtoexcessthree
is begin
w<= not ((a nand a) and(b nand d) and (b nand c));
x<= not (((b nand b) nand d ) and ((b nand b) nand c) and not( b and not c and not
d)); y<= not((not c nand not d) and (c nand d));
z<= d nand d;
end dataflow;
SIMULATION SNAPSHOTS :
27. Realize a Excess 3 to BCD code converter using minimum number of NAND gates in VHDL using Dataflow Modeling.
--Q:EXCESS 3 TO BCD CONVERTER
library ieee;
use ieee.std_logic_1164.all;
entity excessthreetobcd is
port (
w,x,y,z: in std_logic;
a,b,c,d: out std_logic);
end excessthreetobcd;
architecture dataflow of excessthreetobcd
is begin
a<= not ((w nand x)and not(w and y and z));
b<= not ((not z nand not x)and (not y nand not x) and not( x and y and z)) ;
c<= not ((not y nand z) and (y nand not z));
d<= z nand z;
end dataflow;
SIMULATION SNAPSHOTS :
28. Realize a 2-bit Comparator using gates in VHDL in Dataflow.
--Q 28: 2 bit comparator
entity comp2bit is port(a,b,c,d: in bit; AgrtB,AeqB,AlesB:out bit);
end comp2bit;architecture dataflow of comp2bit is beginAgrtB<=((a and not b) or (b and not c and not d) or (a and b and not d)); AeqB<=((not a and not b and not c and not d) or
(not a and b and not c and not d) or (a and b and c and d) or(a and not b and c and not d));
AlesB<=((a and c) or (not a and not b and d) or (a and c and d)); end dataflow;
SIMULATION
SNAPSHOTS :
29. Realize a 4-bit Comparator using gates in VHDL using Dataflow.
--Q 29: 4 bit comparatorlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity comp4bit is port( a,b: in std_logic_vector(3 downto 0); AgrtB,AeqB,AlesB :out bit);end comp4bit; architecture dataflow of comp4bit is begin AgrtB <= '1' when a > b else '0'; AlesB <= '1' when a < b else '0'; AeqB <= '1'when a=b else '0'; end dataflow;
SIMULATION SNAPSHOTS
30. Realize a 4 to 1 Mux using WITH SELECT Statement in VHDL.
-- 4 to 1 mux using with
select entity mux4to1with is
port (
a,b,c,d: in bit;
s: in bit_vector(1 downto 0);
y: out bit);
end mux4to1with;
architecture dataflow of mux4to1with is
begin
with s select
y <= a when "00" , b when "01", c when "10", d when others;
end dataflow;
SIMULATION SNAPSHOTS
31. Realize a 4- to 1 Mux using WHEN -ELSE Statement in VHDL.
-- 4 to 1 mux using when
else entity mux4to1when is
port (
a,b,c,d: in bit;
s: in bit_vector(1 downto 0);
y: out bit);
end mux4to1when;
architecture dataflow of mux4to1when
is begin
y <= a when (s="00") else b when (s="01") else c when (s="10") else d ;
end dataflow;
SIMULATION SNAPSHOTS
32) 32. Realize a BCD to 7 Segment Converter using WITH SELECT Statement in VHDL.
-- BCD TO 7 SEGMENT CONVERTER USING WITH SELECT
entity bcdto7segmentwith is
port (
a : in bit_vector(3 downto 0);
y: out bit_vector(6 downto 0));
end bcdto7segmentwith;
architecture dataflow of bcdto7segmentwith is
begin
with a select
y <= "1111110" when "0000", "0110000" when "0001" , "1101101" when "0010", "1111001" when "0011" ,"0010011" when "0100", "1011011" when "0101", "1001111" when "0110", "1110000" when "0111","1111111" when "1000","1111011" when "1001","0000000" when others ;
end dataflow;
SIMULATION SNAPSHOTS
33. Realize a BCD to 7 Segment Converter using WHEN -ELSE Statement in VHDL.
-- -- BCD TO 7 SEGMENT CONVERTER USING WHEN ELSEentity bcdto7segmentwhen is port ( s: in bit_vector(3 downto 0); y: out bit_vector(6 downto 0)); end bcdto7segmentwhen; architecture dataflow of bcdto7segmentwhen is begin y <= "1111110" when (s="0000") else "0110000" when (s="0001") else "1101101" when (s="0010") else "1111001" when (s="0011") else "0010011" when (s="0100") else "1011011" when (s="0101") else "1001111" when (s="0110") else "1110000" when( s="0111") else "1111111" when (s="1000") else "1111011" when(s="1001") else "0000000"; end dataflow;
SIMULATION SNAPSHOT:-
35) Realize a Delay Flip flop in VHDL using Dataflow Modeling.
--D flip floplibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;
entity dflipflop is port ( d,clk: in std_logic; q: inout std_logic; qbar: inout std_logic ); end dflipflop; architecture dataflow of dflipflop is signal s,r : std_logic ; begin s<= d nand clk; r<= not d nand clk; q<= s nand qbar; qbar<= r nand q; end dataflow;
SIMULATION SNAPSHOTS
36. Realize a Priority Encoder using Dataflow in VHDL.
-- Priority Encoder
entity priencoder is
port (
D0,D1,D2,D3: in
bit; X,Y,Z: out bit);
end priencoder;
architecture dataflow of priencoder is
begin
X<=D3 or D2;
Y<=(D1 and not D2) or
D3; Z<=D1 or D0 or D3 or
D2; end dataflow;
SIMULATION:
38. Design and implement in VHDL a Four variable majority function.
--4 variable majority functionlibrary ieee;use ieee.std_logic_1164.all;entity major_fn is port(a,b,c,d:in std_logic; y:out std_logic); end major_fn; architecture dataflow of major_fn is begin y <= (a and b and d) or (a and b and c) or
(b and c and d)or (a and c and d); end dataflow; SIMULATION:
39. Design and Realize the below problem in VHDL.
-- Q 39 TRAFFIC
LIGHT library ieee;
use ieee.std_logic_1164.all;
entity trafficsmall is
port (
a,b: in std_logic;
r,y,g: out std_logic);
end trafficsmall;
architecture dataflow of trafficsmall is
begin
r<= a nor a;
y<= b;
g<= not a nor b;
end dataflow;
SIMULATION
SNAPSHOTS
18. Design and simulate a Master Slave J-K Flip Flop in VHDL using dataflow-modeling style.
34. Realize a Toggle Flip Flop in VHDL using Dataflow Modeling. 37. Realize a 4-bit binary Full adder with fast carry