VHDL Operators

• Logical operators• Relational operators• Shift operators• Assignment operators• Addition operators• Multiplication operators• Miscellaneous operators

Arithmetic Operators

2

Logical Operators• Can be applied on BIT and BOOLEAN (TRUE = 1, FALSE = 0) data-type.

• And, or, nand, nor, xor, xnor -- have their usual meanings.

• XNOR in VHDL’93 only!!

• There is NO order of precedence, so parentheses must be used to force desired order

of operation execution.

Relational Operators

Used in conditional statements= equal to/= not equal to< less than<= less then or equal to> greater than>= greater than or equal to

Shift Operatorssll shift left logic (fill value is ‘0’)srl shift right logic (fill value is ‘0’)Sla shift left arithmetic (fill value is right-hand bit)sra shift right arithmetic (fill value is left-hand bit)Rol rotate left Ror rotate right

all operators have two operands: left operand must be a bit_vector to shift/rotate right operand must be a integer for no. of shifts/rotates-Ve integer same as opposite operator with +ve integer

examples:“1100” sll 1 yields “1000”“1100” srl 2 yields “0011”“1100” sla 1 yields “1000”“1100” sra 2 yields “1111”“1100” rol 1 yields “1001”“1100” ror 2 yields “0011”“1100” ror –1 same as “1100” rol 1

Shift functions: std_logic_arith

• signed and unsigned Shift left logical 4 bit •sll 4

msb lsb 0 0 0 0

Shift operators: built-in type

• Shift left arithemetic 4 bit (a sla 4):

msb lsb

Unsigned Shift right functions

• unsigned shift right logical 4 bit srl 4

msb lsb0 0 0 0

Singed Shift Right Functions

• signed shift right 4 bit ( shr(a,4) = a sra 4):

msb lsb

10

Example on shift and rotate

A <= “10010101”;• A sll 2 • A srl 3 • A sla 3 • A sra 2 • A rol 3• A ror 5

<= Used to assign a value to a SIGNAL.

:= Used to assign a value to a VARIABLE, CONSTANT, or GENERIC. Used also for

assigning initial values.

=> Used to assign values to individual vector elements or with OTHERS.

Assignment Operators

Example: Consider the following signal and variable declarations:

SIGNAL x : STD_LOGIC;VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);

Then the following assignments are legal:

x<= '1'; y:= "0000“;w<= "10000000“;w<=(0 =>'1', OTHERS =>'0');

Adding Operators+ addition- subtraction& concatenation

example:signal A: bit_vector(5 downto 0);signal B,C: bit_vector(2 downto 0);B <= ‘0’ & ‘1’ & ‘0’;C <= ‘1’ & ‘1’ & ‘0’;A <= B & C; -- A now has “010110”

Multiplying Operators

* Multiplication/ DivisionMod ModulusRem Remainder

rem has sign of 1st operand (A) and absolute value less than the value of B. It is defined as: A rem B = A – (A/B) * B -- (in which A/B in an integer)

mod has sign of 2nd operand (B) and absolute value less than the value of B. It is defined as: A mod B = A – B * N -- for an integer N examples: 11 rem 4 results in 3(-11) rem 4 results in -39 mod 4 results in 17 mod (-4) results in –1 (7 – (-4)*(-2) = -1).

Misc. Operators

2 ** 8 = 2563.8 ** 3 = 54.8724 ** (-2) = 1 / (4**2) = 0.0625

Evaluation Rules:

1. Operators evaluated in order of precedence highest are evaluated first. 2. Operators of equal precedence are evaluated from left to right 3. Deepest nested parentheses are evaluated first