805IEEE JOUIRNALOF SOLID-STATECIRCUITS, VOL SC-20, NO 3, JUNE 1985

Special Correspondence

A MicroPower CMOS-Instromentation Amplifier

M. DEGRAUWE, E. VITTOZ, fvfEMBER,IEEE,

AND I. VERBAUWHEDE

Abstract —A CMOS switched capacitor instromentation amplifier is

presented. Offset is reduced by an auto-zero teehnique and effects due to

charge injection are attenuated by a speciaf amplifier configuration. The

circuit which is realized in a 4-pm double poly process has an offset (a) of

370 pV, an rms input referred integrated noise (0.5 – ~C/2) of 79 pV, andconsumes only 21 pW (/= = 8 kHz, ‘V~~ = 3 V).

I. INTRODUCTION

For the realization of intelligent sensors an instrumentation amplifier isvery often required in order to detect small differential signals in thepresence of a large common mode sign+. Such amplifiers should havevery low offset and l/~ noise, large CMRR, and especially for biomedical

applicationsconsume as less as possible current ~d be able to operate ata low sLlpply voltage.

First an offset cancellation technique will be presented. Further theamplifier realization will be discussed and experimental results will begiven.

II AUTO-ZEROREALIZATIONS

Offset cancellation by means of auto-zero techniques can be imple-mented in different ways [1]. Up to now basically two approaches areused.

The first method (see Fig. l(a)) consists of storing the offset informa-tion at the input of the amplifier. Ideally the stored information will beequal to the offset value. However due to charge injection of the switchS1, this vrdue will be significantly changed resulting in a degraded offsetcancellation

A second method (see Fig. l(b)) [2] consists of storing the offsetinformation at the output of the first amplifier stage. In practice thestored offset information will be about 100 times the offset value. There-fore, the charge injection of the switches SI - S2 will not significantlydegrade the offset cancellation. However the need of a two-stage amplifiergives rise to potentiaf stability problems, degraded noise, and PSRRperformances [3].

In this correspondence an alternative auto-zero topology is presented(Fig. l(c)) [5], [8].

AMP is an ordinary amplifier with gaur ,41 (betwqen node 1 andoutput) and offset YO~fl.An auxiliary input (node 2) of reduced sensitivity(gtin A ~ ) is ad@d to the m~n amplifier. It is controlled by a compensa-

tion voltage V2 stored in capacitor C.. The buffer is added to speed up thecompensation phase.

The compensation works as follows. During time slot “a”, the inputsignal is sampled. In the same time the input terminals of the mainamplifier are short-circuited. This amplifier will thus mnplify its ownoffset. However, due to the feedback path through the auxiliary input, theoutput voltage will be stabdized and across the store capacitor C. there

Manuscnpt received October 29, 1984, rmmed December20, 1985 Thi> work waspartiafly supportedby the“Fends NationalSumsepour la Recherche Sclentlflque, PN13 “

M. Degrauwe and E V]ttoz are with Centre Sumse d’ElectFOmque et de hkcrotechmqueS A CSEM— Recherche& D4veloppement—(formerlyCEH) Maladkre 71,2000 Neuchatel7, Switzerland

1. Verbauwhede was w,th CEH m 19S3 on leave from Kathoheke Umverslte,t Leuven.Kardinaal Mercierlaan 94, B-3030 HeveFlee, Belgmm.

Flg 1 Auto-zero techmques (a) In formaacm stored at the input (b) In formatm” storedafter a f]rst gam stage (c) In formatmn stored at a low sens,twe auxihary input

WIII be a voltage equal to

– AIKmL= ~+A2

(1)

At the beginning of time slot “b”, the switches “3” are opened and acharge is injected at node 1. This causes an additional offset AV1. ne

feedback mechanism is however still actwe and the voltage across C. isnow given by

– A1(VO~~l+ AVI)V2=

1+A2(2)

At the end of time slot “b” the switch “l” opens and causes chargeuqection (A V2) at the node 2. The voltage at this node is now gwen by

–A(J%+AL) +AV2,v2=-1+A2

At the output node appears then a voltage equaf to

VOU,= – Al.(

(Km + AVI) +~v2.+z1+A2 1 )

(3)

(4)

which corresponds to an equivalent input which is Al times smaller.Finally during the time slot “c” the charge stored on the capacitor aC

(sample of the input signal) is transferred to the integration capacitor.The equivalent offset of the whole amplifier contains thus two residual

partsthe sum of the initial offset and the charge injection at node 1 whichboth are attenuated by a factor (1+ A ~); andthe charge injection at node 2 which is attenuated by a factor Al /A2.The optimal value of the gain of the anxililary input is obtained by

differentiation of (4)

(A = (VO,fl+AV1)A1 1’2_12 A V2 )

(5)

0018-9200/85 /0600-0805$01 .00 01985 IEEE

806 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-20, NO. 3, JUNE 1985

I I

jP

f+t-’” + “

1p

+;rl

IN 2-4

Fig. 2. Amplifier with auxiliary input. (a) Two parallel input stages. (b) Degeneratedcurrent mirror.

and results in a residual offset of

Voff = 2.(

(Voffl + AV, )AV2 “2

Al )(6)

The choice of Al and ,42 has to be so that the amplifier never saturate,Therefore the method will result in a smaller achievable residual offset forlarger supply voltages. Further, it can be shown that the offset of theauxiliary amplifier can be neglected, provided it is of the same order ofmagnitude as the input offset,

From (5) it is seen that the optimum value of the auxiliary inputdepends on the initial offset of the main amplifier and on the clockinjection on nodes 1 and 2. For small values of ( VOffl+ AVI), the gain A*

should be small and for large ( Voffl+ AVI), the gain ,4* should be larger.For o~timum compensation, the gain A2 should thus not be constant.Recently it has been shown that a quadratic auxiliary input results in abetter offset reduction [4].

If a fixed gain A ~ is used, this gain should be optimized for the largestexpected values of the initial offset and of the clock feedthrough.

III. CIRCUITCONFIGURATIONANDEXPERtMENTALRESULTS

There are several ways to add an auxiliary input at a conventionalamplifier. A first method consists of using two parallel input stages (Fig.2(a)). The ratio of the gain Al ,/A2 will be determined by the ratio of thetransconductances of the two input stages. The bias current 1P* canhowever not be chosen arbitrary small. Due to the offset voltage VO~fl,thecurrent II and 12 can deviate as much as 10 percent of their ideal value.

Fig. 3. Realized amplifier,

Fig. 4. Chip photograph

TABLE IMEASUREMENT RESULTS

Gain (= 4 c/c) 20 dB

tix. clock frequency 8 kffz

(CL = 22 PF)

Offset (at 8 kHz) {3(u

370 JIV

Equivalent input noise (O.5 Hz-4 kHz) 79 Hv

No 1If noise was observed above 0,5 Hz

(= under limit of measurement equipwnt)

CMRR =-95 dB

Current consumption 7 PA

PsaR- (at DC) 54 dll

PSRR+ (at DC) 66 dB

Therefore, the current IP2 should be at least 10 percent of IP1. LargeAl /A2 can thus only be achieved by operating transistors M3– Md much ( Ml, - M19). Those tru,sistors who operate in the linear region can

deeper in strong inversion than transistors MI- M2. This will however modulate the current ratio of two current mirrors. The buffer stages are

result in a large voltage drop across Mq– &fd which can be unacceptable simple source followers ( M20– M23).

for low-voltage battery operation. The circuit has been realized in a 4-pm double poly CMOS process. A

An alternative method consists of degrading a current mirror ratio by chip photograph is shown in Fig. 4. The total chip area is 640 pm x 700

inserting transistors operating in the linear region (Fig. 2(b)) [6], [7]. In Pm ( = 0’45 ‘m’ )“this case the second input is realized with no additional current consump- The most important measurement results are given in Table I. The

tion. However, the gain Al/A ~ will now depend on the supply voltage standard deviation of the offset is 370 pV. Further reduction of the offset

which will result in a reduced PSRR. For battery operation, the specifica- can be obtained by combining the offset cancellation technique of Fig.

tions for the PSRR can however be somewhat relaxed. l(a) and (c).

An SC instrumentation amplifier was developed according to the Recently the presented circuit has been redesigned in a 3-pm technol-

principles of Figs. l(c) and 2(b). The circuit was realized in a differential ogy [9]. Measurement results of this circuit will be reported very soon [10].

way in order to further improve the performances [2].

The amplifier realization is shown in Fig, 3 (sampling and integratingcapacitors are not shown). The main amplifier Ml – M15 is a differential

IV. CONCLUSIONS

transconductance amplifier whose input stage has a low gain. The sec- A micropower instrumentation amplifier has been presented which hasondary inputs are realized by adding four transistors to the main amplifier a typical offset of 370 pV and consumes only 21 pW. The performances

IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-20, NO. 3, JUNE1985

are aclueved by the use of a new offset cancellation technique in whichthe effects of charge rejection are attenuated. For larger supply voltages( ~ 10 V) residual offsets of less than 50 pV are obtainable with thepresented technique.

ACKNOWLEDGNtSNT

The authors wish to thank Dr. H. Oguey for useful discussions.

[1]

[2]

[3]

[4]

[5]

[6][7]

[8]

[9]

[10]

REFERENCES

R. POUJOIS and J. Borel “ Low-1evel MOS transistor arnphfler using storage tech-nmues.” in ISSCC Drz. Tech Parxrs. 1973. m 152-153.R ‘C. Yen and P. R t%y, .(A M’OS swtchedcapacltor instrumentation a.mphfuer,”IEEE J. Sohd-Stafe Circwrs, vol SC-17, pp 1W8–1013, Dec 1982B. J. Hosticka, W Brockherde, and M Wrede, “Effects of the architecture on ncnseperforraamce of CMOS operational amplifiers,” in Proc ECCTD, 1983E. Vittoz, “ Dynanuc anafog techmques: “ Advanced Summer Course on ‘ Des,gn ofMOS-VLSI Clrcmts for Telecommunicatmns,’” L’Aquila, Itafy, June 18-29, 1984.E. VMoz and H Oguey, SWISS Patent Apphcatmn No. 2179/84, filed on April 5.1984H. Oguey, CEH Rep. HO/81, pp. 56-57, Mar. 1981,A Acovic, “Amplificateur h offset compensk,” Masters work of the EPFL, Lausanne,July 1983, (m French)M. Degra”we, E, V,ttoz, and L Verbamvhede, ‘*A Wcropower CMOS instrument-ation amplifier,” m Proc. ESSCIRC ’84 (J?dmburgh, Scotland), September 1984, pp.31-34.I Verbauwhede, “Design and integration of a low-power CMOS SC-mstrumentatlonamplifier,”” M S thesis, K.U Leuven, June 1984 (in Dutch)P Van Peteghem, I Verbauwhede, and W Sansen, “A nmcmpower h@ performanceS.C building block for integrated low level s,gnal prtxessmg,” submitted for pubhca-rion in the J Sohd-Smte Ctrcum

A Design Strategy in CMOS For Microprocessorsand Its Application to the Intel 80C48

M.D. SAHBATOU

Abstract —Tlte main purpose in redesigning the 8048 Intel Microcom-

puter irnlCMOS technology is to test our tool’s efficiency and to evaluate

our design methodology, called CAPRI [1], which researches a good factor

of regrdlarity.

This paper presents a method of implementing microprocessor circuitryin CMOS which uses an ordered stmctnre of the layout. It allows thedesigner to work, with a symbolism, on a grid made of frdysilicon rows andaluminimn columns. Thus, data buses rors in polysilicon lines which seem togive a handicap to this method. Nevertheless, calculations show an accept-able propagation delay time of ~ ns for a 2.5-mm bus (31 ns in the case of

an etluivafent afuminium bus).

I. INTRODUCTION

In designing a microprocessor, we should look for regularity to decreasedesign cost and increase circuit rehability. This criterion gives birth toschools of different styles.

To attain our goal, we have chosen the style of a top-down approach.From the originaf Intel 8048 specifications, we came down to a definitionof a data path architecture which depends essentially upon the decom-position of the algorithm of the instructions.

Then, we considered an implementation strategy in CMOS to draw thecircuit layout.

II. ARCHITECTURE OF THE DATA-PATH

To establish the architecture, we started from the mstrtrction set of the8048 described in the Intel user’s mantraf [2]. Each instruction was

Manuscnpt recewed November 21, 1984, revmed Febmary 5, 1985The author was with the Computer Arciutecture Group, IMAG TIM 3, 38041, Grenoble

Cedex, France He IS now with the Department Electmmque, U S T.O. —B P 1505, Oran elMNAover, A1’gena

807

ABUS+ ! , , , , I t

F,g 1, Data path archltectwe

FIg 2 Microcomputer floor plan

described by an interpretation algorithm, with respect to the five statetimes of each machine cycle and to the extemaJ signafs. We have afsointroduced a two-phase nonoverlapping clock [3]. Each phase (7’1 or T2)lasts 200 ns, for a 6-MHz crystal.

On the other hand, the origrnaf 8048 architecture was based on onesingle bus. As suggested in the CAPRI design methodology, we havechosen a two-bus structure, without precharge, to aflow paraflel transfersduring one phase.

Here is an example of the decomposition of the first two states S1 andS2 which are common to all instructions and concern the incrementationof the program counter

T1 T2

(S1) U1-a:=F’CL; f/2: =O; cin:=0 PCL+-b:==Ul+U2;

OW:==COUT(S2) Ul~u:=PCH, U2:=O; cin:=OVF PCH+b:==Ul+U2;

where c in and c out are, respectively, the carry in and the carry out of theALU.

From the decomposition of the instructions, we derived the data pathwhich is defined by an rmthmetic and logicaf block, some registers, a fewflags and a circuit generating some constants. The arithmetic sectioncontains an 8-bit ALU with two input latches ( fJl and u2), a swapper, a

shifter, a decimaf adJUSt,a zero test, and bit test circuitry.

The working registers consist of an 8-bit address register (W) for the

RAM, a program counter divided into two parts PCL (8 bits) and PCH

(four most significant bits), an accumulator ( .4), a timer (T), a temporary

register (TEMP), an instruction re$ister ( IR ), and a program status word

sectioned into two parts PSH (four most significant bits) and PSL

(three bits for stack pointer). Some flags are afso implemented in the datapath to complete the empty spaces (see Fig. 1).

The data path was built, using a bit-slice approach [4] and the organiza-tion of the whole microcomputer will be as shown in Fig. 2.

III. [MPLEMENTATION IN CMOS

The classicaf method to implement a circuit in NMOS is to draw thebasic cells within two fixed rails in alumiruum. So, with a single metaftechnology both data and power buses run horizontally in ahrmmium, andcommauds run perpendicularly in polysilicon. This layer is more resistivethan afttmirtium, it is used to make grids of transistors and eventuallyinterconnections where rnetaf cannot be used.

As a CMOS design strategy, we adopted the reverse situation whichconsists of data buses in polysilicon horizontal lines, and power buses andcommands in afuminium vertical lines.

With this method, we can afso work on a grid with a uniform pitch,defined by polysilicon rows and metaf columns instead of ahminium rows

0018 -9200/85/0600-0807 $01.00 @U985 IEEE