vlsi classroom material (16-aug-2011)

7/30/2019 Vlsi Classroom Material (16-Aug-2011)

1/37

VLSI

VLSI

Channel Length Modulation:

0 < Vgs < Vth

When Vgs = 0, Ids = 0 therefore the channel not formed, but when Vgs is

increase, channel gradually formed and increasing linearly and when Vgs is

max i.e. Vgs = VDD, The channel length is max:

When Vgs > VDD , Reverse current start flowing (Reverse saturation current).

Channel length gradually decrease and becomes zero this is called Channel

Length Modulation.

The voltage at which Reverse Saturation current start flowing is called Pinchoff voltage.

The Operation of MOSFET is { }V to V th p

i.e. Vth= Threshold voltage, VP =Pinch Off Voltage

Any Device works in this Range Only i.e. 0 < Vgs < Vds

NMOS Characteristics

1) Cutoff Region :

Case 1) Vgs =0; Vgd > Vgs

Vgd Controlling Voltage

Ids = 0, Vds = 0

Cutoff Region Off Region

kT

Vtq

=

Case 2) Vgs Vgs

Vthn = NMOS = 0.2V

Ids = nAmp

Vds = v 0

Page 1


2/37

VLSI

sub- threshold region

2) Linear Region:

Case 1) Vgs > Vth ; Vgd = Vgs [Vgs = 0.2v to 0.5v]

Ids = Amp

Vds = mv 0

Case 2) Vgs > Vth; Vgd < Vgs [Vgs = 0.5v to 1.2v]

0 < Vds < (Vgs - Vth)

Ids = k ( )2

2VdsV V Vgs th ds

Vds

=( )

( )

2

2

&

VdsK V V Vgs th ds

Non Linear I Vds ds

E55555555555555555F

0< Vds < (Vgs Vth)

[i.e. Vgs- Vth = 1.2v 0.2v =1v]

Vds < 1v

x (0,1)

x > x 2

Vds > Vds2 ;2

2

VdsVds >>

( )

2

2

VdsI K V V Vds gs th ds

=

( ){ }I K V V Vds gs th dsLinear

= E55555555555555555F

y = m x

Page 2


3/37

VLSI

Ids

Vgs = Vary

Vds

Voltage controlled device

3) Saturation Region :

Vgs >> Vth ; Vgd < Vth

Vds > (Vgs - Vth)

( )2

2KI V Vthds gs=

&I Vds ds are independents

2I Vds gs (parabolic relationship)

i.e. Ids is Saturation Region

Page 3


4/37

VLSI

I-V Characteristics

Page 4

Vgs

= 2v

Vgs = 1vV

gs= 0v

Saturation Region

Saturation regionfor FET in NMOS

Ids

Vds

Vds

In CRO

Ids


5/37

VLSI

Low Saturation Region = Class A Amplifier = 50 %

Middle Saturation Region = Class B Amplifier = 78.51 %

High Saturation Region = Class C Amplifier = 91%

Having thermal runway problem. Because max power dissipation :

For this graphs using we draw the load line characteristics

And decide the voltage Amp are current Amp.

,

If V Vegs

I Veds

V Ve So take mirror imageds

=

=

=

If Vgs. We get the | Vp |

Vgs 0- vdd

When R current high, Voltage is high

In MOSFET we can avoid B.D. Region

Page 5

Vgs

= 3v

Vgs

= 2v

Vgs

= 1v

Vgs

= 0v

Saturation Region

Vds

Ids

Cutoff

Region

Linear Region

Vth

Mirror Image

Ids

Vds


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VLSI

Summary

1) Cutoff Region Ids = 0 ; Vds = 0

2) Linear Region Ids & Vds increase linearly

3) Saturation Region : Large change in Vds ; Small change in Ids

4) Breakdown Region Large change in Ids ; Small change in Vds

PMOS Characteristics :

Page 6

Breakdown Region

DG

S

Cutoff Region

Large Ids

Small Ids

Ids

VdsV

ds

Large Small Vds

Vgs

= 2v

Vgs

= 1v

Vgs = 0v

Saturation

region

-ve+ve

+ve-ve


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VLSI

1) 0.2V V or V V th tp tp= =

2) , , ,I V V Vds ds gs gd =

To understand CMOS characteristics the common area PMOS & NMOS must be

consider

Transformation on PMOS

Page 7

Cutoff

Region

Vds

IdsLinear

Saturation Region

Vgs = Vgs + Vdd


8/37

VLSI

Analysis of CMOS Inverter

Logic diagram

CMOS Circuit diagram

Page 8

Right Shift

Vds

Vgs = 2v

Vgs = 1v

Vgs = 0v

Ids

Vds

Ids

Vds

Vgs = 2v

Vgs = 1v

Vgs = 0v

+5v

Vtp = -0.2v 0v

In PMOS only


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Names PMOS

C S

L L

S C

VLSI

I/

P

NMO

S

PM

OS0 OFF ON

1 ON OFF

Practically Invertors

0 x

0 1

1 1 Device fail

1 0 for (1,0) will not seen for reducing we are going for (NMOSand PMOS)

Page 9

d

i/p

Vdd(O)

S

O/P


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VLSI

NMOS PMOSCutoff Sat

Linear Sat

Sat Sat C3

Sat Linear

Sat Cutoff

Symmetric CMOS circuit will have condition 3 (set- (e3) set) so avoid

designing of symmetric CMOS circuit.

Asymmetric CMOS circuit. Where Vth is not equal to

Vtp [Vth Vtp] i.e. Vtp = - 0.2 V

Transistor size of compare to another transistor so that Vth is increase. So both

transistor are not ON at a time.

Page 10

Ids

Vds

Vgs = 2v

Vgs = 1v

Vgs = 0v

Vtp=-0.2v

0v

Vgs = 2v

Vgs = 1v VgsLinear (PMOS)

Vgs = 0v

NMOS

Linear

Vtp=0.2v

NMOScutoff

Saturation(NMOS)

Saturation (PMOS

NMOS is continuous saturation regionwhere as PMOS goes to Saturation to linear

& after cutoff region


11/37

VLSI

It increase the size of PMOS transistor so that condition 3 avoided.

The size of PMOS transistor increase in such away that cutoff occupies linear,

linear occupies lower set. After middle set & after higher set. Hence C3 is

avoided leads to the power circuit.

Constrained limit of on size of NMOS. So that we cant increase the size of

NMOS.

Buffer :

Transistor = 1 Buffer Circuit.

O

NMOS O/P = Vgs

PMOS O/P = Vdd- Vgs

Supply Bounce ground Bounce

The performance of NMOS circuit when there are connect to supply. Hence they

are called weak ones

The produce accurate O/P. When they are connect to ground. Hence called

Strong Zeros

PMOS circuits are called strong ones & weak zeros.

Page 11

n

2T 2T

n

di/p

O/p

Vd

d

1

O

O/p

= Vgs- Vth

= Vgs=0V

Vdd

Vgs =0

Vgs = 012345


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VLSI

Note : Always connect NMOS to ground, PMOS to supply

Because PMOS connect to supply it takes extra energy from supply and response

an same as NMOS. Hence O/P is synchronizing. Therefore increase the size of

PMOS transistor.

If increaser the transistor NMOS. We should connect Vdd to NMOS. NMOS

should not accept ones cause NMOS ones are weak. So that we are increase the

size of PMOS and apply extra energy to PMOS.

Application of CMOS

Power Dissipation

Total Power = Dynamic + static + leakage + SIC

PT = Pdy + PSTA + Ple + PSLC

Dynamic power (py) = f VDD2 CL

Transition Activity

f Operating Frequency

VDD Supply voltage

CL Load Capacity

E = CV 2

E = CV2

P = E/T = f.E = FCV2

But for is no of cycles

P = (, f) CV2

P= (, f) CV2

If pdy , then f (x cant change) , C VDD (x cant change)

Page 12


13/37

VLSI

x

To Reduce dynamic power Transition activity() must be reduced.

is also called Hamming Distance i/p pattern.

= 8

1 0 1 1 0 1 1 ; = 4

1 1 1 1 1 ; = 0

If, dy also

Static Power :

P static = Static. VDD

[static= DC current (Every Transistor have point from point]

Static technology is sinking static power decreases. S D

Distance , VDD so Q point (static also decreases)

Transistor size is , VDD, Q source to destination is small

Short Circuit Power :

Page 13

Systemi/p

o/p

power

ENCODE System Decode

S1 S2 S3

O/P

S > S1 + S2 + S3


14/37

VLSI

1) |Vth| = -0.32V

Vthn= 0.2V

2) Bp = 2.5 Bn

Bp = Size of PMOS

Bp = Size of NMOS

NMOS general PMOS transistor is 8 times of NMOS transistors

i.e. Bp = 3 Bn

Leakage Power :

With sinking technology leakage current increase. Therefore leakage power increase.

65 nm VDD : 0. 9 V

VDD > VDD2

0.9 > 0.8

VDD = 10 V VDD2 = 100

VDD = 11 V VDD2 = 125

Page 14

I/p

VDD

O/p

ConductorL2


15/37

VLSI

VDD = 12 V VDD2 = 150

VDD = 13 V VDD2 = 225

VDD = 3V 9

VDD = 2V 4 To make VDD = 0. Connect adiabatic circuit

All Medical (Commented) applications are lower power and low speed

All Military Applications (-55 to 125c) are high power and high speed.

Dynamic power is high at higher technologies the technology shrinking dynamic

power reduces.

At lower technologys short circuit & leakage power can increase. Because the

channel length is small.

Pdy + Pstat + Ple + Pslc

Higher technology Lower Technology

PDy+Pst dominates PLe & PSlc dominates

High Speed Circuit

RC Circuit:

Page 15

SPEED

Low Speed

< 800 MHz

1. Capacitor

2. RL Circuit

High Speed

> 800 MHz

1. Inductive

2. RLC Circuit


16/37

VLSI

t 50% = 0.693 RC

T = RC

If R = 5, C = 5

t50% = K (RC)

= K (25)

T = 1 + 1 + 1 + 1 + 1

= 5

t50% = K(5)

= t 50% , delay , speed

= l , R, T speed

Longer wire having p , speed

Short wire having p , speed Longer inter connects have larger delays. So therefore low speed & low power

Shorter inter connects have small delays. So high speed & high power.

RLC Circuit :

Page 16

RV

C


17/37

VLSI

For RLC circuit T is not defined (Undefined)

Delay is always lower than time Unit

If XL = C Resistive. So T is not defined

t50% spice

Depletion Mode MOSFET (MOS capacitor)

Source and drain are Equally Doped where as Enhance mode mosFET source is

higher than drain Oxide thickness, gate & substite thickness cannot be neglected.

The device is in the S.S. Region. In L.L. region v=0 & = constant.

Steppers are insulating material to avoids Recombination of substrate holes and

Electrons of source and drain.

Page 17

R

C

L

V=

0

- 0x

S D

P-Substrate


18/37

VLSI

Stappers are used near source junction and drain junction.

C = 0A/d(tox); Q = CV;

If (tox) ,C= 0A/d

So C

Depletion mode threshold voltage is Ve

Q = CV

Q = Constant

C = V

V = 0 V < 0

V = -0.52 V (Si)V = -0.89V (Ge)

Threshold of mosFET

Depletion Region or Accumulation:

Conversion Region

Flate band region current constant S & D are etui potential

When Vgs = 0V. The all -1 are accumulated at source.

A Small no. of e- push towards the drain and they are recombine with

holes of gate As a result e- occupies the channel then form the (-Ve) plate.

There for mosFET act as capacitor in accumulation region.

Page 18

tox

tg

tox Both

tg are

suffix

tox

tg


19/37

VLSI

Enhancement Mode Depletion Mode

1. Source is highly Dopped than drain1. Source & Drain equally

Dopped2. Oxide, gate, subscribe thickness are

neglected2. All are consider

3. Threshold is (+Ve) 3. Threshold is (-Ve)

4. Applications:

Switch, sometimes Amplifier Capacitor

4. Breakdown Region Occurs

When (Vgs >> VDD)4. Breakdown does not occur

Fabrication Principles :

Basic Steps :

They are 10 steps

1) Water fabrication

2) Oxidation Dry

Wet

3) Masking, patterning or photolithography

4) Diffusion Pre diffusion

Drive In

5) Ion Implication

6) Deporition

7) Metalization

8) Passivation

9) Annealing

10) Clean chip

Semi Conductor : (Si/Ge)

1) SiO2 Sand 80% Si + 20% Impure

Graphite 10% Si + 90 % impure

Page 19


20/37

VLSI

2) SiO2 15000C - 20000C Rixe the temp 15000C Oxide partials are removed Si in the

water state is consider by cooling down the temp Ingot is formed.

3) It is a cylindered shape or Clone shape.

Oxidation :

O2 vapour is layered on wafer

To avoide varying component current oxidation or oxide layer is used.

Patterning on masking or Photolithography

Page 20

disk

Add

Wafer

P and n

type

Dry Wet

O2

(1500-2000

c) vapour

H2O

(1500-2000c)H

2Components are removed

pure O2

vapour

Oxidatio

n

U,V Rays

Substrate


21/37

VLSI

If photo rays are used to remove the oxide layer then the process is called

photolithography

Diffusion:

1) Pre Diffusion

2) Drive In

Pre Diffusion :

The left over oxide partial in step3, are removed in pre diffusion states.

With 1st Cl Steps counteraction of substrate might decrease by adding Extra i on

concentration can be gained back.

Deposition :

1 Deposite n-type material at source & drain p-type material at gate.

2 At deposition stage exact source, gate & drain formed.

Metalization

A1 < 1994

Widely used Cu


22/37

VLSI

Al 5 metal layer

Cu 8 metal layer

But Iron have more than 8 metal layer. But Iron have some disadvantage.

Diagonal routing is not possible.

Passivation :

Bringing down the temperature to room temperature is called as Passivation

GDSSRTL GDS2

RTL - Silicon

For every VLSC components have another GDSS (Graphic Data System Stream)

Annealing :

If any radio activity nature exists that radio activity nature can be removed.

From 1st step on wards we are making a high temperature only.

Clean Chip:

The edges of course, gate and drain are sharply cut.

Enhancement Mode

(In terms of fabrication)

Depletion Mode

(In terms of fabrication)

1. Water fabrication made at 10m 1. 40-6010m2. Oxidation is same 2. Same

3. Patterning is same 3. Same

4. Diffusion

Pre diffusion

Drive-In

4. Diffusion is same

5. Room Temperature are same 5. Same6. Deposition 6. Deposition

7. Remaining all are same 7. Same

Region of Operation :

Page 22


23/37

VLSI

Various Pull-ups :

pull up N/W is S.C>

Page 23

Vgs< Vtn

Cutoff

Vgs > (Vgs-Vtn)

Vdl (Vgs-Vtn) linear Vdl (Vgs-Vtn)

saturation

Vgs, Vtn, Vds

i/p

VDD

p-mos

n-mos

p-mos pullup N/W

N-mos pull down. N/W

PUN

PDN

i/p o/p

P-mos Parallel series

n-mos Series parallel


24/37

VLSI

Case 1)

PUN SLC

O/P Vds

Disadvantage :

High power dissipation at o/p

Drain may be damaged.

Case 2) For control the current put a resistor

PUN = Resistor

O/P = VDD ID RD

Disadvantage :

Device mis match, Hence fabrics is very difficult

Page 24

G

+Vgs

D

VDD

O/p

Vds

S

C

i/p

D

VDD

O/p

ID RD


25/37

VLSI

Case 3)

Depletion mode :

Disadvantage : Device mis match, power units (text is not visible in original format)

more high power defray patches.

Hence current always flower. Therefore high power dissipation circuits.

Case 4)

PUN = PMOS & Best Design

PUN is ON and OFF depends on i/p. Hence low power Circuit.

Q) Find the VCn or m1

Vt1 = 0.5v ; Vt2 = 2.55V

Page 25

C

i/p

l

O/p

VDD

O/p

Act as resistor

PUN always on

i/p

O/p

VDD

This is the best

N/W

Vgs

= 3v

O/p = 5V

VDD

= 5v

M2

In PUN is

always vgs = 0

M1


26/37

VLSI

Transistor m1

Vgs= 3V

Vds = 5V

Vgs = 0.5V

Vds1 > (Vgs1 vt1)

5 > ( 3 - 0.5 )

Set

Transistor m2

Vgs2 = 0

Vt2 = -2.55

Vds2 = 3V ( 8-5)

Vgs2 Vt = 2.55 V

V gs2 > (Vgs

2-Vt2)

Set

Q) Find the Ratio x of Size of Transistor

Because of Both are saturation region. So Ids1=Ids2

Note : Use current (text is not visible in original format) to calculate the

sizes of transistors always.

( )

( )

( )

( )

211 1 1

222 2 2

21 2.5

22 2.55

I K V Vds gs t

I K V Vds gs t

KSuffix

K

=

=

==

K1 = 1.04K2

PUN size is always greater than PDNN i.e. P-mos circuit always > the N-mos

circuit.

According to problem that values are not valid.

Page 26


27/37

VLSI

Vt1 = 0.5 V ; Vt2 = - 0.5 V

M1 : Vds < (Vgs1-Vt1)

Vds < (9 -0.5)

Linear

M2 : Vds2 > (Vgs2 Vt2)

Set

Q) For m1 be the saturation region what must be the range of i/p

0 4.51Vgs

vlsi classroom material (16-aug-2011)

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