TheVLSIHandbookSecond Edition 4199_C000.fmPage iTuesday, November 14, 20065:30 PM The Electrical Engineering Handbook Series Series Editor Richard C. Dorf University of California, Davis Titles Included in the Series The Handbook of Ad Hoc Wireless Networks, Mohammad Ilyas The Avionics Handbook, Second Edition, Cary R. Spitzer The Biomedical Engineering Handbook , Third Edition, Joseph D. Bronzino The Circuits and Filters Handbook, Second Edition , Wai-Kai Chen The Communications Handbook, Second Edition, Jerry Gibson The Computer Engineering Handbook, Vojin G. Oklobdzija The Control Handbook , William S. Levine The CRC Handbook of Engineering Tables, Richard C. Dorf The Digital Avionics Handbook , Second Edition Cary R. Spitzer The Digital Signal Processing Handbook , Vijay K. Madisetti and Douglas Williams The Electrical Engineering Handbook , Second Edition, Richard C. Dorf The Electric Power Engineering Handbook , Leo L. Grigsby The Electronics Handbook , Second Edition, Jerry C. Whitaker The Engineering Handbook, Third Edition , Richard C. Dorf The Handbook of Formulas and Tables for Signal Processing , Alexander D. Poularikas The Handbook of Nanoscience, Engineering, and Technology, William A. Goddard, III,Donald W. Brenner, Sergey E. Lyshevski, and Gerald J. Iafrate The Handbook of Optical Communication Networks, Mohammad Ilyas and Hussein T. Mouftah The Industrial Electronics Handbook , J. David Irwin The Measurement, Instrumentation, and Sensors Handbook , John G. Webster The Mechanical Systems Design Handbook , Osita D.I. Nwokah and Yidirim Hurmuzlu The Mechatronics Handbook , Robert H. Bishop The Mobile Communications Handbook , Second Edition , Jerry D. Gibson The Ocean Engineering Handbook , Ferial El-Hawary The RF and Microwave Handbook , Mike Golio The Technology Management Handbook , Richard C. Dorf The Transforms and Applications Handbook , Second Edition, Alexander D. Poularikas The VLSI Handbook , Second Edition , Wai-Kai Chen 4199_C000.fmPage iiTuesday, November 14, 20065:30 PMEdited byWai-Kai ChenUniversity of IllinoisChicago, USACRC Press is an imprint of theTaylor & Francis Group, an informa businessBoca Raton London New York 4199_C000.fmPage iiiTuesday, November 14, 20065:30 PM CRC PressTaylor & Francis Group6000 Broken Sound Parkway NW, Suite 300Boca Raton, FL 33487-2742 2007 by Taylor & Francis Group, LLCCRC Press is an imprint of Taylor & Francis Group, an Informa businessNo claim to original U.S. Government worksPrinted in the United States of America on acid-free paper10 9 8 7 6 5 4 3 2 1International Standard Book Number-10: 0-8493-4199-X (Hardcover)International Standard Book Number-13: 978-0-8493-4199-1 (Hardcover)Thisbookcontainsinformationobtainedfromauthenticandhighlyregardedsources.Reprintedmaterialisquotedwithpermission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publishreliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materialsor for the consequences of their use.No part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or othermeans, now known or hereafter invented, including photocopying, microlming, and recording, or in any information storageor retrieval system, without written permission from the publishers.Forpermissiontophotocopyorusematerialelectronicallyfromthiswork,pleaseaccesswww.copyright.com(http://www.copyright.com/)orcontacttheCopyrightClearanceCenter,Inc.(CCC)222RosewoodDrive,Danvers,MA01923,978-750-8400.CCCisanot-for-protorganizationthatprovideslicensesandregistrationforavarietyofusers.Fororganizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. TrademarkNotice: Productorcorporatenamesmaybetrademarksorregisteredtrademarks,andareusedonlyforidentication and explanation without intent to infringe. Visit the Taylor & Francis Web site athttp://www.taylorandfrancis.comand the CRC Press Web site athttp://www.crcpress.comLibrary of Congress Cataloging-in-Publication Data The VLSI handbook / edited by Wai-Kai Chen.2nd ed.p. cm.(Electrical engineering handbook series; 38)Includes bibliographical references and index.ISBN 0-8493-4199-X1. Integrated circuitsVery large scale integration. I. Chen, Wai-Kai, 1936- II. Title. III. Series.TK7874.75.V573 2006621.395dc222006050477 4199_C000.fmPage ivTuesday, November 14, 20065:30 PM v Preface We are most gratied to nd that the rst edition of The VLSI Handbook (2000) was well received andis widely used. Thus, we feel that our original goal of providing in-depth professional-level coverage ofVLSI technology was, indeed, worthwhile. Seven years is a short time in terms of development of scienceand technology; however as this handbook shows, momentous changes have occurred during this period,necessitating not only the updating of many chapters of the handbook, but more startling, the additionandexpansionofmanytopics.Signicantexamplesarelow-powerelectronicsanddesign,testingofdigitalsystems,VLSIsignalprocessing,anddesignlanguagesandtoolstonameafewofthemoreprominent additions. Purpose The VLSIHandbook providesinasinglevolumeacomprehensivereferenceworkcoveringthebroadspectrum of VLSI technology. It is written and developed for practicing electrical engineers in industry,government,andacademia.Thegoalistoprovidethemostup-to-dateinformationinintegratedcircuits(IC)technology,devicesandtheirmodels,circuitsimulations,low-powerelectronicsand design, ampliers, analog and logic circuits, memory, registers and system timing, microprocessorandASIC,testandtestability,designautomation,VLSIsignalprocessing,anddesignlanguagesandtools.Thehandbookisnotanall-encompassingdigestofeverythingtaughtwithinanelectricalengineeringcurriculumonVLSItechnology.Rather,itistheengineersrstchoiceinlookingforasolution. Therefore, full references to other sources of contributions are provided. The ideal reader isaBSlevelengineerwithaneedforaone-sourcereferencetokeepabreastofnewtechniquesandproceduresaswellasreviewstandardpractices. Background Thehandbookstressesfundamentaltheorybehindprofessionalapplications.Todoso,itisreinforcedwith frequent examples. Extensive development of theory and details of proofs have been omitted. Thereaderisassumedtohaveacertaindegreeofsophisticationandexperience.However,briefreviewsoftheories,principles,andmathematicsofsomesubjectareasaregiven.Thesereviewshavebeendoneconcisely with perception. The handbook is not a textbook replacement, but rather a reinforcement andreminder of material learned as a student. Therefore, important advancement and traditional as well asinnovative practices are included.Since most of the professional electrical engineers graduated before powerful personal computers werewidelyavailable,manycomputationalanddesignmethodsmaybenewtothem.Therefore,computersand software use are thoroughly covered. Not only does the handbook use traditional references to citesources for the contributions, but it also contains all relevant sources of information and tools that would 4199_C000.fmPage vTuesday, November 14, 20065:30 PM vi Preface assist the engineer in performing his/her job. This may include sources of software, databases, standards,seminars, conferences, etc. Organization Over the years, the fundamentals of VLSI technology have evolved to include a wide range of topics anda broad range of practice. To encompass such a wide range of knowledge, the handbook focuses on thekeyconcepts,models,andequationsthatenabletheelectricalengineertoanalyze,design,andpredictthe behavior of very large-scale integrated circuits. While design formulas and tables are listed, emphasisis placed on the key concepts and theories underlying the applications.The information is organized into 13 major sections, which encompass the eld of VLSI technology.Each section is divided into chapters, each of which is written by a leading expert in the eld to enlightenandrefreshknowledgeofthematureengineer,andtoeducatethenovice.Eachsectioncontainsintro-ductorymaterial,leadingtotheappropriateapplications.Tohelpthereader,eacharticleincludestwoimportantandusefulcategories:deningtermsandreferences. Deningterms arekeydenitionsandtherstoccurrenceofeachtermdenedisindicatedinitalictypeinthetext.The references providealist of useful books and articles for further reading and for additional information on the topic. Locating Your Topic Numerous avenues of access to information contained in the handbook are provided. A complete tableof contents is presented at the beginning of the book. In addition, an individual table of contents precedeseach of the 13 sections. Finally, each chapter begins with its own table of contents. The reader is urgedto review these tables of contents to become familiar with the structure, organization, and content of thebook. For example, see Section VIII: Microprocessor and ASIC, then Chapter 64: Microprocessor DesignVerication, and then Section 64.2: Design Verication Environment. This tree-like structure enables thereader to move up the tree to locate information on the topic of interest.A combined subject and author index has been compiled to provide means of accessing information.It can also be used to locate denitions; the page on which the denition appears for each key deningterm is given in this index. The VLSI Handbook is structured to provide answers to most inquiries and to direct inquirer to furthersources and references. We trust that it will meet your needs. Acknowledgments Thecompilationofthisbookwouldnothavebeenpossiblewithoutthededicationandeffortsofthesection editors, the publishers, and most of all the contributing authors. I wish to thank all of them andalso my wife, Shiao-Ling, for her patience and understanding. Wai-Kai Chen Editor-in-Chief 4199_C000.fmPage viTuesday, November 14, 20065:30 PM vii Editor-in-Chief Wai-Kai Chen is professor and head emeritus of the Department of Electrical Engineering and ComputerScience at the University of Illinois at Chicago. He received his BS and MS in electrical engineering fromOhioUniversity,wherehewaslaterrecognizedasadistinguishedprofessor.HeearnedhisPhDinelectricalengineeringfromtheUniversity of Illinois at Urbana-Champaign.Professor Chen has extensive experience in education and industryandisveryactiveprofessionallyintheeldsofcircuitsandsystems.He has served as visiting professor at Purdue University, University ofHawaii at Manoa, and Chuo University in Tokyo, Japan. He was editorof the IEEE Transactions on Circuits and Systems, Series I and II, pre-sidentoftheIEEECircuitsandSystemsSociety,andisthefoundingeditor and editor-in-chief of the Journal of Circuits, Systems and Com-puters .HereceivedtheLesterR.Ford AwardfromtheMathematicalAssociationofAmerica,theAlexandervonHumboldtAwardfromGermany, the JSPS Fellowship Award from Japan Society for the Pro-motionofScience,theNationalTaipeiUniversityofTechnologyDistinguished Alumnus Award, the Ohio University Alumni Medal ofMeritforDistinguishedAchievementinEngineeringEducation,theSenior University Scholar Award and the 2000 Faculty Research AwardfromUniversityofIllinoisatChicago,andtheDistinguishedAlumnusAwardfromtheUniversityofIllinois at Urbana-Champaign. He is also the recipient of the Golden Jubilee Medal, the Education Award,the Meritorious Service Award from IEEE Circuits and Systems Society, and the Third Millennium MedalfromtheIEEE.Hehasalsoreceivedmorethanadozenhonoraryprofessorshipawardsfrommajorinstitutions in Taiwan and China.A fellow of the Institute of Electrical and Electronics Engineers and the American Association for theAdvancement of Science, Professor Chen is widely known in the profession for his published works whichinclude AppliedGraphTheory (North-Holland), TheoryandDesign ofBroadbandMatchingNetworks (PergamonPress), ActiveNetworkandFeedbackAmplierTheory (McGraw-Hill), LinearNetworksandSystems (Brooks/Cole), PassiveandActiveFilters:TheoryandImplements (JohnWiley), TheoryofNets:Flows in Networks (Wiley-Interscience), The Circuits and Filters Handbook (CRC Press), and The ElectricalEngineering Handbook (Elsevier Academic Press). Wai-Kai Chen 4199_C000.fmPage viiTuesday, November 14, 20065:30 PM 4199_C000.fmPage viiiTuesday, November 14, 20065:30 PM ix Contributors Ramachandra Achar Department of Electronics Carleton UniversityOttawa, Ontario, Canada Arshad Ahmed DSP R&D Texas Instruments, Inc. Dallas, Texas Jonathan A. Andrews Department of Electrical and Computer EngineeringVirginia Commonwealth UniversityRichmond, Virginia James H. Aylor School of Engineering and Applied ScienceUniversity of VirginiaCharlottesville, Virginia R. Jacob Baker Department of Electrical and Computer EngineeringUniversity of Idaho at Boise Boise, Idaho Andrea Baschirotto Department of Innovation EngineeringUniversity of LecceLecce, Italy Charles R. Baugh C. R. Baugh and AssociatesSeattle, Washington Magdy Bayoumi The Center for Advanced Computer StudiesUniversity of Louisiana Lafayette, Louisiana David Blaauw Department of Electrical Engineering and Computer ScienceUniversity of MichiganAnn Arbor, Michigan Victor Boyadzhyan Jet Propulsion LaboratoryPasadena, California Alison Burdett Toumaz Technology Ltd.Abingdon, UK Wai-Kai Chen University of IllinoisChicago, Illinois Kuo-Hsing Cheng Tamkang UniversityTamkang, Taiwan Bi-Shiou Chiou Department of Electronics EngineeringNational Chiao Tung UniversityHsinchu, Taiwan John Choma, Jr. Department of Electrical Engineering/ElectrophysicsUniversity of Southern CaliforniaLos Angeles, California Amy Hsiu-Fen Chou National Tsing-HuaUniversityHsinchu, Taiwan Moon Jung Chung Department of Computer ScienceMichigan State UniversityEast Lansing, Michigan David J. Comer Department of Electrical and Computer EngineeringBrigham Young UniversityProvo, Utah Donald T. Comer Department of Electrical and Computer EngineeringBrigham Young UniversityProvo, Utah Daniel A. Connors Department of Computer ScienceUniversity of ColoradoBoulder, Colorado Donald R. Cottrell Silicon IntegrationInitiative, Inc. Austin, Texas John D. Cressler School of Electrical and Computer EngineeringGeorgia Institute of TechnologyAtlanta, Georgia 4199_C000.fmPage ixTuesday, November 14, 20065:30 PM x Contributors Sorin Cristoloveanu Institute of Microelectronics, Electromagnetism and PhotonicsGrenoble, France Wouter De Cock Katholieke Universiteit LeuvenLeuven-Heverlee, Belgium Abhijit Dharchoudhury Motorola, Inc.Austin, Texas Robert P. Dick Department of Electrical Engineering and Computer ScienceNorthwestern UniversityEvanston, Illinois Vassil S. Dimitrov Department of Electrical and Computer EngineeringUniversity of CalgaryCalgary, Alberta, Canada Donald B. Estreich Microwave Technology DivisionAgilent TechnologiesSanta Rosa, California John W. Fattaruso Texas Instruments, Inc.Dallas, Texas Ayman A. Fayed Texas Instruments, Inc.Dallas, Texas Eby G. Friedman Department of Electrical and Computer EngineeringUniversity of RochesterRochester, New York Shantanu Ganguly Intel CorporationAustin, Texas Aman Gayasen Department of Computer Science and EngineeringPennsylvania State UniversityUniversity Park, Pennsylvania Jan V. Grahn School of Information and Communication Technology KTH, Royal Institute of TechnologyKista, Sweden Flavius Gruian Department of Computer ScienceLund University Sweden Maria del Mar Hershenson Stanford UniversityStanford, California Charles Ching-Hsiang Hsu National Tsing-Hua UniversityHsinchu, Taiwan Jen-Sheng Hwang National Science CouncilTaipei, Taiwan Wen-mei W. Hwu University of Illinois atUrbana-ChampaignUrbana, Illinois Kazumi Inoh Center for Semiconductor Research andDevelopmentSemiconductor CompanyToshiba CorporationYokohama, Japan Ali Iranli Electrical Engineering DepartmentUniversity of Southern CaliforniaLos Angeles, California K. Irick Department of Computer Science andEngineeringPennsylvania StateUniversityUniversity Park,Pennsylvania M. J. Irwin Department of Computer Science and EngineeringPennsylvania State UniversityUniversity Park, Pennsylvania Hidemi Ishiuchi Center for Semiconductor Research and DevelopmentSemiconductor CompanyToshiba CorporationYokohama, Japan Mohammed Ismail Department of Electrical and Computer EngineeringOhio State UniversityColumbus, Ohio Hiroshi Iwai Frontier Collaborative Research CenterTokyo Institute of TechnologyYokohama, Japan Vikram Iyengar IBM MicroelectronicsEssex Junction, Vermont W. Kenneth Jenkins Department of Computer Science and EngineeringPennsylvania State UniversityUniversity Park, Pennsylvania Jeff Jessing Department of Electrical and Computer EngineeringBoise State UniversityBoise, Idaho Niraj K. Jha Department of Electrical EngineeringPrinceton UniversityPrinceton, New Jersey Graham A. Jullien Department of Electrical and Computer EngineeringUniversity of CalgaryCalgary, Alberta, Canada 4199_C000.fmPage xTuesday, November 14, 20065:30 PM Contributors xi Dimitri Kagaris Department of Electrical and Computer EngineeringSouthern Illinois UniversityCarbondale, Illinois Steve M. KangUniversity of California at Santa CruzSanta Cruz, CaliforniaNick KanopoulosAtmel CorporationMorrisville, North CarolinaNaghmeh Karimi Electrical and Computer EngineeringUniversity of TehranTehran, IranTanay KarnikStrategic CAD LabsIntel CorporationHillsboro, OregonYasuhiro KatsumataEngineering Planning DivisionSemiconductor CompanyToshiba CorporationKawasaki, Japan Ali KeshavarziCircuit Research LabsIntel CorporationHillsboro, Oregon Heechul KimDepartment of Computer Science and EngineeringHankuk University of Foreign StudiesYongin, Kyung Ki-Do, KoreaJihong KimSchool of Computer Science and Engineering Seoul National University Seoul, KoreaHideki KimijimaSystem LSI Division IISemiconductor CompanyToshiba CorporationKitakyushu, JapanRobert H. KlenkeDepartment of Electrical and Computer EngineeringVirginia Commonwealth UniversityRichmond, VirginiaIvan S. KourtevDepartment of Electrical and Computer EngineeringUniversity of PittsburghPittsburgh, PennsylvaniaSeok-Jun LeeDSP R&DTexas Instruments, Inc. Dallas, TexasThomas H. LeeStanford UniversityStanford, CaliforniaHarry W. LiFormerly with the University of Idaho at BoiseYijun LiThe Center for Advanced Computer StudiesUniversity of Louisiana Lafayette, LouisianaChi-Sheng LinDepartment of Electrical EngineeringNational Cheng Kung UniversityTainan, TaiwanFrank Ruei-Ling LinNational Tsing-Hua UniversityHsinchu, TaiwanBin-Da LiuDepartment of Electrical EngineeringNational Cheng Kung UniversityTainan, TaiwanJohn LockwoodDepartment of Computer Science and EngineeringWashington UniversitySt. Louis, MissouriStephen I. LongDepartment of Electrical and Computer EngineeringUniversity of CaliforniaSanta Barbara, California Ashraf LotEnpirion, Inc.Bridgewater, New Jersey B. Gunnar MalmSchool of Information and Communication Technology KTH, Royal Institute of TechnologyKista, SwedenMohammad MansourDepartment of Electrical and Computer Engineering American University of BeirutBeirut, LebanonDiana MarculescuDepartment of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburgh, Pennsylvania Radu MarculescuDepartment of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburgh, PennsylvaniaMartin MargalaElectrical and Computer Engineering DepartmentUniversity of MassachusettsLowell, Massachusetts Shin-ichi MinatoNTT Network Innovation LaboratoriesKanagawa, JapanShahrzad MirkhaniElectrical and Computer Engineering DepartmentUniversity of TehranTehran, IranSunderarajan S. MohanStanford UniversityStanford, California4199_C000.fmPage xiTuesday, November 14, 20065:30 PMxii ContributorsHisayo S. MomoseCenter for Semiconductor Research and DevelopmentSemiconductor CompanyToshiba CorporationYokohama, Japan Eiji MorifujiSystem LSI Division ISemiconductor Company Toshiba CorporationYokohama, JapanToyota MorimotoMemory DivisionSemiconductor CompanyToshiba CorporationYokohama, Japan Saburo MurogaUniversity of Illinois at Urbana-ChampaignUrbana, IllinoisRoberto Muscedere Research Centre for Integrated Microsystems (RCIM)University of WindsorOntario, Canada Akio NakagawaDiscrete Semiconductor DivisionSemiconductor CompanyToshiba CorporationKawasaki, JapanYuichi NakamuraNEC CorporationKawasaki, JapanMichel S. NakhlaDepartment of ElectronicsCarleton UniversityOttawa, Ontario, CanadaZainalabedin NavabiNanoelectronics Center of ExcellenceSchool of Electrical and Computer EngineeringUniversity of TehranTehran, IranPhilip G. NeudeckNASA Glenn Research CenterCleveland, Ohio C. NicopoulosDepartment of Computer Science and EngineeringPennsylvania State UniversityUniversity Park, PennsylvaniaHideaki NiiSystem LSI Division ISemiconductor CompanyToshiba CorporationYokohama, JapanUmit Y. OgrasDepartment of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburgh, Pennsylvania Tatsuya OhguroCenter for Semiconductor Research and DevelopmentSemiconductor CompanyToshiba CorporationYokohama, Japan Mikael stlingSchool of Information and Communication Technology KTH, Royal Institute of TechnologyKista, SwedenSeok-Bae ParkDepartment of Electrical and Computer EngineeringOhio State UniversityColumbus, Ohio Alice C. ParkerDepartment of Electrical Engineering-SystemsUniversity of Southern CaliforniaLos Angeles, California Massoud PedramElectrical Engineering DepartmentUniversity of Southern CaliforniaLos Angeles, California Patrick ReynaertElektrotechniek, ESAT-MICASKatholieke Universiteit LeuvenLeuven-Heverlee, BelgiumMahsan RofoueiNanoelectronics Center of ExcellenceSchool of Electrical and Computer EngineeringUniversity of TehranTehran, IranJ. Gregory RollinsAntrim Design SystemsScotts Valley, CaliforniaSaeed SafariNanoelectronics Center of ExcellenceSchool of Electrical and Computer EngineeringUniversity of TehranTehran, IranKirad SamavatiStanford UniversityStanford, CaliforniaNaresh R. ShanbhagElectrical and Computer Engineering DepartmentUniversity of Illinois atUrbana-ChampaignUrbana, IllinoisLi ShangDepartment of Electrical and Computer EngineeringQueens UniversityKingston, Ontario, CanadaRick Shih-Jye ShenNational Tsing-Hua UniversityHsinchu, TaiwanBing J. SheuTaiwan Semiconductor Manufacturing CompanyTaiwanDongkun ShinSamsung Electronics Co., LTD.Suwon, Korea4199_C000.fmPage xiiTuesday, November 14, 20065:30 PMContributors xiiiMuh-Tian ShiueDepartment of Electrical EngineeringNational Central UniversityChung-Li, TaiwanHamid ShojaeiElectrical and Computer Engineering DepartmentUniversity of TehranTehran, IranBang-Sup SongDepartment of Electrical and Computer EngineeringUniversity of CaliforniaSan Diego, California Michiel SteyaertKatholieke Universiteit Leuven Leuven-Heverlee, BelgiumEarl E. Swartzlander, Jr.Department of Electrical and Computer EngineeringUniversity of TexasAustin, TexasHaruyuki TagoToshiba Semiconductor CompanySaiwai, Kawasaki, JapanNaofumi TakagiDepartment of Information EngineeringNagoya UniversityNagoya, JapanEmil TalpesAdvanced Micro Devices, Inc.Sunnyvale, CaliforniaBaris TaskinDepartment of Electrical and Computer EngineeringDrexel UniversityPhiladelphia, PennsylvaniaDonald C. ThelenAmerican Microsystems, Inc.Bozeman, MontanaT. TheocharidesDepartment of Electrical and Computer EngineeringUniversity of Cyprus, Cyprus Yosef Tirat-Gefen Department of Electrical Engineering-SystemsUniversity of Southern CaliforniaLos Angeles, CaliforniaChris ToumazouInstitute of Biomedical EngineeringUniversity of LondonLondon, UKSpyros TragoudasDepartment of Electrical and Computer EngineeringSouthern Illinois UniversityCarbondale, Illinois Yuh-Kuang TsengIndustrial Research and Technology InstituteHsinchu, TaiwanN. VijaykrishnanDepartment of Computer Science and EngineeringPennsylvania State UniversityUniversity Park, PennsylvaniaSuhrid A. WadekarDepartment of Electrical Engineering-SystemsUniversity of Southern CaliforniaLos Angeles, CaliforniaChorng-Kuang WangDepartment of Electrical EngineeringNational Taiwan UniversityTaipei, TaiwanR. F. WassenaarDepartment of Electrical EngineeringUniversity of TwenteThe NetherlandsLouis A. Williams IIITexas Instruments, Inc.Dallas, Texas Wayne WolfDepartment of Electrical EngineeringPrinceton UniversityPrinceton, New Jersey Chung-Yu WuDepartment of Electronics EngineeringNational Chiao Tung UniversityHsinchu, TaiwanEvans Ching-Song YangNational Tsing-Hua UniversityHsinchu, TaiwanKazuo YanoSystem LSI Research DepartmentCentral Research LaboratoryHitachi Ltd.Kokubunji, Tokyo, JapanKo YoshikawaCAD DepartmentComputers DivisionNEC CorporationFuchu, Tokyo, JapanKuniyoshi YoshikawaQuality Promotion CenterSemiconductor CompanyToshiba CorporationYokohama, Japan Takashi YoshitomiSystem LSI Division ISemiconductor CompanyToshiba CorporationTokyo, JapanMin-Shueh YuanDepartment of Electrical EngineeringNational Taiwan UniversityTaipei, TaiwanC. Patrick YueStanford UniversityStanford, California4199_C000.fmPage xiiiTuesday, November 14, 20065:30 PM4199_C000.fmPage xivTuesday, November 14, 20065:30 PMxvTable of ContentsPreface ...................................................................................................................................... vEditor-in-Chief ...................................................................................................................... viiContributors ........................................................................................................................... ixSECTION I VLSI Technology1 Bipolar Technology B. Gunnar Malm, Jan V. Grahn and Mikael stling........................................................................................................... 1-32 CMOS/BiCMOS Technology Yasuhiro Katsumata, Tatsuya Ohguro, Kazumi Inoh, Eiji Morifuji, Takashi Yoshitomi, Hideki Kimijima, Hideaki Nii, Toyota Morimoto, Hisayo S. Momose, Kuniyoshi Yoshikawa, Hidemi Ishiuchi and Hiroshi Iwai ...................................................................................... 2-13 Silicon-on-Insulator Technology Sorin Cristoloveanu................................................ 3-14 SiGe HBT Technology John D. Cressler ...................................................................... 4-15 Silicon Carbide Technology Philip G. Neudeck .......................................................... 5-16 Passive Components Ashraf Lot............................................................................... 6-17 Power IC Technologies Akio Nakagawa ..................................................................... 7-18 Microelectronics Packaging Bi-Shiou Chiou.............................................................. 8-19 Multichip Module Technologies Victor Boyadzhyan and John Choma, Jr. ............................................................................................................... 9-14199_C000.fmPage xvTuesday, November 14, 20065:30 PMxvi Table of ContentsSECTION II Devices and Their Models10 Bipolar Junction Transistor Circuits David J. Comer and Donald T. Comer............................................................................................................ 10-311 RF Passive IC Components Thomas H. Lee, Maria del Mar Hershenson, Sunderarajan S. Mohan, Kirad Samavati and C. Patrick Yue ............................................... 11-112 CMOS Fabrication Jeff Jessing ................................................................................. 12-113 Analog Circuit Simulation J. Gregory Rollins ........................................................... 13-114 Interconnect Modeling and Simulation Michel S. Nakhla and Ramachandra Achar ....................................................................................................... 14-1SECTION III Low Power Electronics and Design15 System-Level Power Management: An Overview Ali Iranli and Massoud Pedram............................................................................................................ 15-316 Communication-Based Design for Nanoscale SoCs Umit Y. Ogras andRadu Marculescu............................................................................................................ 16-117 Power-Aware Architectural Synthesis Robert P. Dick, Li Shang and Niraj K. Jha............................................................................................... 17-118 Dynamic Voltage Scaling for Low-Power Hard Real-Time SystemsJihong Kim, Flavius Gruian and Dongkun Shin ................................................................. 18-119 Low-Power Microarchitecture Techniques and Compiler Design Techniques Emil Talpes and Diana Marculescu ............................................... 19-120 Architecture and Design Flow Optimizations for Power-Aware FPGAsAman Gayasen and Narayanan Vijaykrishnan................................................................................................ 20-121 Technology Scaling and Low-Power Circuit DesignAli Keshavarzi ................................................................................................................ 21-1SECTION IV Ampliers22 CMOS Amplier Design Harry W. Li, R. Jacob Baker and Donald C. Thelen........................................................................................................... 22-323 Bipolar Junction Transistor Ampliers David J. Comer and Donald T. Comer............................................................................................................ 23-14199_C000.fmPage xviTuesday, November 14, 20065:30 PMTable of Contents xvii24 High-Frequency Ampliers Chris Toumazou and Alison Burdett................................................................................................................ 24-125 Operational Transconductance Ampliers Mohammed Ismail, Seok-Bae Park, Ayman A. Fayed and R.F. Wassenaar.......................................................... 25-1SECTION V Logic Circuits 26 Expressions of Logic Functions Saburo Muroga ..................................................... 26-327 Basic Theory of Logic Functions Saburo Muroga ................................................... 27-128 Simplication of Logic Expressions Saburo Muroga............................................... 28-129 Binary Decision Diagrams Shin-ichi Minato and Saburo Muroga .............................................................................................................. 29-130 Logic Synthesis with AND and OR Gates in Two LevelsSaburo Muroga .............................................................................................................. 30-131 Sequential Networks Saburo Muroga ....................................................................... 31-132 Logic Synthesis with AND and OR Gates in Multi-LevelsYuichi Nakamura and Saburo Muroga.............................................................................. 32-133 Logic Properties of Transistor Circuits Saburo Muroga.......................................... 33-134 Logic Synthesis with NAND (or NOR) Gates in Multi-LevelsSaburo Muroga .............................................................................................................. 34-135 Logic Synthesis with a Minimum Number of Negative GatesSaburo Muroga .............................................................................................................. 35-136 Logic Synthesizer with Optimizations in Two PhasesKo Yoshikawa and Saburo Muroga ................................................................................... 36-137 Logic Synthesizer by the Transduction Method Saburo Muroga ........................... 37-138 Emitter-Coupled Logic Saburo Muroga ................................................................... 38-139 CMOS Saburo Muroga .............................................................................................. 39-140 Pass Transistors Kazuo Yano and Saburo Muroga........................................................ 40-141 Adders Naofumi Takagi, Haruyuki Tago, Charles R. Baughand Saburo Muroga........................................................................................................ 41-142 Multipliers Naofumi Takagi, Charles R. Baugh and Saburo Muroga............................... 42-14199_C000.fmPage xviiTuesday, November 14, 20065:30 PMxviii Table of Contents43 Dividers Naofumi Takagi and Saburo Muroga.............................................................. 43-144 Full-Custom and Semi-Custom Design Saburo Muroga ........................................ 44-145 Programmable Logic Devices Saburo Muroga......................................................... 45-146 Gate Arrays Saburo Muroga ...................................................................................... 46-147 Field-Programmable Gate Arrays Saburo Muroga .................................................. 47-148 Cell-Library Design Approach Saburo Muroga ....................................................... 48-149 Comparison of Different Design Approaches Saburo Muroga............................... 49-1SECTION VI Memory, Registers and System Timing 50 System Timing Baris Taskin, Ivan S. Kourtev and Eby G. Friedman .............................. 50-351 ROM/PROM/EPROM Jen-Sheng Hwang ................................................................. 51-152 SRAM Yuh-Kuang Tseng ............................................................................................ 52-153 Embedded Memory Chung-Yu Wu .......................................................................... 53-154 Flash Memories Rick Shih-Jye Shen, Frank Ruei-Ling Lin, Amy Hsiu-Fen Chou, Evans Ching-Song Yang and Charles Ching-Hsiang Hsu .............................................................................................. 54-155 Dynamic Random Access Memory Kuo-Hsing Cheng............................................. 55-156 Content-Addressable Memory Chi-Sheng Lin and Bin-Da Liu ............................................................................................................. 56-157 Low-Power Memory Circuits Martin Margala........................................................ 57-1SECTION VII Analog Circuits 58 Nyquist-Rate ADC and DAC Bang-Sup Song.......................................................... 58-359 Oversampled Analog-to-Digital and Digital-to-Analog ConvertersJohn W. Fattaruso and Louis A. Williams III...................................................................... 59-160 RF Communication Circuits Michiel Steyaert, Wouter De Cock and Patrick Reynaert .............................................................................. 60-161 PLL Circuits Muh-Tian Shiue and Chorng-kuang Wang............................................... 61-162 Switched-Capacitor Filters Andrea Baschirotto......................................................... 62-14199_C000.fmPage xviiiTuesday, November 14, 20065:30 PMTable of Contents xixSECTION VIII Microprocessor and ASIC 63 Timing and Signal Integrity Analysis Abhijit Dharchoudhury, David Blaauw and Shantanu Ganguly.............................................................................. 63-364 Microprocessor Design Verication Vikram Iyengar............................................... 64-165 Microprocessor Layout Method Tanay Karnik........................................................ 65-166 Architecture Daniel A. Connors and Wen-mei W. Hwu ................................................ 66-167 Logic Synthesis for Field Programmable Gate Array (FPGA) Technology John Lockwood .............................................................. 67-1SECTION IX Testing of Digital Systems 68 Design for Testability and Test Architectures Dimitri Kagaris, Nick Kanopoulos and Spyros Tragoudas ............................................................................ 68-369 Automatic Test Pattern Generation Spyros Tragoudas............................................. 69-170 Built-In Self-Test Dimitri Kagaris ............................................................................. 70-1SECTION X Compound Semiconductor Integrated Circuit Technology 71 Compound Semiconductor Materials Stephen I. Long ........................................... 71-372 Compound Semiconductor Devices for Analog and Digital Circuits Donald B. Estreich .................................................................... 72-173 Compound Semiconductor RF Circuits Donald B. Estreich ................................... 73-174 High-Speed Circuit Design Principles Stephen I. Long........................................... 74-1SECTION XI Design Automation 75 Internet-Based Micro-Electronic Design Automation (IMEDA) FrameworkMoon Jung Chung and Heechul Kim........................................................ 75-376 System-Level Design Alice C. Parker, Yosef Tirat-Gefen and Suhrid A. Wadekar ......................................................................................................... 76-177 Performance Modeling and Analysis Using VHDL and SystemCRobert H. Klenke, Jonathan A. Andrews and James H. Aylor................................................ 77-14199_C000.fmPage xixTuesday, November 14, 20065:30 PMxx Table of Contents78 Embedded Computing Systems and Hardware/Software Co-Design Wayne Wolf ............................................................................................. 78-179 Design Automation Technology RoadmapDonald R. Cottrell .......................................................................................................... 79-1SECTION XII VLSI Signal Processing 80 Computer Arithmetic for VLSI Signal ProcessingEarl E. Swartzlander, Jr. .................................................................................................. 80-581 VLSI Architectures for JPEG 2000 EBCOT: Design Techniques and Challenges Yijun Li and Magdy Bayoumi ............................................................ 81-182 VLSI Architectures for Forward Error-Control DecodersArshad Ahmed, Seok-Jun Lee, Mohammad Mansour and Naresh R. Shanbhag ....................................................................................................... 82-183 An Exploration of Hardware Architectures for Face DetectionT. Theocharides,C.Nicopoulos,K.Irick,N. VijaykrishnanandM.J. Irwin ..................................................................................................................... 83-184 Multidimensional Logarithmic Number System Roberto Muscedere, Vassil S. Dimitrov and Graham A. Jullien.......................................................................... 84-1SECTION XIII Design Languages 85 Languages for Design and Implementation of HardwareZainalabedin Navabi ...................................................................................................... 85-386 System Level Design Languages Shahrzad Mirkhani and Zainalabedin Navabi ...................................................................................................... 86-187 RT Level Hardware Description with VHDL Mahsan Rofouei andZainalabedin Navabi ...................................................................................................... 87-188 Register Transfer Level Hardware Description with VerilogZainalabedin Navabi ...................................................................................................... 88-189 Register-Transfer Level Hardware Description with SystemCShahrzad Mirkhani and Zainalabedin Navabi ................................................................... 89-190 System Verilog Saeed Safari ...................................................................................... 90-191 VHDL-AMS Hardware Description Language Naghmeh Karimi andZainalabedin Navabi ...................................................................................................... 91-14199_C000.fmPage xxTuesday, November 14, 20065:30 PMTable of Contents xxi92 Verication Languages Hamid Shojaei and Zainalabedin Navabi................................ 92-193 ASIC and Custom IC Cell Information RepresentationNaghmeh Karimi and Zainalabedin Navabi ...................................................................... 93-194 Test Languages Shahrzad Mirkhani and Zainalabedin Navabi ...................................... 94-195 Timing Description Languages Naghmeh Karimi and Zainalabedin Navabi ...................................................................................................... 95-196 HDL-Based Tools and Environments Saeed Safari ................................................ 96-1Index......................................................................................................................................I-14199_C000.fmPage xxiTuesday, November 14, 20065:30 PM4199_C000.fmPage xxiiTuesday, November 14, 20065:30 PM Section I -1 0-8493-XXXX-X/04/$0.00+$1.50 2006 by CRC Press LLC Section I VLSI Technology John Choma, Jr. University of Southern California 4199_C001.fmPage 1Friday, November 10, 200610:34 AM 4199_C001.fmPage 2Monday, October 23, 20065:57 PM 1 -3 2006 by CRC Press LLC 1 Bipolar Technology CONTENTS 1.1 Introduction ............................................................... 1- 31.2 Bipolar Process Design .............................................. 1- 5 1.2.1 Figures of Merit ............................................................... 1- 51.2.2 Process Optimization....................................................... 1- 51.2.3 Vertical Structure ............................................................. 1- 61.2.4 Collector Region .............................................................. 1- 71.2.5 Base Region ...................................................................... 1- 81.2.6 Emitter Region ................................................................. 1- 91.2.7 Horizontal Layout ............................................................ 1- 9 1.3 Conventional Bipolar Technology .......................... 1- 11 1.3.1 Junction-Isolated Transistors......................................... 1- 111.3.2 Oxide-Isolated Transistors............................................. 1- 111.3.3 Lateral pnp Transistors .................................................. 1- 13 1.4 High-Performance Bipolar Technology.................. 1- 13 1.4.1 Polysilicon Emitter Contact........................................... 1- 131.4.2 Advanced Device Isolation............................................ 1- 141.4.3 Self-Aligned Structures .................................................. 1- 151.4.4 Single-Poly Structure ..................................................... 1- 151.4.5 Double-Poly Structure ................................................... 1- 17 1.5 Advanced Bipolar Technology................................. 1- 17 1.5.1 Implanted Base............................................................... 1- 191.5.2 Epitaxial Base.................................................................. 1- 191.5.3 Bipolar Integration on SOI ........................................... 1- 201.5.4 Future Trends ................................................................. 1- 21 Acknowledgments ............................................................. 1- 21References .......................................................................... 1- 21 1.1 Introduction The development of a bipolar technology for integrated circuits (ICs) went hand in hand with the steadyimprovement in semiconductor materials and discrete components during the 1950s and 1960s. Conse-quently,siliconbipolartechnologyformedthebasisfortheICmarketduringthe1970s.Ascircuitdimensions shrink, the MOSFET (or MOS) has gradually taken over as the major technological platformfor silicon ICs. The main reasons are the ease of miniaturization and high yield for MOS compared withbipolartechnology.For VLSIcircuitsthelowstandbypowerofcomplementaryMOS(CMOS)gatesisa signicant advantage compared with integrated bipolar circuits. TheevolutionofMOStechnologyhasfollowedthefamousMooreslawthatpredictsasteadydecrease in gate length. Bipolar technology has also beneted from the progress in lithography and iscurrentlyfabricatedusingdeepUVtoolswithfeaturesizescloseto100nm.Thescalinghasledtoa B. Gunnar Malm Royal Institute of Technology Jan V. Grahn Royal Institute of Technology Mikael stling Royal Institute of Technology 4199_C001.fmPage 3Friday, October 27, 20067:13 PM 1 -4 The VLSI Handbook 2006 by CRC Press LLC signicant performance improvement and is further illustrated in Figure 1.1, where the reported gate delaytime for emitter coupled logic (ECL) and current mode logic (CML) circuits is plotted for a 10-year period.Inadditiontothereduceddimensions,theintroductionofSiGeepitaxyforthebaseregionhasfurtherpushed the performance limits. SiGe bipolars are now considered a mature technology and is mainly offeredas a high-speed complement to the low-power MOS in the so-called BiCMOS technology. By adding a smallamountofcarbontotheSiGeepitaxialbase,betterprolecontrolandcompatibilitywithMOSprocessows have been obtained [1]. A mature Si bipolar technology with implanted base at the 0.25 m MOS technology node offers 12 psgatedelayandcanbeusedtorealize10Gb/sICs[2].ThecontinuousperformanceincreaseowingtoreduceddimensionisillustratedinTable1.1,whereseveralgenerationsofacommercialBiCMOStechnologyarecompared[3].Asthedimensionsarereduced,thetraditionallocaloxidationofsilicon(LOCOS) isolation technology is replaced by shallow and deep trenches to increase the packing density,and also to optimize the process ow by getting a more planar structure. As seen in the table, the epitaxialSiGe base markedly improves the device performance at the same technology node.Apart from high-speed performance, the bipolar transistor is recognized by its excellent analog prop-erties which feature high linearity, superior low- and high-frequency noise behavior as well as very hightransconductance[4].SuchpropertiesarehighlydesirableformanyRFapplications,bothfornarrow-bandandbroad-bandcircuits[5].Thehighcurrentdrivecapabilityperunitsiliconareamakesthebipolartransistorsuitableforinput/outputstagesinmanyICdesigns(e.g.,infastSRAMs).Thedis-advantageofbipolartechnologyisthelowtransistordensity,combinedwithlargepowerdissipation. FIGURE 1.1 Reported gate delay time for bipolar ECL and CML circuits versus year. TABLE 1.1 Technology Evolution and Performance Trends of Commercial BiCMOS Technologies Si Implanted Base SiGe EpibaseEmitter lithography ( m) 1.0 0.7 0.5 0.25 0.25 f T (GHz) 13 20 30 40 70 f MAX (GHz)s 60 90 >100Isolation LOCOS STI/DTICMOS gate length ( m) 0.78 0.70 0.42 0.14 0.14Metal layers 3 3 4 5/6 5/6 Source: Modied from Deixler P. et al., IEEE Bipolar/BiCMOS Circuits Technol. Meeting Tech. Dig. ,201, 2002.01995 2000Year200551015202530ECL/CML gate delay time (ps)Si implanted baseSiGe epibaseSiGeC epibase 4199_C001.fmPage 4Monday, October 23, 20065:57 PM Bipolar Technology 1 -5 2006 by CRC Press LLC High-performance bipolar circuits are therefore normally fabricated at a modest integration level (MSI/LSI).By using BiCMOS design, the benets of both MOS and bipolar technology are utilized [6]. One exampleis mixed analog/digital systems, where a high-performance bipolar process is integrated with high-densityCMOS [7]. This technology forms a vital part in several system-on-a-chip designs for telecommunicationand wireless circuits.Inthischapter,abriefoverviewofbipolartechnologyisgivenwithanemphasisontheintegratedsilicon bipolar transistor. The information presented here is based on the assumption that the reader isfamiliarwithbipolardevicefundamentalsandbasicVLSIprocesstechnology.Bipolartransistorsaretreated in detail in well-known textbooks by Ashburn [8] and Roulston [9]. Section 1.2 will outline thegeneralconceptsinbipolarprocessdesignandoptimization.Threegenerationsofintegrateddevicesrepresentingstate-of-the-artbipolartechnologiesforthe1970s,1980s,and1990swillbepresentedinSections 1.3, 1.4, and 1.5, respectively. Finally, some future trends in bipolar technology are outlined. 1.2 Bipolar Process Design Thedesignofabipolarprocessstartswiththespecicationoftheapplicationtargetanditscircuittechnology (digital or analog). This leads to a number of requirements formulated in device parametersand associated gures of merit. These are mutually dependent, and a parameter trade-off must thereforebemade,makingthenalbipolarprocessdesignacompromisebetweenvariousconictingdevicerequirements. 1.2.1 Figures of Merit In the digital bipolar process, the cutoff frequency ( f T ) is a well-known gure of merit for speed. The f T is dened for a common-emitter conguration with its output short circuit when extrapolating the smallsignal current gain to unity. From a circuit perspective, a more adequate gure of merit is the gate delaytime( t d )measuredforaring-oscillatorcircuitcontaininganoddnumberofinverters[10].The t d canbe expressed as a linear combination of the incoming time constants weighted by a factor determined bythe circuit topology (e.g., ECL) [10, 11]. Alternative expressions for t d calculations have been proposed [12].Besidesspeed,powerdissipationcanalsobeacriticalissueindenselypackedbipolardigitalcircuits,resulting in the power-delay product as a gure of merit [13].Intheanalogbipolarprocess,theDCpropertiesofthetransistorareofutmostimportance.Thisinvolves minimum values on common-emitter current gain ( ), Gummel plot linearity ( max / ) break-down voltage (BV CEO ), and early voltage ( V A ). The product V A is often introduced as a gure of meritforthedeviceDCcharacteristics[14].Ratherthan f T ,themaximumoscillationfrequencyispreferredasagureofmeritinhigh-speedanalogdesign,where R B and C BC denotethetotalbaseresistanceandthebase-collectorcapacitance,respectively[15]. Alternativeguresof merit for speed have been proposed in the literature [16, 17]. Analog bipolar circuits are often cruciallydependentonacertainnoiseimmunity,leadingtotheintroductionofthecornerfrequencyandnoisegure as gures of merit for low-frequency and high-frequency noise properties, respectively [18]. 1.2.2 Process Optimization The optimization of the bipolar process is divided between the intrinsic and extrinsic device design. Thiscorresponds to the vertical impurity prole and the horizontal layout of the transistor, respectively [10];seeexampleinFigure1.2,wherethedevicecrosssectionisalsoincluded.Itisclearthattheverticalproleandhorizontallayoutareprimarilydictatedbythegivenprocessandlithographyconstraints,respectively.Figure 1.3 shows a simple owchart of the bipolar design procedure. Starting from the specied DCparametersatagivenbiaspoint,thedopingprolescanbederived.Thehorizontallayoutmustbeadjusted for minimization of the parasitics. A (speed) gure of merit can then be calculated. An implicitrelation is thus obtained between the gure of merit and the processing parameters [11, 19]. In practice,F F R CMAX T B BC= ( ), 8 4199_C001.fmPage 5Monday, October 23, 20065:57 PM 1 -6 The VLSI Handbook 2006 by CRC Press LLC several iterations must be performed in the optimization loop to nd an acceptable compromise betweenthedeviceparameters.Thisprocedureissubstantiallyalleviatedbyone-ortwo-dimensionalprocesssimulations of the device fabrication as well as nite-element physical device simulations of the bipolartransistor[20,21].Foroptimizationofalargenumberofdeviceparameters,thestrategyisbasedonscreeningouttheunimportantfactors,combinedwithastatisticalapproach(e.g.,responsesurfacemethodology) [22, 23]. 1.2.3 Vertical Structure The engineering of the vertical structure involves the design of the collector, base, and emitter impurityproles.Inthisrespect, f T isanadequateparametertooptimize.Foramodernbipolartransistorwithsuppressedparasitics,themaximum f T isusuallydeterminedbytheforwardtransittimeofminoritycarriers through the intrinsic component. The most important f T trade-off is against BV CEO , as stated bythe Johnson limit for silicon transistors [24], the product f T BV CEO cannot exceed 200 GHz V. A moredetailed calculation taking into account realistic doping prole predicts values of >500 GHz V) [25]. In FIGURE 1.2 (a) Layout, (b) cross section, and (c) example of impurity prole throughemitter window for an integrated bipolar transistor (E, emitter; B, base; C, collector).E(a)B CMetalEpnOxide(b)nnepinpB CCollector(c)BaseEmitterDepth (m)Doping concentration (cm3)p1020101910181017101610150 1 2 3 4 5 6n epinn 4199_C001.fmPage 6Monday, October 23, 20065:57 PM Bipolar Technology 1 -7 2006 by CRC Press LLC fact, recent experimental results for high-speed SiGeC bipolar transistors have shown a value of 510 GHz Vfor a 300 GHz f T technology with 1.7 V BV CEO [26]. 1.2.4 Collector Region The vertical n-type collector of the bipolar device in Figure 1.2 consists of two regions below the p-typebasediffusion:alowormoderatelydopedn-typeepitaxial(epi)layer,followedbyahighlydopedn + subcollector. The thickness and doping level of the subcollector are noncritical parameters; a high arsenicor antimony doping density between 10 19 and 10 20 cm 3 is representative, resulting in a sheet resistanceof 2040 /sq. In contrast, the design of the epilayer constitutes a fundamental topic in bipolar processoptimization.To rst-order, the collector doping in the epilayer is determined by the operation point (more specif-ically,thecollectorcurrentdensity)ofthecomponent(seeFigure1.3).Anormalconditionistohavethe operation point corresponding to maximum f T , which typically means a collector current density oftheorderof24 10 4 A/cm 2 .Aswillberecognizedlater,bipolarscalingresultsinincreasedcollectorcurrentdensities. Aboveacertaincurrentlevel,therewillbearapidroll-offincurrentgainandcutofffrequency.Thisisduetohigh-currenteffects,primarilythebasepushoutorKirkeffect,leadingtoasteepincreaseintheforwardtransittime[27].Sincethecriticalcurrentvalueisproportionaltothecollectordoping[28],aminimumimpurityconcentrationfortheepilayerisrequired,thusavoiding f T degradation(typicallyaround10 17 cm 3 forahigh-speeddevice).Usually,theepilayerisdopedonlyintheintrinsicstructurebyaselectivelyimplantedcollector(SIC)procedure[29]. Anexampleofsuchadopingprolefromanadvanced0.25 mBiCMOStechnologyisseeninFigure1.4.Suchacollectordesign permits an improved control over the base-collector junction, that is, shorter base width as wellas suppressed Kirk effect. The high collector doping concentration, however, may be a concern for both C BC and BV CEO . The latter value will therefore often set a higher limit on the collector doping value.The SIC technology provides a simple way of creating a high-BV CEO device by masking the implanta-tion. The reduced collector doping in the SIC-free device will also reduce the pinch-base resistance and C BC , which is in favor of high f max [3]. FIGURE 1.3 Generic bipolar device optimization owchart.StartfT, fmax, dJICBVCEORCparasiticsFeedbackEmitter widthx lengthCircuit topologyweightingHORIZONTALLAYOUTVERTICALPROFILECIRCUITREQUIREMENTSEpithicknessNC, VANB 4199_C001.fmPage 7Monday, October 23, 20065:57 PM 1 -8 The VLSI Handbook 2006 by CRC Press LLC Thepreferredproletoachieveagoodcompromisebetweenatoohigheldatthebase-collectorjunction and suppression of the Kirk effect at high current densities is obtained by a retrograde collectorprole [30]. For this prole the SIC implantation energy is chosen to obtain a low impurity concentrationnear the base-collector junction and then increasing toward the subcollector.The thickness of the epilayer exhibits large variations among different device designs, extending severalmicrometers in depth for analog bipolar components, whereas a high-speed digital design typically hasan epilayer thickness around 1 m or below, thus reducing the total collector resistance. As a result, thetransistor breakdown voltage is sometimes determined by reach-through breakdown (i.e., full depletionof penetration of the epicollector). The thickness of the collector layer can therefore be used as a parameterin determining BVCEO, which in turn is traded off against fT.In cases where fmax is of interest, the collector design must be carefully taken into account. ComparedwithfT,theoptimumfmaxisfoundforthickerandlessdopedcollectorepilayers[32,33].Theverticalcollector design will therefore, to a large extent, determine the trade-off between fT and fmax.1.2.5 Base RegionThewidthandpeakconcentrationofthebaseprolearetwoofthemostfundamentalparametersinvertical prole design. In a conventional Si bipolar process the base width is limited by the implantationenergyandtosomeextentthecollectordoping,sinceanimplantedprolewillhaveaGaussiantailtoward the collector. The base width WB is normally in the range 0.11 m, whereas a typical base peakconcentration lies between 1017 and 1018 cm3. In contrast to this, base widths of get_proc_type());if(/*1st_line*/string_temp=="mixed"){SC_THREAD(mixed_behav); //only make the relevant behavior a thread!hardware_compute=new refined_computation("name",proc_num); //may need to add an argument this class...}class rng_comp_tb : public sc_foreign_module{public:sc_in start;sc_out done;rng_comp_tb(sc_module_name nm, const char* hdl_name) : sc_foreign_module(nm, hdl_name), start("start"), done("done"){ //cout '0');elsif ld = '1' thenq_t := d;elsif l_r = '1' thenq_t := q_t (2 downto 0) & s_in ;elseq_t := s_in & q_t (3 downto 1);end if;end if;q