vlsi - vhdl hi ranjith

8/6/2019 VLSI - VHDL hi Ranjith

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VHDL

E-mail: [email protected],

By

Jayasanthi Ranjith - PhD Scholar

Anna UniversityCoimbatore


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VLSI!!!

1. Digital VLSI Design

2. Analog VLSI Design

3. Mixed signal VLSI Design


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WHY VLSI and HOW?


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DESIGN DOMAINS

STRUCTURAL DOMAIN

BEHAVIOURAL DOMAIN

PHYSICAL DOMAIN


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VHDL models

Structuraldomain

Behavioraldomain

Physical domain

Domains of Description

Gajskis Y-Chart

Level ofabstraction

high level ofabstraction

low level ofabstraction


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Domains and Levels of Modeling

Functional/BehavioralStructural

Geometric/physical

Algorithm(behavioral)

Register-TransferLanguage

Boolean Equation

Differential Equation


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Domains and Levels of Modeling

FunctionalStructural

Geometric

Processor

Register-Transfer

Gate

Transistor


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Basic Design Methodology

Requirements

SimulateRTL Model

Gate-levelModel

Synthesize

Simulate Test Bench

ASIC or FPGA Place & Route

TimingModel Simulate


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VHDL History

U.S. Department of Defense initiated in 80s

later transferred to the IEEE

Initial objective was modeling only and thusonly a simulator was envisaged

Subsequently tools for VHDL synthesis weredeveloped


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VHDL

V-VHSIC-Very High Speed Integrated CircuitHDL-Hardware Description Language

VHDL is a programming language that allows

one to model and develop complex digitalsystems in a dynamic environment.

Allows you to designate in/out ports (bits) andspecify behavior of the system.

What is VHDL?


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VHDL Benefits

AbstractionModularity

Concurrency

Hierarchy


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Abstraction

Abstraction is hiding of details

Differentiate between essential and nonessential

information only the essential information is considered,

nonessential information is left out


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LEVELS OF ABSTRACTION


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Modularity

Modularity allows the partitioning of bigfunctional blocks into smaller units and to

group closely related parts in self-containedsub blocks, so called modules.

This way, a complex system can be divided into

manageable subsystems. The guidelines forpartitioning can differ from design to design.


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Concurrency

process 1 process 2 process n


17/77Hierarchy

S1

S2

C4

S3

S13

S14

S4

S5

C5

C1

S6

C6

S7

S8

S9

S10

C7

C2

S11

S12

C3

C0

Hierarchy allows the building of a design outof modules which themselves may be builtout of (sub-)modules.


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VHDL forFPGA/ASIC


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VHDL for FPGA

In the first step, Boolean equations arederived from the VHDL description, no matter,

whether an ASIC or a FPGA is the targettechnology.

This Boolean code has to be partitioned intothe configurable logic blocks (CLB) of the

FPGA. This is more difficult than the mappingonto an ASIC library.

Another big problem is the routing of the CLBsas the available resources for interconnections

are the bottleneck of current FPGAs.


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VHDL for ASIC

VHDL is used mainly for the development ofApplication Specific Integrated Cicuits (ASICs).

Tools for the automatic transformation ofVHDL code into a gate-level netlist weredeveloped already

Eg-Xilinx

This transformation is called synthesis and is anintegral part of current design flows.


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Library and package

library ieee;

use ieee.std-logic-1164. all ; invoke the std-logic-1164 package from the ieee

library.

The package and library allow us to add additional

types, operators, functions, etc. to VHDL.

Standard: bit

std-logic-1164:Multivalued logic/Xs and 3 state

buses All: all defns in package are to be used


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Modeling Styles

Dataflow or RTL (Register TransferLanguage) Modeling

Structural or gate level modeling Behavioral modeling


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Program structure

Entity name is

port(A1,A2: IN std_logic;

x,y: OUT std_logic);End name;

Architecture arch of name is

Begin

-----

-----

end arch;


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Half adder


25/77Data flow Modeling Eg.

It uses statements that defines the

actual flow of dataEntity hadd isport(A1,A2: IN std_logic;

Sum, Cout: OUT std_logic);

End hadd;architecture HA_CONCURRENT of hadd is

begin

SUM


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Behavioral Modeling

It describes the algorithm performed by themodule

It contains

process statements , each containing sequential statements, including

signal assignment statements and

wait statements


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Behavioral Modeling Eg.

Entity hadd is

port(A1,A2: IN std_logic;

Sum, Cout: OUT std_logic);End hadd;

Architecture a of hadd is

Begin

process(A1,A2)

BeginSum


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Structural Modeling-Components

Structuralarchitecture implements the module as a composition of

subsystems(Signals) + (Component instances + Port maps)

contains signal declarations, for internal interconnections

the entity ports are also treated as signals component instances instances of previously

declared entity/architecture pairs

port maps in component instances

connect signals to component ports


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Structural modeling of Half adder

architecture HA_STRUCTURE of HADD is

component XOR2

port (X, Y: in BIT; Z: out BIT);end component;

component AND2

port (L, M: in BIT; N: out BIT);

end component;

begin

X1: XOR2 port map (A, B, SUM);

A1: AND2 port map (A, B, CARRY);

end HA_STRUCTURE;


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Mixed modeling

Mixed Behavior and Structure

An architecture can contain both behavioral and

structural parts process statements and component instances

collectively called concurrent statements

processes can read and assign to signals

Example: register-transfer-level (RTL) Model data path described structurally

control section described behaviorally


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Behavioral Vs Dataflow

Procedural

(textual order => executionorder)

Sequential statements

Control constructs alternormal sequential flow

Called Behavioraldescription in VHDL

Non-procedural

(textual order NOT =>execution order)

Concurrent statements

Data flow (or rather datadependency restrictsconcurrency)

Called Data flowdescription in VHDL


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VHDL is an Object Oriented Programming(OOP) Language. Objects can have values,attributes and methods. We will primarily usethe following VHDL data objects:

Signals

Constants

Variables

VHDL Data Objects


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Variables

Variables are data objects in which the value ofthe object can be changed. This change occursinstantaneously.

Variables can only be defined within aprocessdeclarationblock.

They cannot be implemented in hardware.


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Constants

Constants are data objects in which the value ofthe object cannot be changed.

They are defined within an architecture or

process declaration block.

They cannot be implemented in hardware.


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Data types


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Operators

The six logical operators are

and or nand nor xor not

The relational operators are= /= < >=

Adding Operators are

+ - &

Multiplying Operators are

* / mod rem

Miscellaneous Operators are

abs **


38/77Design units

Entity declaration

Architecture body

Configuration declaration

Package declaration

Package body


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Entity Declaration

entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;

q0, q1, q2, q3 : out bit );end reg4;

entity name port names port mode (direction)

port typereserved words

punctuation

Specifies the name of the entity being

modeled and lists the set of I/O interfaceports.


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I/O port modes

in: signal values are read-only out: signal values are write-only

multiple drivers

Buffer: output signal values may be read as well

inout:1.In order to model busses, wheremultiple units have access to the same

data lines

2. Bidirectional port


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ENTITY Eg.

EntityHAisport ( A,B : in bit;

SUM,CARRY : out bit );end HA;


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Architecture

Describes an implementation of an entity

may be several per entity

As a set of interconnected components

As a set of concurrent assignment statements

As a set of sequential assignment statements

Any combination of the above three.


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Architecture Eg.

architecture HA_CONCURRENT of HA isbegin

SUM


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Configuration

A configuration declaration is used to select oneof the possibly many architecture bodies that anentity may have

we also have to choose between various alternative

entities.

suppose an alternate architecture of half adder isavailable or the component is defined in the library as

HALF_ADD.

In such case, we need to use a configuration

statement in the declaration zone i.e. after componentdeclaration and before begin


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Configuration Eg.


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entity HA is

port(a, b :in BIT; s, c: out BIT);

end HA; architecture dataflow of HA is

begin

..

end dataflow;

architecture struct of HA is

begin

end struct;

Configuration Eg.


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Configuration Eg.

entity HALF_ADD isport(sum, cy: out std_logic; x, y: in std_logic;);

end HALF_ADD;

architecture DF of HALF_ADD is

beginsum


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Configuration MYCONFIG of FA is

For structFor H1: HA use entity HA (dataflow); end for;

For H2: HA use entity COMP_LIB.HALF_ADD(DF)

port map (x => a, y => b, sum => s, cy => c);end for;

For ORG: OR2 use entity OR2 (dataflow);

end for;

End for;

End MYCONFIG;

Configuration Eg.


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Package Declaration & Body

A package declaration is used to store a set of

common declarations like components,types, procedures, and functions.

These declarations can then be imported intoother design units

A package body contains the definitions of

subprograms declared in a package declaration.


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Package Declaration Eg.

package EXAMPLE_PACK is

type SUMMER is (MAY, JUN, JUL, AUG, SEP);

component D_FLIP_FLOPport (D, CK: in BIT; Q, QBAR: out BIT);

end component;

constant PIN2PIN_DELAY: TIME := 125 ns;

function INT2BIT_VEC (INT_VALUE:INTEGER)

return BIT_VECTOR;

end EXAMPLE_PACK;


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Package Body Eg.

package body EXAMPLE_PACK is

function INT2BIT_VEC (INT_VALUE:INTEGER)

return BIT_VECTOR is

begin--Behavior of function described here.

end INT2BIT_VEC;

end EXAMPLE_PACK;


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GENERATE

The generate statement can be used for

replicating any set of concurrentstatements/Multiple copies of a component

E.g. Iterative networks like generating an n-bit

ripple-counter from n T flip-flops, n-bit shiftregister from n D flip-flops, word-adder from a16 bit-adders etc.

The statement has two forms namelyfor generate and ifgenerate.


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Byte adder


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Byte adder using forgenerate

architecture structural of BA is

component FA

port(x,y,ci:in std_logic;sum,co:out std_logic);end component;

signal c:std_logic_vector(6 downto 0);

begin

FA0 :FA port map(a(0),b(0),cin,s(0),c(0));FAmid:for i in 1 to 6 generate

FAm:FA port map(a(i),b(i),c(i-1),s(i),c(i));

end generate;

FA7 :FA port map(a(7),b(7),c(6),s(7),cout);end structral;


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Byte adder using ifgenerate

FA_GEN: for i in 0 to 7 generate

If i = 0 generate

FA0:FA port map(a(i),b(i), cin,s (i),c(i));

end generate;

If i >0 and I


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Behavioral modeling

In behavioral modeling, sequential

blocks like process, procedures andfunctions are heavily used


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Process

Architecture a of b is

BeginProcess(sensitivity list)

.

.

End processEnd a;


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Procedures

The statements within a procedure getexecuted sequentially.

A procedure can not return a value in its namebut it can return any number of valuesthrough its out parameters.

The formal parameters of a procedure can be

constants, variables or signals and theirmodes can be in, out, or inout.


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Function

The statements within a function body getexecuted sequentially.

A function returns a single value in its name. The formal parameters of a function

can have only the input mode.

By default, the out and inout parameters are

assumed to be variable objects and the inparameters are assumed to be constants.


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CASE STATEMENT

The syntax of a case statement is asfollows.case EXPRESSION iswhen value1 => STATEMENT(S);

when value2 => STATEMENT(S);- - - - - - - - - - - - - - - - -when others => STATEMENT(S);end case;


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entity GetRate is

port(HOUR:in integer;RATE:out real);

end GetRate;architecture DATAFLOW of GetRate is

begin

process(HOUR)

begin

Case HOUR isWhen 0|23 => RATE RATE RATE


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Simple loop

Simple loop: The loop statement is usedto repeatedly execute a set of sequential

statements

This is an endless loop and therefore,

next, exit or return statement

should be included.

Syntax 1 (Simple loop):

[LABEL]: loop

Statement(s);

End loop [LABEL];


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While loop

While loop: The statement body isrepeatedly executed as long as the

CONDITION is true.

However, an additional exit path may beprovided through an exit statement.

Syntax 2 (While loop):

[LABEL]: while CONDITION loop

Statement(s);

End loop [LABEL];


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FOR Loop

Syntax[label]: for LOOP_VAR_NAME inRANGE loopStatement(s);End loop [LABEL];


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OTHER STATEMENTS

Other statements are

Next Exit

Null

Assert etc.


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TEST BENCH

test bench is a model that is used to verify thecorrectness of a hardware model.

A test bench has three main purposes:


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TEST BENCH SYNTAX

entity TEST_BENCH is

end;

architecture TB_BEHAVIOR of TEST_BENCH is

component ENTITY_UNDER_TESTport ( list-of-ports-their-types-and-modes);

end component;

Local-signal-declarations;

begin

Generate-waveforms-using-behavioral-constructs;Apply-to-entity-under-test;

EUT: ENTITY_UNDER_TEST port map (port-associations);

Monitor-values-and-compare-with-expected-values;

end TB_BEHAVIOR;


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Waveform Generation

process

constant OFF_PERIOD: TIME := 30 ns;

constant ON_FERIOD : TIME := 20 ns;begin

wait for OFF_PERIOD;

D_CLK


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EXAMPLES


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Full adder


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FULL ADDER

entity fulladder is

port(x,y,cin:in bit;cout,sum:out bit);

end fulladder;architecture equations of fulladder is

begin

sum


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MULTIPLEXER

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY mux IS

PORT (i0, i1, i2, i3, a, b: IN std_logic;q : OUT std_logic);

END mux;

ARCHITECTURE better OF mux IS

BEGIN

q


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CLOCK GENERATION

library ieee;

use IEEE.std_logic_1164.all;

entity clk is

port (ck:buffer bit);end clk;

architecture clk1 of clk is

begin

process

beginck


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T FLIPFLOP

entity tff is

port(t,c:in bit;q:inout bit;qn:inout bit:='1');

end tff;

architecture tff1 of tff is

begin

process(c)

begin

if c='0' then

if t='0' then

q


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Simulation Tool- ModelSim

B i L i G t


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Basic Logic Gates

DRIVERlibrary ieee;

use ieee.std_logic_1164.all;

----------------------------------------

entity Driver is

port( x: in std_logic;

F: out std_logic

);

end Driver;

----------------------------------------

architecture behv1 of Driver is

beginprocess(x)

begin

-- compare to truth table

if (x='1') then

F

vlsi - vhdl hi ranjith

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