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FINAL YEAR IEEE PROJECTS TITLES 2014-2015(DIGITAL SIGNAL PROCESSING)
S.NoProject CodeTITLEYEAR
No 1ECSV001Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line.2014-15
No 2ECSV002A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler2014-15
No 3ECSV003Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache2014-15
No 4ECSV004A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS2014-15
No 5ECSV005A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme2014-15
No 6ECSV006A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits2014-15
No 7ECSV007A Low Complexity-High Throughput QC-LDPC Encoder2014-15
No 8ECSV008A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures2014-15
No 9ECSV009A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain2014-15
No 10ECSV010A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture2014-15
No 11ECSV011A Synergetic Use of Bloom Filters for Error Detection and Correction 2014-15
No 12ECSV012Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC2014-15
No 13ECSV013Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms2014-15
No 14ECSV014An 8 bit 0.30.8 V 0.240 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS2014-15
No 15ECSV015An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability2014-15
No 16ECSV016Analysis and Characterization of Capacitance Variation Using Capacitance Measurement Array2014-15
No 17ECSV017Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit2014-15
No 18ECSV018Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter2014-15
No 19ECSV019Compensating Modeling Overlay Errors Using the Weighted Least-Squares Estimation2014-15
No 20ECSV020Compensating Modeling Overlay Errors Using the Weighted Least-Squares Estimation2014-15
No 21ECSV021Demonstrating HWSW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane2014-15
No 22ECSV022Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging2014-15
No 23ECSV023Design Techniques to Improve Blocker Tolerance of Continuous-Time __ ADCs2014-15
No 24ECSV024Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor2014-15
No 25ECSV025Efficient Hardware Architecture of T Pairing Accelerator Over Characteristic Three2014-15
No 26ECSV026Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects2014-15
No 27ECSV027Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems2014-15
No 28ECSV028Energy-Efficient Soft-Input Soft-Output Signal Detector for Iterative MIMO Receivers2014-15
No 29ECSV029Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories2014-15
No 30ECSV030Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs2014-15
No 31ECSV031Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study2014-15
No 32ECSV032Fast Radix-10 Multiplication Using Redundant BCD Codes2014-15
No 33ECSV033Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint2014-15
No 34ECSV034Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 1, 2n 1, 2n}2014-15
No 35ECSV035Fault Tolerant Parallel Filters Based on Error Correction Codes2014-15
No 36ECSV036Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis2014-15
No 37ECSV037Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications2014-15
No 38ECSV038Functional Constraint Extraction From Register Transfer Level for ATPG2014-15
No 39ECSV039Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems2014-15
No 40ECSV040Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs2014-15
No 41ECSV041Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution2014-15
No 42ECSV042Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding2014-15
No 43ECSV043Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding2014-15
No 44ECSV044Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection2014-15
No 45ECSV045Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes2014-15
No 46ECSV046Novel Structures for Cyclic Convolution Using Improved First-Order Moment Algorithm2014-15
No 47ECSV047Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms2014-15
No 48ECSV048Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count2014-15
No 49ECSV049Protein Alignment Systolic Array Throughput Optimization2014-15
No 50ECSV050Quaternary Logic Lookup Table in Standard CMOS2014-15
No 51ECSV051Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line.2014-15
No 52ECSV052A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler2014-15
CONTACT: PRAVEEN KUMAR. L (+91 9626110101,+91 9751442511)MAIL ID: [email protected], [email protected]