week 4 - university of waterloopami.uwaterloo.ca/~basir/ece124/week4-1.pdf · ece124 digital...

WEEK 4.1

ECE124 Digital Circuits and Systems


Combina=onal circuits

  A combinatorial circuit is one that consists of logic gates with outputs that are determined en=rely by the present value of the inputs.

  Combinatorial circuits might be 2‐level logic (SOP,POS) or mul=‐level.

  Black box illustra=on (there is no storage elements inside the box):

  Two opera=ons we might want to perform:   Analysis – given what is in the box, what func:on(s) does it perform?   Design – given func:ons to perform, what do we need in the box?

o1

o2

om

i1i2i3

in

?


Analysis (for combina=onal circuits)

  Determines the func=on performed by a circuit.

  Starts with a circuit, and the result of analysis are the logic func=ons.

  Steps (assuming we have inputs, outputs and gates iden=fied):

  Label intermediate logic gate outputs star:ng from the inputs with arbitrary signal names.

  Determine the Boolean func=ons for each gate output star:ng from the inputs.   Con=nue, moving towards the outputs un=l we have expressions for the outputs

in terms of the inputs.

  We introduce extra signals and work our way through the circuit from inputs to the outputs.

Analysis example (1)

abc

abc

a

ab

bc

c

f1

f2

T2

T1

T3


  Intermediate signals introduced as required (T1, T2, T3)

  This bunch of logic equa=ons does the trick, but we can subs=tute out the temporary signals to get an input‐output rela=onship.

Analysis example (2)

  The input‐output rela=onship (removing temporary signals):


Design (for combina=onal circuits)

  Opposite of analysis… Given func=ons to be performed, implement a combinatorial circuit that performs the func=ons.

  Steps:

  From specifica=ons, determine number of inputs and outputs.

  Derive the func=ons, or truth tables, that define input‐output rela=onship.

  Derive simplified Boolean func=ons.

  Draw the circuit diagram and verify correctness.

  Note: We might end up with a 2‐level circuit (SOP,POS) or possibly a mul=‐level circuit implementa=on.


Design example (1)

1

1

0100

x

1

00

01

cdab

0

0

0

11 10

11

10

0 1

0 1

x x

x x

x

z

1

1

0100

x

1

00

01

cdab

0

0

0

11 10

11

10

1 0

1 0

x x

x x

x

y

0

0

0100

x

1

00

01

cdab

1

1

0

11 10

11

10

1 1

0 0

x x

x x

x

x

0

1

0100

x

0

00

01

cdab

1

0

1

11 10

11

10

0 0

1 1

x x

x x

x

w


  Consider the following 4‐input (a,b,c,d), 4‐output (w,x,y,z) circuit specified via K‐Maps.

Design example (2)

  We could just implement the SOP for each function individually. Could also (maybe) try and see if some product terms can be shared.

  Could also try to factor/decompose functions to find shared equations…


Design example (3)

d

c

b

z

ycd

(c+d)'c+d

b(c+d)

aw

x


  Mul=level factored circuit requires 9 gates and 17 gate inputs (inverters connected directly at inputs are free).   2‐level implementa=on requires 10 gates and 23 gate inputs.

Combinatorial circuits (arithme=c)

  Some combina=onal circuits are very common and it is worth looking at them in more detail.

  One par=cular class of very useful circuits are arithme:c circuits; i.e., those circuits used for performing opera=ons such as: addi:on, subtrac:on, mul:plica:on, etc. of binary numbers.


Binary half‐adder circuit

  Basic definition of addition is to take two bits, and add them, producing a sum and a carry out.   The circuit that produces these two outputs is called a binary half-adder.



Binary half‐adder implementa=on

  We can draw different implementations of a binary half-adder (depends on availability of XOR gates):

sum

cout

xy

cout

sum

xy

!xy

x!y

Binary full‐adders

  Most commonly, we are interested in adding n‐bit numbers. Therefore, we need to be able to also handle a carry in signal.   The circuit implemen=ng these two func=ons is known as a binary full‐adder.


Sum: odd #1’s EXOR


Binary full‐adder implementa=on

  We can draw different implementations of binary full adders.

  Note that the 2-nd implementation uses 2 half-adders to implement the full-adder.

y sum

cout

x

cin sum

cout

xy

cin

xy

xcin

ycin


Ripple adders for n‐bit addi=on

  Can build n-bit adders to add A = (an-1 an-2 … a1 a0) and B = (bn-1 bn-2 … b1 b0) simply by linking 1-bit full adders together.

  We might want to think about the performance (delay) of this adder circuit…

FA FAFAFA


Ripple adder performance (1)

  Recall that we spoke about combinational logic gates having some delay (i.e., a change in an input does not cause the output to change immediately)… Assume that a logic gate has delay of “1 unit”.

  Assume that each of our full-adders is built from half-adders.

  We can therefore trace/identify the longest combinatorial path in the circuit.

  This is the path that determines the performance of the circuit;

  The delay of the longest path tells us the minimum amount of time that we need to wait for the output to be correct.

FA FAFAFA

sum

cout

xy

cin

Issue of Ripple Adder

  Carry propaga=on is the main issue in an N‐bit ripple adder   A faster adder needs to address the serial propaga=on of the carry bit   Let’s re‐examine the equa=on for full adders


Ripple adder performance (2)

  For the ripple adder, it is possible that a change in the LSB of A or B (i.e., a0 or b0) will cause a change in the carry out of the MSB (i.e., cn)

  We can identify the longest path:

sum

cout

xy

cin

FA FAFAFA

  We can compute the longest path for an n-bit ripple adder as follows:

Delay is f(x,y) only; performed at the same time for all stages.

For Stage FA0

For Stages FA1 FA2,……

4‐bit Ripple Adder using Full Adder

Full Adder

A B

Cin Cout

S

S0

A0 B0

Full Adder

A B

Cin Cout

S

S1

A1 B1

Full Adder

A B

Cin Cout

S

S2

A2 B2

Full Adder

A B

Cin Cout

S

S3

A3 B3

Carry

Full Adder Propaga=on Delay

S0

A0 B0

Carry Cin

1st Stage Critical Path = 3 gate delays = DXOR+DAND+DOR

Full Adder Propaga=on Delay

S0

A0 B0

Cin

S1

A1 B1

2nd Stage Critical Path = 2 gate delays = DAND+DOR

(Since 1st Critical path > DXOR)

1st Stage Critical Path = 3 gate delays = DXOR+DAND+DOR

Issue of 4‐bit Ripple Adder

Critical Path = DXOR+4*(DAND+DOR) for 4-bit ripple adder (9 gate levels) For an N-bit ripple adder Critical Path Delay ~ 2(N-1)+3 = (2N+1) Gate delays

S0

A0 B0

Cin

S1

A1 B1

S2

A2 B2

S3

A3 B3

Carry


Carry look‐ahead adders

s(i)

c(i+1)

x(i)y(i)

c(i) g(i)

p(i)

  Ripple adders can be very slow for large numbers of bits. If we can calculate the carry ins faster, then we can build a faster adder.

  Consider the i-th bit of the adder, and identify two signals, namely the propagate pi and generate gi:

  Write the carry out ci+1 in terms of the pi and gi signals instead.


Carries wri`en as func=ons of the propagates and generates

  We can consider writing all the carry outs in terms of the pi and gi signals, but substitute previously calculated carries as we go…

  We have written the carries in terms of values all computed when the inputs are applied to the circuit:

  All pi and gi are computed after 1 gate delay.   All ci are then computed after 2 more gate delays, since the are 2-level SOP in

terms of pi and gi.

s(i)

c(i+1)

x(i)y(i)

c(i) g(i)

p(i)

This should be g2

Carry look‐ahead performance

  If we use carry lookahead to generate all of the carries, then our adder will have a delay of 3 units of gate delay to get cn.

  What is the penalty to be paid?   The carry lookahead circuit is 2‐level logic (SOP) and we should see that higher

numbered carries require more AND gates as well as AND/OR gates with a large number of inputs.

  It becomes imprac=cal (can’t get AND/OR gates with large numbers of inputs).   It becomes expensive in terms of the number of logic gates required.

  So, we get be`er performance, but we pay for it in terms of area and cost of the circuit implementa=on.



Combina=ons of ripple and carry look‐ahead circuits

  We can get something better than a ripple adder, but not as good as full carry lookahead by cascading smaller carry lookahead adders…

  E.g., consider a 16-bit adder composed of 4, 4-bit carry lookahead adders.

4-CLA 4-CLA4-CLA4-CLA

  Performance will be 3+2+2+2 = 9 units of gate delay to get c16 (notice a ripple adder would have required 2(16)+1 = 33 units of delay.


Trade‐off – area vs. delay

8-bit adder design

type delay cost max gate

ripple (8, 1-bit FA) 17 gates 120 2

4, 2-bit CLA 7 gates 140 3



  Demonstration of Area vs. Delay for different ways of making an 8-bit adder.   Note: delay is assumed to be time to generate c8   Note: cost is calculated as #gates+#gate inputs.   Note: max gate means #inputs to the largest gate required

0

50

100

150

200

250

300

350

ripple (8,1-bit FA)

4, 2-bitCLA

2, 4-bitCLA

1, 8-bitCLA

DelayArea

week 4 - university of waterloopami.uwaterloo.ca/~basir/ece124/week4-1.pdf · ece124 digital...

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