week 4 - university of waterloopami.uwaterloo.ca/~basir/ece124/week4-2.pdf · overﬂow detecon...

WEEK 4.2

ECE124 Digital Circuits and Systems


Prac;cal comments

  There is another point in generating carry look-ahead for high numbers of bits…

  If we don’t have a large enough gate, we might have to decompose the gate into smaller gates; e.g., say we need a 5-input AND gate, but only have 2-input AND gate…

  We might need to do something like:

  And what we thought required 1 gate delay is actually 3 gate delays.

RECALL EXOR AS Controlled Inverter (Complement)

X Y f 0 0 0 0 1 1 1 0 1 1 1 0


WE OBSERVE THAT IF X=0, THEN f=y, IF X=1, THEN f=y’.

Binary adders/subtractors and an ALU symbol

  Subtrac;on is fairly straighNorward if we assume the numbers are 2s complement.   Recall: subtrac;on is performed by taking the 2s complement of the subtrahend

and performing addi;on.   Take any adder circuit. We can make it a combina;on adder and subtrac;on circuit by

adding XOR gates and a add/sub control signal.


5

  Desirable to use same hardware for both opera;ons   2’s complement addi;on for subtrac;on

  Overflow   Addi;on/subtrac;on of 2 n bit numbers may produce n+1 bit output   Problem if fixed # of bits (n) are allocated for input and output   Must detect its occurrence

d=101-010 d=101+2scom(010) d=101+1scomp(010)+1 d=101+101+1 d=1011 d=3 M=0, add

M=1, Subtract

M=1, XOR=Complement M=0, XOR=Pass through

ignore

Adder/Subtractor

Overflow detec;on

  When two n-bit binary numbers A and B are added together and the sum requires (n+1) bits, we say an overflow has occurred.   True to either signed or unsigned arithmetic.

  Overflow is a problem for digital computation since we are limited in the number of bits available to represent a number.

  Detection of overflow depends on whether the numbers are signed or unsigned.


Overflow detec;on – unsigned numbers

  When adding unsigned numbers, an overflow is detected if there is a carry out from the MSB.


Overflow detec;on – signed numbers (1)

  When adding unsigned numbers, an overflow is detected if there is a carry out from the MSB.   No possibility of overflow if numbers are opposite in sign, since result will be

smaller than the larger of the two numbers.

  Examples of overflow: assume 8‐bits available (‐128 to +127); carry into and out of the MSB shown.



Overflow detec;on – signed numbers (2)

  No;ce that in both of the previous cases, the sign bit (the MSB) indicates a nega;ve result when it should have been a posi;ve result.

  We can detect the overflow by examining the carry in and carry out of the MSB. If not equal, then there is overflow:

  The circuit:   If numbers are unsigned C=1 means overflow, otherwise result good.   If numbers are signed, then V=1 means overflow, otherwise result good.

FA FAFA(MSB)

C

V


Binary mul;pliers

  Mul;plica;on of binary numbers works exactly like in decimal:

  Since numbers are binary, the mul;plica;on of a_i (mul;plier bit) with B can be done with AND.   When a_i = 0, we add 0 to the par;al product.   When a_i = 1, we add the mul;plicand to the par;al product.

  To mul;ply 2, n‐bit numbers we need 2n‐bit output.


Example of binary mul;plica;on

  Simple example ; 7 x 6 = 42


Circuit for a binary array mul;plier

ajbi

FA

ppi

  Since multiplication is just ANDs and addition, we can make an array multiplier with AND gates and 1-bit FAs.

  Example: An array multiplier for 4-bit numbers (8-bit output):

0

0

0

0

b2 b0b1b3

a0

a1

a2

a3

a0b3a0b2a0b1a0b0

a1b3a1b2a1b1a1b0

a2b3a2b2a2b1a2b0

Combina;onal circuits (other useful combina;onal blocks)

  Many types of useful combinational circuits such as comparators, encoders and decoders, multiplexers and demultiplexers, and so on.

  We should be familiar with such blocks since they occur so often in practice.


Magnitude comparators

  Consider that we have two n‐bit unsigned binary numbers A and B.

  We want a circuit that compares the two numbers and produces outputs indica;ng when:

  A = B.   A < B.   A > B.

  We need an algorithm for comparing numbers of n‐bits. From the algorithm, we can build a circuit.

  How do we compare two numbers… A=an an‐1 a1 a0 and B=bn bn‐1 b1 b0 ?

  Consider comparing bits in pairs from the MSB towards the LSB.


Magnitude comparators – equality of bits

  The i‐th bits of A and B are equal if Ai = Bi .

  Introduce the new signals ei to detect this equality (this is an NXOR, which we can write as an SOP):


  Detec;on of equality (A=B) is now easy – two numbers A and B are equal if all their bits are equal (take the AND of the ei signals):

Magnitude comparators – inequality of bits

  Think of how we compare two n‐digit numbers A and B…

  Let i = n ini;ally (the MSB).   If ai > bi, then A > B and stop.   If ai < bi then B > A and stop.   If ai = bi, let i = i – 1 (go to the next lower bit) and repeat.   Stop once i = 0 (the LSB) and all bits considered.

  We can write this algorithm as a formula for (A>B) and (A<B):


A= 1 0 0 1 1 1 1 B= 1 1 0 1 0 0 0

Magnitude comparator implementa;on

a0

a1

a2

a3

b0

b1

b2

b3(A=B)

(A>B)


  Note: (A<B) is not shown, but could be added. e3

Magnitude comparator comments

  Previous illustra;on is slightly different than in text book, but does the same thing.

  Rather than implemen;ng (A<B) using gates, we could realize that the following is true and use signals already generated:


Decoders

  When we have n‐bits, we can represent possibly 2n dis;nct paqerns.

  Figuring out what paqern is represented in n‐bits is called decoding.

  We can have n‐to‐m decoders with m = 2n.

  Basically, we can consider a decoder to recognize input paqerns and output a 1 corresponding to the minterm seen at the input.

  Oren a decoder will also have an enable signal. When enable=1, then the decoder func;ons as desired. When enable=0, all outputs are 0.


Illustra;on of a 2‐to‐4 decoder

enable

x

y

d0

d1

d2

d3


  We can consider the implementa;on of a 2‐to‐4 decoder (with an enable).

Decoders implemented with NAND gates

  Some;mes, in implementa;on decoders are done with NAND gates rather than AND gates.

  With NAND gates, the table illustra;ng the decoder opera;on would look like this:


  This only has the effect of inver;ng the outputs…

  So pay aMen;on… In using a decoder, it is useful to know when the output is intended to be ac;ve high, or ac;ve low!

enable

x

y

d0

d1

d2

d3

Decoder trees

d0

d1

d2

d3

x

y

enable


  If we have decoders with enables, we can use mul;ple, small decoders to implement larger decoders.

  Represent a smaller decoder as a box with inputs and outputs (we know how it works).

Example decoder tree: 4‐to‐16 decoder Using 2‐to‐4 decoders

d0

d1

d2

d3

x

y

enable

d0

d1

d2

d3

x

y

enable

d0

d1

d2

d3

x

y

enable

d0

d1

d2

d3

x

y

enable

d0

d1

d2

d3

x

y

enable

x1

x2

x3

x4

y0

y11

y10

y9

y8

y7

y6

y5

y4

y3

y2

y1

y12

y13

y14

y15


  Inputs are x1 (MSB), x2, x3, and x4 (LSB).

  Outputs are y0, , y15.

  The two most‐significant bits x1 and x2 are used to enable the appropriate decoder in the second stage.

  The two least‐significant bits x3 and x4 are used to generate the correct output in the second stage.

Func;on implementa;on with decoders

d0

d1

d2

d3

x

y

enable

d5

d4

d6

d7

z

a

b

c f

1


  If we have a decoder and an OR gate handy, we can also implement func;ons too…

  Consider implemen;ng f(a,b,c) = ∑(1,4,6,7) using a decoder and an OR‐gate to pick off the correct minterms.

Encoders

  Performs the inverse opera;on to a decoder.

  Encoder has 2n or fewer input lines and n output lines.

  The output is the binary code corresponding to the input value.

  Can make the circuit using OR‐gates.


Example of an encoder

  An example of an 8‐to‐3 encoder:


7

Priority encoders

  Simple encoder has problems:

  Assumes that only one input is ac;ve (high) at any given ;me. When mul;ple inputs are high, there is an undefined output.

  Produces the output of 000 when no input is ac;ve (high) which is the same as d0 begin ac;ve (high) so there is an ambiguity.

  A priority encoder gives priority to higher numbered inputs. It also has a validity output to indicate the all inputs are not zero.

  Example: 4‐to‐2 priority encoder:


Mul;plexers

  Combinatorial circuit block that has data inputs, select inputs and a single data output.

  Data is passed from one of the inputs through to the output based on the setng of the select lines.

  For n‐inputs, we need ceil( log2(n) ) select inputs.

  Mul;plexers have their own symbol.


Example of a 2‐input mul;plexer

s

x0

x1

f

0

1


  Illustra;on of a 2‐input mul;plexer:

  Can always write the SOP for a mul;plexer easily;   It is the appropriate setng of the control signal(s) AND‐ed with the appropriate

input (the control signals “gate” the AND).

Example of a 4‐input mul;plexer

s1s0

x0x1

f

00

11

0110x2

x3


  Illustra;on of a 2‐input mul;plexer:

  The SOP for the 4‐input mul;plexer is:

Mul;plexers trees

s1

x1 0

1x3

x0 0

1x2

s0

f

0

1


  We can build larger mul;plexers from smaller mul;plexers.

  Example: 4‐input MUX using several 2‐input MUX:

Implementa;on of an n‐input func;on using (n‐1) input mul;plexer


  We can implement an n‐input func;on using an (n‐1) input MUX by examining the truth table.   The first n‐1 inputs in the truth table become the control lines, and the last

input in the truth table is fed appropriately to the MUX inputs.

x0x1

x2x2

f

00

11

0110x2

!x2

Shannon decomposi;on

  We don’t need an (n‐1) input mul;plexer to implement an n‐input func;on using mul;plexers.   Building a 4‐input MUX from 2‐input MUX should sort of indicate that we can

implement logic func;ons using any sort of MUX (par;cularly 2‐input mul;plexers).

  Inputs to the logic func;on become the select lines, and we connect 0 or 1 to the data inputs of the MUX – the correct value (0 or 1) appears at the output given the setng on the select lines.

  Breaking a func;on down for a MUX implementa;on is called Shannon Decomposi;on.

  We should run through the math, since it is why it works…


Cofactors

  Consider any Boolean func;on f = f(x0, x1, , xn). We can always factor the func;on with respect to any variable, say x0.


  The terms f(0, x1, … , xn) and f(1, x1, … , xn) are the cofactors of f with respect to x0.

  No;ce the x0 no longer appears in either of the cofactors; it has been factored out.

  We can think of cofactors as dividing the truth table of f into halves.   The rows in which x0 = 0 are grouped together.   The rows in which x0 = 1 are grouped together.

  A MUX is used to select the proper half of the truth table based on the value of x0.

Example using only 2‐input mul;plexers (1)

  Implement the following func;on using 2‐input mul;plexers only (i.e., no logic gates).


  Solu;on is to cofactor with respect to some of the variables un;l we don’t need any logic gates (i.e., no product terms ler).

Example using only 2‐input mul;plexers (2)

x1

x2 0

1!x2

x2 0

1x2

x0

f

0

1


  Our final circuit using only 2‐input MUX is (simplified and unsimplified):

x1

x2 0

1!x2

x2

x0

f

0

1

Demul;plexers

  Recall that a mul;plexer selects from mul;ple inputs and directs this input through to the output.

  A demul;plexer does the opposite – it switches a single data input onto one of several output lines.

  Note: A demul;plexer is simply a decoder in which the meaning of the inputs has changed.

  The decoder enable becomes the data input.   The decoder data inputs become the select lines.

  Depending on how the decoder data inputs (select lines) are set, the selected output will follow the decoder enable (data input)


Tri‐State Buffers (1)

x y

oe


  In addi;on to 0 and 1, we need the concept of an open circuit, or a high impedance state.

  A circuit that allows us to disconnect the output (open circuit) is called a tri‐state buffer):

  The signal oe is the output enable:   When oe = 1, y = x, and   when oe = 0 the output y is disconnected from input x

Tri‐State Buffers (2)

  Tri‐state buffers are useful when we want mul;ple signals to drive a single wire at different ;mes.

  We can use the output enables to control which source drives a wire.

  We can implement mul;plexers with tri‐state buffers.

  Tri‐state buffers are useful in bus‐based design when we have mul;ple sources of informa;on that travel down the same set of wires (e.g., the data bus in a computer).


Mul;plexers built using decoders and tri‐state buffers

y

d0

d1

d2

d3

x

y

enable

i0

i1

i2

i3

select

enable


  Illustra;on of a 4‐to‐1 mul;plexer made with tri‐state buffers and a decoder:

Busses

  These slides are included since an upper‐year instructor ques;oned if students in ECE124 were taught this idea… Hence some explicit notes.

  A bus is simply a bundle of mul;ple wires running together which carry data from one place to another; e.g., “a 16‐bit bus, a 32‐bit bus, a 64‐bit bus”.

  We represent a bus using a bold line with a “slash” through it possibly labeled with the number of individual wires contained in the bus.


Busses

  Imagine that each wire in the bus has different sources of informa;on. In other words, there are mul;ple drivers for each wire.   You CANNOT have mul;ple sources driving the same wire at the same ;me! This

could, for example, cause electrical shorts if one source wants to drive a logical‐1 (+ve voltage) while another source wants to drive a logical‐0 (0 voltage).

  How can we prevent the “mul;ple driver problem” ???


Busses

  Could make each wire be driven by a mul;plexer. Then, the select lines on the mul;plexer control whose can drive the wire at any given ;me…

  Will never have more than one source driving a wire at a ;me.


In this illustration, there are 8 multiplexers; one for each wire in the bus!

Busses

  Can accomplish the same thing using tri‐state buffers and a decoder to force the enable signals on the tri‐state buffers to values such that only one tri‐state buffer is ever on (other tri‐states are in high impedance state).

  Will never have more than one source driving a wire at a ;me.


In this illustration, there are 8 tri-states; one for each wire in the bus!

Output enables coming from decoder; only 1 enable signal is active (at most) meaning only one driver ever connected.

week 4 - university of waterloopami.uwaterloo.ca/~basir/ece124/week4-2.pdf · overﬂow detecon...

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