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T H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

Issue 46Summer 2003

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Xcell journalXcell journalT H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

ISSUE 46, SUMM

ER 2003XCELL JOURNAL

XILINX, INC.

Low Cost Solutions for High Performance ResultsLow Cost Solutions for High Performance Results

NEW PRODUCTS

Spartan-3 FPGAs Open New Markets and Applications

RocketPHY Delivers 10 Gbps SONETPerformance in CMOS

SOFTWARE

ISE 5.2i Supports Spartan-3 FPGAs Now

Precision Synthesis Tool for Next-Generation Designs

APPLICATIONS

Scaleable SPI-4.2 “Lite” Solution for Spartan-3 FPGAs

Software-Compiled SystemDesign Methodology

TECHNOLOGY

Adaptive I/O SolutionAccelerates Serial Design

Second-Generation XCITE Lowers PCB Costs

NEW PRODUCTS

Spartan-3 FPGAs Open New Markets and Applications

RocketPHY Delivers 10 Gbps SONET Performance in CMOS

SOFTWARE

ISE 5.2i Supports Spartan-3 FPGAs Now

Precision Synthesis Tool for Next-Generation Designs

APPLICATIONS

Scaleable SPI-4.2 “Lite” Solution for Spartan-3 FPGAs

Software-Compiled SystemDesign Methodology

TECHNOLOGY

Adaptive I/O SolutionAccelerates Serial Design

Second-Generation XCITE Lowers PCB Costs

COVER STORYSpartan-3 FPGAs on 90 nm Technology Will Change the Way You Design Logic

COVER STORYSpartan-3 FPGAs on 90 nm Technology Will Change the Way You Design Logic

IBM Microelectronics

©International Business Machines Corporation, 2003. All rights reserved. All other products are trademarks or registered trademarks of their respective companies.

Get the product differentiation edge you need with IBM.

SEE THE NEXT NEXT BIG THING IN IBM POWERPC SOLUTIONS.

Discover how to speed your designs with the powerful combination of Xilinx FPGA solutions and IBM PowerPC processor cores. Stay ahead of your competition with IBM Microelectronics’ leading-edge technology, design expertise and process manufacturing excellence.

High performance with flexibility. IBM PowerPC microprocessors, embedded processors and cores deliver cutting-edge performance, scalability and power efficiency.

Real Support. With integrated product roadmaps, PowerPC licensing options and a network of distributors offering PowerPC products, IBM is the logical PowerPC choice. Visit www.ibm.com/powerpc/xcell

alph Waldo Emerson said it best: Do not go where the path may lead. Go instead where there

is no path and leave a trail.

Here at Xilinx, we do not follow the trends of business and technology – we set them.

Take, for example, our new family of Spartan™-3 Platform FPGAs – the first reprogrammable

logic devices to be manufactured with the state-of-the-art 90 nm process technology. Because 90 nm

device geometries enable more transistors in a smaller area, Xilinx has reduced die size with this

new generation of Platform FPGAs by as much as 80 percent – and increased density to as many

as 5 million system gates with as many as 1,200 user I/Os. Perhaps most important of all,

Spartan-3 FPGAs are priced to replace ASICs in high-volume production. Now the FPGA you

use to prototype your design can be the FPGA you use in the manufacture of your design.

We are also pleased to announce in this edition of XJ the RocketPHY family of 10 Gbps CMOS

Physical Layer (PHY) transceivers. Designed on a standard 0.15 µm CMOS process, RocketPHY

devices are the first Xilinx family of Physical Layer OC-192 SONET-compliant transceivers

optimized for a wide range of 10 Gbps optical interconnect applications. This technology is also

used in our new Virtex-II Pro™ X FPGAs.

Many of you may be reading Xcell Journal for the first time at Programmable World 2003.

Welcome to our world. It’s growing bigger, faster, and better every day. A subscription to XJ is

free for the asking (see URL below). We hope you enjoy and gain valuable knowledge from this

edition. Much of what we publish is brand new to the world. In our Fall 2003 issue, we will show

you what may very well be the beginning of the end of all fixed logic design. But if you just can’t

wait for the latest news and information on programmable logic and systems, visit Xcell Online

(www.xilinx.com/publications/xcellonline/), where you’ll find frequent reports on what’s happening

in the world of programmable logic.

L E T T E R F R O M T H E E D I T O R

Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400Phone: 408-559-7778FAX: 408-879-4780©2003 Xilinx, Inc.All rights reserved.

Xcell is published quarterly. XILINX, the Xilinx logo,CoolRunner, Rocket Chips, Rocket IP, Spartan, andVirtex are registered trademarks of Xilinx, Inc. ACEController, ACE Flash, Alliance Series, AllianceCORE,ChipScope, CORE Generator, Fast CONNECT, Fast FLASH,Fast Zero Power, Foundation, HDL Bencher, IRL, J Drive,LogiCORE, MicroBlaze, MultiLINX, NanoBlaze,PicoBlaze, QPro, Real-PCI, RocketIO, SelectIO,SelectRAM, SelectRAM+, Smart-IP, System ACE, Virtex-IIPro, Virtex-II EasyPath, WebFITTER, WebPACK,WebPOWERED, XACT-Floorplanner, XACT-Performance,XAPP, XC designated products, Xilinx Foundation Series,Xilinx XDTV, and XtremeDSP are trademarks, and TheProgrammable Logic Company is a service mark ofXilinx, Inc. Other brand or product names are registeredtrademarks or trademarks of their respective owners.

The articles, information, and other materials includedin this issue are provided solely for the convenienceof our readers. Xilinx makes no warranties, express,implied, statutory, or otherwise, and accepts no liabilitywith respect to any such articles, information, orother materials or their use, and any use thereof issolely at the risk of the user. Any person or entityusing such information in any way releases andwaives any claim it might have against Xilinx for anyloss, damage, or expense caused thereby.

Welcome to Our Programmable WorldR

Xcell journalXcell journal

Tom DurkinManaging Editor

EDITOR IN CHIEF Carlis [email protected]

MANAGING EDITOR Tom [email protected]

ASSOCIATE EDITOR Jack Shandle

COPY EDITOR Charmaine Cooper Hussain

XCELL ONLINE EDITOR Tom [email protected]

CONTRIBUTING EDITORS Jane MiddletonPeter Bergsman

ADVERTISING SALES Dan Teie1-800-493-5551

ART DIRECTOR Scott Blair

To subscribe to the printed Xcell Journal, or to view the Web-based Xcell Online Journal, visit:

www.xilinx.com/publications/xcellonline/

T A B L E O F C O N T E N T S

New Spartan-3 FPGAs Are Cost-Optimizedfor Design and ProductionThe new Xilinx Spartan-3 FPGA family offers up to 5 million systemgates with the lowest cost per gate and lowest cost per I/O comparedto any other programmable logic alternative. Why use a gate array orstandard cell ASIC when you can get a low-cost, high-density, andfaster time-to-market solution with Spartan-3 FPGAs?

7

Xcell Online Web XclusivesCheck out Xcell Online (www.xilinx.com/publications/xcellonline/) for these late-breaking Xcell Online Web Xclusives and more:

• Xilinx 300 mm and 90 nm Process Technologies: Why This Is Important to Designers.

• Is Your FPGA Design Secure? It Is with Xilinx – and Here’s How It Works.

• PCI Express Advanced Switching: Solve Your PCI Implementation Problems.

• Why The Boeing Company Chose Virtex-II Pro Platform FPGAs for Image Processing.

New RocketPHY Transceiver Family Debuts at 10 GbpsE

A new family of 10 Gbps serial I/O transceivers dramatically cuts costs in light-speed applications. These transceivers make it possible to create unique optical connectivity designs.

NSPICE Bridges Simulation Gap A next-generation, mixed-domain

SPICE tool with directly integrated S-parameter data capability provides

the most accurate simulation of combined silicon and system behavior.

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C O V E R S T O R Y

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2020

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Platform Delivers Fast,Flexible AC Servomotor-Control Designs New digital motor-control applicationsexceed the capabilities of conventional solutions.

82

How to Design a 3DES Security MicrocontrollerUsing IP cores and a pre-integrated IP platform, engineers at SoC Solutions built a custom microcontroller platform in less than two weeks.

69

View from the Top ................................................................6

New Spartan-3 FPGAs Are Cost-Optimized ................................7

Spartan-3 Family Opens New Applications..............................10

ISE 5.2i Delivers Head Start to Spartan-3 Designers ................14

Spartan-3 FPGAs Add SPI-4.2 “Lite” Core ..............................16

New RocketPHY Transceiver Family – 10 Gbps.......................20

Accelerate Your Multi-Gigabit Serial Design .............................24

High-Speed Serial Interface Design........................................28

Kit for Cadence Tools Speeds RocketIO Designs.......................30

Software-Compiled System Design ........................................32

Tarari and Celoxica — Fast Algorithm Acceleration .................38

Next-Generation FPGA Synthesis ...........................................44

NSPICE Bridges Simulation Gap ............................................46

Optimize Pin Assignments Early ............................................49

Got the BGA Blues?............................................................52

Reduce Resistor Counts and Lower Costs................................56

Get the EasyPath Solution ...................................................58

Xilinx Chips Fight Drunk Driving ............................................63

FPGAs Are the Brains Behind “Smart” Cars ............................64

How to Design a 3DES Security Microcontroller.......................69

How to Use Free Software in Embedded Designs ....................74

Xilinx Delivers HyperTransport Lite Reference Design ................79

Low-Cost IP Connectivity Lets Diverse Systems Communicate ........80

Platform Delivers Fast, Flexible AC Servomotor Designs ...........82

Xilinx FPGA Blasted into Orbit...............................................86

MyXPA Helps You Get the Most from the XPA Program ............90

Xilinx Events and Tradeshows...............................................91

Fuzzy Logic .......................................................................93

Xilinx Partner Yellow Pages..................................................94

Spartan-3 Data Sheet .......................................................102

Reference Pages...............................................................106

Get the EasyPath SolutionThe Virtex-II and the Virtex-II ProEasyPath solutions are a cost-effective alternative to ASIC conversion – saving you money while significantly decreasing your time to market.

S U M M E R 2 0 0 3, I S S U E 4 6

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Xcell journalXcell journal

Xilinx FPGA Blasted into OrbitA radiation-hardened Xilinx FPGA gives the Australian FedSat satellite powerful reconfigurable computing capabilities.

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E x t r a o r d i n a r yadvances in pro-grammable logictechnologies aremaking it possiblefor FPGAs to offerunique new waysto build advanceddesigns that werepreviously impos-sible. In fact,

many traditional design components arebecoming obsolete as FPGAs becomefaster and less expensive. The standardmicroprocessor is no longer the only way –or the best way – to develop high-performance, low-cost computers.

Programmable logic devices are dramat-ically changing the way computers aredesigned. Instead of using a single CPUthat executes instructions serially (the vonNeumann approach), with programmablelogic you can easily run multiple tasks inparallel and achieve an impressive increasein performance while drastically reducingcosts. The benefits are too overwhelming toignore, and programmable logic is the key.The von Neumann architecture is already50 years old – it’s clearly time for a change.

A Xilinx customer, Wincom Systems, willsoon introduce a new Web server that canhandle the work of 50 to 300 conventionalmicroprocessor-based servers each costing$5,000 or more – and it costs approximately$2,500. It does all this without relying onmicroprocessors, and the server fits in a boxthe size of a DVD player. This remarkableimprovement in cost and performance isbeing realized in a variety of other newdesigns that will soon come to market.

Because FPGAs can easily handle mas-sive numbers of calculations in parallel,they are far faster than conventional DSPsor microprocessors in many applications.

Programmable logic has always been farless expensive to develop than ASICs. Nowthe device costs have been dramaticallyreduced as well. For example, an FPGAthat cost $1,000 in 1996 costs less than$10 today – and today’s device offers farmore features at a much higher speed. Inaddition, the introduction of 90 nm tech-nology will position our costs to be low-ered once again. Next year, our largestFPGA will have approximately 20 milliongates, compared to 20,000 in 1993.

ConclusionProgrammable logic devices can do muchmore than just replace conventional com-ponents. You can create designs that arefar more profitable and far more power-ful than alternative solutions. Your busi-ness depends on getting new designs tomarket ahead of your competition –designs that provide maximum value, atminimal costs. Programmable logic deliv-ers what you need, today. And it justkeeps getting better.

Programmable logic devices performing many operations in parallel are replacing microprocessors by providing much higher performance at far lower cost. Here’s one example.

Move Over, von Neumann

6 Xcell Journal Spring 2003

Viewfrom the top

by Wim RoelandtsCEO, Xilinx, Inc.

6 Xcell Journal Summer 2003

by Rob SchreckSenior Marketing Manager Xilinx, [email protected]

Today’s design engineers deal with adilemma every time they start a newlogic development project. They wantto develop a product fast and get it tomarket first – but they also must meetdemands to lower costs. Many times,engineers have turned to ASIC solu-tions to meet their cost objectives, butthat often means high NRE costs andlong development times. Using ASICsalso often means running the risks of:

• Missing the market window

• Losing out to competition

• Design problems

• Design changes

• Skyrocketing NRE costs.

New Spartan-3 FPGAs Are Cost-Optimized for Design and Production

Summer 2003 Xcell Journal 7

New Spartan-3 FPGAs Are Cost-Optimized for Design and ProductionThe new Xilinx Spartan-3 FPGA family offers up to 5 million system gates with the lowest cost per gate and lowest cost per I/O compared to any other programmable logic alternative. Why use a gate array or standard cell ASIC when you can get a low-cost, high-density, and faster time-to-market solution with Spartan-3 FPGAs?

The new Xilinx Spartan-3 FPGA family offers up to 5 million system gates with the lowest cost per gate and lowest cost per I/O compared to any other programmable logic alternative. Why use a gate array or standard cell ASIC when you can get a low-cost, high-density, and faster time-to-market solution with Spartan-3 FPGAs?

Xilinx offers you a better solution withthe new class of Spartan™-3 PlatformFPGAs. Built on four generations of provenSpartan success in high-volume consumerand automotive applications, this new family of Platform FPGAs delivers unprece-dented density, field reprogrammable func-tionality, and competitive price points. Youalso get a platform with the density, scalabil-ity, and features to tackle tough connectivity,DSP, and embedded design problems.

With Spartan-3 FPGAs, youcan develop logic for many newconsumer, networking, andautomotive applications, includ-ing blade servers, low-costrouters, and medical imaging.You can get those products tomarket fast, because you manu-facture the system with the sameFPGA you use to develop andprototype the design.

Driving Down FPGA CostsDesign engineers have beenlooking for an alternative to longASIC development cycles andhigh ASIC NRE costs. To sup-port an industry requirementthat has grown to over $20 bil-lion, Xilinx set the goal of lowcost, unprecedented densityrange, and high capability for the Spartan-3family of FPGAs so they could be used bothfor prototyping and for production of high-volume products. To meet that aggressivetarget, Xilinx developed this Platform FPGAarchitecture with a small die size, a widelogic density range, and sufficient I/Os tosupport the mid-range of gate array andstandard cell logic designs. In addition,Xilinx included the features most needed fortoday’s designs:

• Up to 1.8 Mb of block RAM can beused for large FIFOs and data storage.

• Abundant distributed RAM, imple-mented from logic cells, can be usedfor small FIFOs, shift registers, andconstant coefficients. This combinationof block RAM and distributed RAMprovides a unique flexibility foundonly in Xilinx FPGAs.

FPGAs. These 300 mm wafers deliveralmost 2.5 times the number of die com-pared to the mature 200 mm wafers, but ata fraction of the cost per die. We alsoimplemented a dual wafer fabrication strat-egy, using world-class foundries at bothIBM and UMC to reduce production risksand increase capacity.

Our process technology leadershipmakes Xilinx the world’s lowest-cost, lowest-risk FPGA provider. The Xilinx

investment in design opti-mization, 90 nm manufactur-ing technology, and 300 mmwafer production deliversprice points for Spartan-3FPGAs at under $20 for a 1M-gate FPGA and under $100for a 4M-gate FPGA.

Delivering More I/Os in Smaller DieSpartan-3 FPGAs offer aremarkably small die for thenumber of logic gates using 90 nm process technology.Naturally, with a smaller diecomes a smaller perimeter forthe necessary number of I/Opads. This could be a problemfor an application thatdemands a high I/O count.

However, by using staggered pad technolo-gy (Figure 1), Xilinx is able to deliver tworows of I/Os on each edge of the die versusone row found in all other FPGAs andASIC alternatives. You get more I/Os in asmaller die, resulting in a low cost per I/Oand low cost per gate for Spartan-3 FPGAs.

Spartan-3 FPGAs: The Complete Design PlatformSpartan-3 Platform FPGAs offer a completesolution of logic, memory, and I/Os – alongwith features such as multipliers – to providea rich fabric to support connectivity, DSP,and embedded design applications (Figure 2).

Spartan-3 Connectivity SolutionMany design problems revolve around get-ting data on and off the FPGA. The bestway to ease these connectivity problems is arobust I/O solution. All Spartan-3 I/O pins

• Digital clock managers (DCMs) andpre-engineered clock networks facilitatethe design of high-speed systems.

• High-speed multipliers are embeddedfor DSP applications, such as adaptivefilters and forward error correction.

• Programmable SelectIO™-Ultra sup-ports 23 I/O standards and provides alow-cost bridge from one I/O standardto another.

• XCITE digitally controlled impedancetechnology supports increased signalintegrity for both single-ended and differential I/Os.

The result is a cost-optimized FPGAfabric that is, nevertheless, flexible, scala-ble, and able to provide the capability tosupport many designs.

Process Leadership in 90 nm Xilinx integrated a large logic density rangewith all of the above features – and thentook another giant step to drive down costusing a new 90 nm process technology. TheSpartan-3 FPGA family is the first pro-grammable logic built with this processtechnology, which leads to die sizes 50% to80% smaller than any competing solution.

Xilinx also uses 300 mm wafer technol-ogy to deliver the efficiency and capacityneeded to produce high-volume Spartan-3


Figure 1 - Staggered pad technology

support the Xilinx SelectIO™-Ultra func-tionality, dramatically increasing design flexibility. Each user I/O pin can support anyof the 23 electrical interface standards. Withthe abundant I/Os in the Spartan-3 FPGAfamily, you get the lowest cost per parallelinterconnect available in the industry.

The differential I/O standards assist youin achieving higher performance, lowerpower consumption, and lower pin count.These standards are supported by soft IPbuilding blocks for important new interfaceprotocols, such as PCI 32/33 and PCI64/33, RapidIO™, POS PHY Level 4,Flexbus 4, SPI-4, and HyperTransport™.

To further simplify the design process andreduce costs, the Spartan-3 FPGAs supportXCITE digitally controlled impedance tech-nology for both single-ended and differentialI/O standards. XCITE technology providesI/O impedance matching that adapts tochanges in supply voltage and temperature.XCITE technology reduces board cost byeliminating the need for most external ter-mination resistors. What’s more, XCITEtechnology increases signal integrity.

Low-Cost Points for High-Performance DSP The abundant RAM resources – along with18X18 multipliers – give Spartan-3 FPGAs a

significant DSP capability that can deliver upto 330 billion MACs/second. This economicaland robust performance makes Spartan-3devices a cost-effective solution for low-costapplications, such as digital communications,video and imaging, and industrial control.

In addition, the partnership between Xilinxand The MathWorks offers a simple, familiardesign flow with MATLAB™/Simulink™software to design the DSP functions.

Industry’s Lowest Cost Soft Processor SolutionThe high feature set of the Spartan-3 FPGAfamily provides a low-cost platform forembedding the Xilinx MicroBlaze™ soft

processor. When you combine theMicroBlaze processor and available peripher-als with Spartan-3 logic, memory, and I/Os,you can develop a custom embedded designfor your specific requirements. You increaseon-chip integration, reduce board cost, andminimize the risk of vendors choosing tomake obsolete a specific microcontroller.

Xilinx Complete Development SupportSpartan-3 FPGAs also come fully supportedin the current Xilinx ISE 5.2i software designsuite (Figure 3). ISE 5.2i is the most prevalentdesign methodology in the industry, withmore than 150,000 installed users. ISEincludes a full spectrum of easy-to-use productivity options that can be inserted tofit in almost any existing corporate logicdesign methodology. Xilinx ISE tools increaseyour productivity, which in turn slash designtimes by as much as 50% when compared toASIC methodologies.

For design verification, the XilinxChipScope™ Pro debugging environ-ment delivers unmatched power touncover critical bottlenecks and opti-mize your design.

For engineers using the MicroBlazeprocessor to develop a field program-mable controller, Xilinx offers a com-plete hardware and software solutionwith the Xilinx Embedded Design Kit(EDK). Software tools similar to thoseused for IBM PowerPC™ designs areavailable to:

• Configure peripherals

• Develop protocols

• Integrate the logic.

Then you can verify your design in thesystem at speed in the Spartan-3 FPGA. It’san easy solution for today’s complex designs.

ConclusionThe Xilinx Spartan-3 FPGA offers the lowestcost FPGA in the industry, as well as a truelow-cost design platform for many applica-tions. You get the density and features youneed for a wide range of designs, plus a devel-opment environment to get you through thedesign cycle and into production quickly. Tolearn more about the Spartan-3 family, visitwww.xilinx.com/spartan3/.


Figure 2 - Spartan-3 Platform FPGA

Figure 3 - ISE 5.2i design suite

by Robert Bielby Sr. Director, Strategic Solutions MarketingXilinx, [email protected]

Nineteen years ago, Xilinx introduced thefield programmable gate array, or FPGA.The concept was simple: by building agate array based upon SRAM technology,you could develop a chip directly on yourdesktop, doing away with the high non-

recurring engineering costs associatedwith custom ASICs. The benefits

of this technology were imme-diate and obvious – instantturnaround time and infinitereprogrammability. The ideaof a “foundry on the desktop”

caught on over time as design-ers began to rely on FPGAs for

product development and limitedproduction deployment.

However, because of the inherent sili-con overhead cost for reprogrammability(easily more than 20:1 for an FPGA vs.ASIC), FPGAs were not considered cost-effective for higher volume applications.

Spartan-3 FPGAs invade traditional ASIC markets with competitive price points and value-added reprogrammability.

Spartan-3 Family Opens New Markets and Applications


Spartan-3 Family Opens New Markets and Applications Spartan-3 FPGAs invade

traditional ASIC markets with competitive price points and value-added reprogrammability.

In 1998, Xilinx forever changed theplaying field with the introduction of theSpartan™ FPGA family. Based on thehighly successful XC4000 FPGA architec-ture, the Spartan FPGA family heralded anew era in programmable logic by deliver-ing products at price points previously notconsidered possible in the industry.Through streamlined packaging, speedgrades, test, and process technology, Xilinxachieved significant cost reductions. Thesereductions opened a wide range of newmarkets and applications that could reapthe time-to-market benefitsand flexibility of program-mable logic.

Since the introductionof the first Spartan family,Xilinx has maintained anunabated trend of deliver-ing successively improvedSpartan families almostyearly. Each new familyoffered significant cost andperformance benefits overthe previous families.Additionally, each familyprovided additional, newfeatures leading to an evengreater reduction in bill ofmaterials costs.

The extent of the costreductions cannot be over-stated: The Spartan-II, thethird-generation Spartanfamily, featured the 100,000-gateXC2S100 family member for just $10.This represents a 100:1 reduction in costover the equivalent density device that wasintroduced just five years earlier.

The Spartan-II FPGA not only deliversa lower cost per gate than its predecessor, italso includes embedded features, such aslogic level translators, embedded memoryblocks, and integrated phase locked loops,all at the $10 price point. Thus, it’s no sur-prise that more than 45 million units of theSpartan-II series family have been shippedsince its introduction.

Equally as impressive is the range andtypes of applications where Spartan FPGAsare used in production. Applications suchas PC add-in cards, children’s digital cam-

of up to 1,120 user I/Os, the Spartan-3FPGA family opens up the world of pro-grammability to an even greater suite ofapplications than ever before.

Driving New MarketsWith such a wide density range and pincount, the Spartan-3 family can competewith the majority of ASIC design starts. Ineffect, in the future, it’s going to be harder tofigure out where you won’t find Spartan-3FPGAs than where you will find Spartan-3FPGAs. Although this comment may be

somewhat fanciful, the listof markets and applicationsin those markets that are aperfect match for the new,low cost Spartan-3 family isquite broad:

Automotive The newest innovations inautomobiles today are notcentered on improved fuelefficiency or improved per-formance, but instead arefocused on improving thedriver and passengers’ driv-ing experience and safety.This emerging new technol-ogy is called telematics.

Telematics represents thegreatest innovation in theautomotive industry sinceperhaps the introduction of

the car itself. Imagine what would be possi-ble if all of your personal informationappliances and entertainment devices couldcommunicate and share information withone another in a single environment. Insuch a scenario, your cell phone couldcommunicate directly to your PDA, whichwould allow you to review your email,download a MP3 audio track, and play iton the car stereo while you checked yourstock portfolio and looked for the bestroute to go to work. Multifunction telem-atics is both possible and available in high-end cars today.

The challenges to optimal telematics,however, are many, because the emergenceof new standards, technologies, and shortdevelopment cycles complicate product

eras, CD players, DVD players, personalcomputers, set-top boxes, personal videorecorders, plasma displays, MP3 players,home theater, home audio, karaokemachines, and a host of other applicationstoo extensive to list here. It’s almost safe tosay that if you can think of an application,there’s a very good chance that it contains aSpartan FPGA.

The effect of a low-cost FPGA hasn’t goneunnoticed on the Xilinx bottom line: Todaymore than 13% of Xilinx revenue is generat-ed in nontraditional consumer applications.

With the recent introduction of theSpartan-3 family, Xilinx continues to buildon the momentum established six years ago– delivering FPGAs at price points that areunmatched in the industry. Based on a 90nm SRAM technology and manufacturedon 300 mm wafers, the Spartan-3 familyenjoys the industry’s most advanced processtechnology. This technology allows theSpartan-3 family to maintain an inarguableprice/performance advantage over not onlycompetitors’ FPGAs but also ASICs.

The Spartan-3 family also represents asignificant breakthrough both in densityrange and I/O pin count when compared toprevious the Spartan families. With a 100:1range in density spanning from 50,000gates to 5,000,000 gates and an I/O count


development and deployment. Cost-effective, flexible solutions such as thosemade possible by Spartan-3 devices willenable you to stay current in this rapidlygrowing and evolving market.

MedicalThe latest breakthroughs in telemedicineleverage advances in networking andbroadband technologies to provide localcare by a remote physician or a team of dis-persed specialists.

New programs, such as Telestroke, havebeen developed to support medical doctorswho practice medicine in small rural com-munities or in community hospitals wherethere are no local specialists in stroke treat-ment. The Telestroke program is a systemto connect medical staffs who work atemergency rooms of small hospitals withstroke specialists by using videoconferencesystems, ISDN, and desktop computers.These two parties examine the patientsimultaneously, test the extent of thestroke, investigate scanned films of thepatient’s internal organs, and determinethe types of strokes that the patient mayhave suffered. The system enables strokespecialists to tell doctors in the emergencyroom what appropriate medication to pre-scribe and what operations to perform.The cost sensitivities of this technology,which combine a wide range of complextechnologies, are again well addressed bySpartan-3 FPGAs.

Digital Video The digital television set market is poised toenter a period of sustained growth. Variousregional digital broadcasting standards havebeen established in most countries – ATSChigh definition in the U.S. and South Korea,ISDB in Japan, and DVB in most of the restof the world. More countries continue toroll out digital television services everymonth. And there is more to come. In theU.S., high-definition cable signals are beingoffered by an increasing number of cableservice providers in an increasing number ofmarkets.

Meanwhile, digital terrestrial broadcastsare expected to begin in Japan this year. Thedeployment of digital video services will

drive the long-awaited consumer demandfor digital television sets. The image pro-cessing requirements demand both a cost-effective yet high-performance digitalsignal processing technology such as thatoffered by Spartan-3 devices.

Home NetworkingThe connected home market – consistingof home networking equipment, software,residential gateways, home control, andautomation products – is estimated to be$9.2 billion worldwide by 2006. The cur-rent growth of the connected home markethas been spurred over the past year by asurge in popularity of wireless networkingtechnology and basic home routers toenable broadband and resource sharing,including file and printer sharing.

Multiple other factors will continue tofuel this growth, including the need for net-work security. Home routers and residentialgateways will need “firewall” protection foralways-on connections. Additionally, therelease of Windows™ XP, the first true“home network friendly” operating systemfrom Microsoft, has greatly simplified thetask of interconnecting and sharingresources. The next wave in home network-ing will be the broad-based sharing of videoand audio – adding new complexities andchallenges but also benefits to the consumer.Localized media centers with global sharingwill drive new solution models that willagain greatly benefit from the programma-bility and flexibility of Spartan-3 FPGAs.

These examples are but a small samplingof the many exciting new markets and appli-cations for Spartan-3.

eSP Simplifies System DesignTwo years ago, Xilinx introduced theindustry’s first Web portal dedicated toaccelerating product development for awide range of markets and applications.With a focus on providing solutions andtutorials primarily targeting new andemerging standards and protocols, theaptly named eSP (emerging standards andprotocols) Web portal has proved to be aneffective industry resource validated bymore than seven million visits to date.

The eSP portal covers a wide range ofmarkets and applications, including:

• Both consumer and professional digitalvideo technologies

• Wireless networking

• Home networking

• Automotive telematics

• Metro access networking technologies.

With the introduction of the Spartan-3family, Xilinx has expanded the breadth ofthe eSP portal to highlight and providesolutions and tutorials on the new marketsand applications now addressed by this rev-olutionary new FPGA family. To learnmore about the new Spartan-3 markets,applications, and solutions, visit the eSPportal at www.xilinx.com/esp/.


Thousands of Designers.Infinite Applications.

One Powerful Resource.

Online innovation

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this is the ultimate resource for all your design solutions.

The power of 3

The high-performance, low-cost Spartan-3 platform FPGA features a range of

density options from 50,000 to 5 million gates, as well as the lowest I/O and gate

costs available. This makes it the ideal device for a wide variety of applications.

Now, our eSP web portal gives you access to a complete suite of Spartan-3 silicon,

software, and IP solutions optimized for your design.

For more information, visit us at www.xilinx.com/esp/s3.

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® 2003 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx and Spartan are registered trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc.

by Lee HansenProduct Solutions Marketing ManagerXilinx, [email protected]

Why wait for critical software design sup-port of the latest FPGA family when XilinxISE 5.2i design software already supportsthe new, low-cost Spartan™-3 FPGAs rightnow? You can hit the ground running withthe newest and best-in-class FPGAs anddevelopment tools – including third-partysoftware support.

Spartan-3 FPGAs are based on the pioneering Virtex™-II Platform FPGAarchitecture introduced in late 2000.Virtex-II FPGAs exploded beyond thesupposed limits of what a programmablelogic device could do. Since then, theXilinx ISE design environment has keptpace with the technology to make full useof the Platform FPGA architecture,including tight partner tool integration.

Xilinx ISE 5.2i design and development software allows you to take full advantage of the features of the newly released Xilinx Spartan-3 family of FPGAs.

ISE 5.2i Delivers Head Start to Spartan-3 Designers


ISE 5.2i Delivers Head Start to Spartan-3 DesignersXilinx ISE 5.2i design and development software allows you to take full advantage of the features of the newly released Xilinx Spartan-3 family of FPGAs.

Leverage the Architectural AdvantageSpartan-3 FPGAs are ready to use withSynplicity™ and Mentor GraphicsExemplar synthesis support now. Thatmeans all of the internal logic structurescan be put to maximum use in yourSpartan-3 design today – not six months toa year from now, which is the usual time-line when a new architecture is released.

The ISE 5.2i toolset and synthesis part-ners support inferencing of internal logicstructures. This allows the synthesis tools tomake maximum performance choices foryour design during implementation, andmakes it easier to code, debug, and readHDL source code.

Spartan-3 devices also contain the“active interconnect” routing pioneered inVirtex-II FPGAs. The active interconnecttechnology, with its buffered routing,allows more logic structures to be reachedwith minimum impact on signal delaytime. Because timing delay is minimized,even for long signal routes, you also see lessimpact to timing during the re-place-and-route phase. With active interconnect tech-nology, more signal paths stay in time specthan with traditional architectures.

ISE 5.2i offers architecture wizardsupport for the Spartan-3 DCMs (digitalclock managers), as shown in Figure 1.The architecture wizard lets you programthe advanced clock features of theSpartan-3 DCMs through an easy-to-use

focusing on individual module performancerather than overall design completion.Modular design functionality speeds thedesign flow through to faster completion.

Although incremental design and mod-ular design have similar capabilities, theincremental design approach provides asimple design flow and faster runtimeswhen all modules are available. On theother hand, the modular design optionprovides individual independence inside ateam environment and can be used whenyou need the flexibility for design modulesto arrive at different times.

The area mapping capabilities of ISEFloorplanner and PACE enable quick andeasy logic grouping, leading to better timingresults and faster design performance. RPMs(relationally placed macros) allow designteams to save floorplanned HDL designs forlater design reuse. RPMs let managers bestutilize their HDL resources and deliverrepeatable, guaranteed design performance.

ConclusionWith ISE 5.2i and Spartan-3 FPGAs, younow have at your fingertips the lowest costFPGA design options available today. ISE5.2i extends these advantages by adding thedesign edge that delivers more productivityand lower design costs, all in a packagethat’s built on proven Xilinx architecturaldesign advantages.

design wizard. Just set the appropriateattributes in the dialog box, and fullyeditable VHDL or Verilog™ code is writ-ten into your HDL source, saving valu-able design time. This HDL source is“correct by construction” without requir-ing you to understand every nuance ofthe device architecture.

The full range of I/O options forSpartan-3 FPGAs are completely support-ed in ISE, including differential routing,which gives you the maximum in systemI/O protocol choices. Xilinx XCITE digitalinternal resistor I/O termination is fullysupported in ISE, greatly reducing thenumber of external resistors on your boardand freeing up valuable PCB real estate foressential devices.

Productivity Options A full spectrum of ISE design productivityoptions is available to optimize yourSpartan-3 design. Incremental design tech-nology slashes design recompile times bylimiting the re-implementation phase to onlythe design modules that need to change. Therest of the design is frozen and intact, pre-serving previous performance results.

Now included at no extra cost in ISE 5.2iis a modular design capability delivering adivide-and-conquer, team-based approachto high-density design. Teams of engineerscan complete their modules in parallel,


Figure 1 - ISE 5.2i DCM architecture wizard

by Krista MarksSr. Engineering Manager, IP Solutions DivisionXilinx, [email protected]

Paul Ingersoll Solutions Marketing ManagerXilinx, [email protected]

Finding creative ways to keep costs low hasbecome a mandate for designers ofadvanced systems. This is especially true inthe telecommunications space, where thedemand for ultra-fast 10 Gbps infrastruc-ture performance is still in the formativestages. Therefore, providing 10 Gbps levelsof performance is not a market or productpriority at this time.

Instead, metro access and WAN/LANequipment providers are focused onbuilding and servicing the more main-stream 2.5 Gbps infrastructure as a wayto ride out the current economic dol-drums. Their priorities have shifted fromfeatures and performance to cost and riskavoidance.

Given these market conditions, design-ers of Ethernet, Packet-Over-SONET, andATM applications have demonstrated akeen interest in low-cost solutions forinterconnecting PHY devices and trafficmanagement components such as networkprocessors and ASSPs using the SPI-4.2interconnect standard.

Xilinx is responding to this interestwith a pre-engineered, drop-in SPI-4.2“Lite” intellectual property (IP) core thatcan be implemented on its low-costSpartan-3 devices. The core is fully com-pliant with the 10 Gbps (OC-192) OIF-SPI4-02.0 specification while operating ata reduced line rate of 2.5 Gbps (OC-48).This article provides an overview of thebenefits of the solution and the details ofthe SPI-4.2 Lite core.

Spartan-3 FPGAs and SPI-4.2 Lite The sweet spot for new telecommunica-tions equipment over the next 12 to 18months will be products running at 2.5Gbps. Because POS-PHY Level 3 (SPI-3)is targeted to 2.5-Gbps OC-48 applica-

Spartan-3 FPGAs AddSPI-4.2 “Lite” Core to Slash Design Costs


The SPI-4.2 “Lite” solution for Spartan-3 FPGAs delivers 2.5 Gbps but remains compliant with the SPI-4.2 10 Gbps specification to deliver a low-cost, high-end solution perfect for existing MAN/LAN networks.

tions, one way to meet this demand is tobuild SPI-3 compliant interfaces insidethese products.

However, a powerful alternative tobuilding a SPI-3 interface is to build aninterface using the SPI-4.2 Lite solutionhosted on a Spartan-3 FPGA. Thisapproach achieves 2.5 Gbps line rateswhile still adhering to the OIF SPI-4.210 Gbps specification. Furthermore, thePCB design is simplified because thissolution delivers better flow control thanthe SPI-3 standard and uses fewer pins.

Hosting the SPI-4.2 Lite IP core on aSpartan-3 allows gigabit networkproviders to meet the demand for 2.5Gbps performance at the lowest possiblecost – while also putting their designersin a great position for the transition to10 Gbps data rates. Because the coreruns at a line rate of 2.5 Gbps, comparedto 10 Gbps for the full-rate core, it canbe successfully hosted on a low-costSpartan-3 device that delivers the requi-site performance to achieve the lowerline rate.

The SPI-4.2 Lite solution is a greatstarting point for network equipmentproviders that will scale their products to10 Gbps data rates when the marketmoves in that direction. Because theSPI-4.2 Lite solution running at 2.5Gbps is functionally compliant with theOIF SPI-4.2 10 Gbps specification, theinternal interface, the functional testing,and the back-end application logic canall be reused. In the line card design, asshown in Figure 2, IP reuse is straight-forward. Only the size of the SPI corewill change. This significantly reducesthe development time associated withbuilding equipment targeted at a 10Gbps-dominated marketplace.

SPI-4.2 Lite Core OverviewThe SPI-4.2 Lite core is delivered as inde-pendent source (Tx) and sink (Rx) cores.A block diagram of the SPI4.2 Lite IPcore and its interfaces is shown in Figure3. It is a drop-in replacement for theXilinx full-rate SPI-4.2 IP core – the sig-nals and functionality of both the full-rateand Lite SPI4.2 core are identical.

single combined EOP/SOP control word. You can request the insertion of idle

cycles or training patterns regardless of thesource FIFO status. By allowing the inser-tion of idle bus cycles in response to userrequests, flow control latency is greatlyreduced. In addition, the SPI-4.2 Litecore is able to transfer contiguous databursts across the SPI-4.2 interface. Thesource FIFO will refrain from transmit-ting data until an entire burst has beenwritten into the FIFO. Once a burst hasbeen written into the FIFO, the data willbe transferred across the SPI-4.2 interfacewithout interruption until the entire bursthas been transmitted.

SPI4.2 Lite Core Specifications:

• Performance: 200 Mbps on SPI-4.2

• Supported families: Virtex™-II,Spartan-3

• Slices Required: 1,450

• SelectRAM™ blocks: 6

• Global clock buffers: 3

• Digital clock managers: 2.

The source and sink cores provide datastorage implemented with FIFOs using dual-port SelectRAM blocks that support inde-pendent read/write clock domains. TheseFIFOs allow the storage of up to 512 datawords. The design optimizations developedfor the full-rate SPI-4.2 source core are alsoimplemented in the Literelease. This includes theunique ability of theXilinx SPI-4.2 solutionto maximize bandwidthutilization by not insert-ing filler idle cycles on theSPI-4.2 interface. Undernormal operating condi-tions, back-to-back pack-ets are separated by a


SPI-4.2 Lite IP Core1450 Slices = 10%

SPI-4.2 Full-Rate IP Core3550 Slices = 25%

Floorplanner Snap ShotXC2V3000-FF1152

Rx

TxTx

Rx

OC-48 2.5G Line Card

NPU

(ASSP)

Traffic

Manager

SER

DES

OC-192 10G Line Card

NPU

(ASSP)

Virtex-II

OC-192

PHY (ASSP)

Optical

I/F

Traffic

Manager

SER

DESSPI-4.2

Full-RateCore

USERSDESIGN

Spartan-3

SPI-4.2Lite Core

USERSDESIGN

OC-48

PHY (ASSP)

Optical

I/F

OC-48 FPGA USER DESIGN AND PCB LAYOUT CAN BE REUSED FOR OC-192 APPLICATIONS

Figure 1 - Lite core requires 15% fewer slices.

Figure 2 - SPI-4.2 Lite and full-rate design reuse example for OC-48 and OC-192 line cards

SPI-4.2 Lite InterfacesThe SPI-4.2 Lite core has four primaryinterfaces:

1. User interface

2. SPI-4.2 interface

3. Status interface

4. Calendar interface, as shown in Figure 3.

The core also has a set of static configu-ration signals that are used for in-circuitcustomization of the core. The SPI-4.2core’s interface supports up to 200 Mbps(100 MHz LVDS DDR I/O) for an aggre-gate bandwidth of 2.5 Gbps. Like the full-rate SPI-4.2 IP core, the FIFO status pathoperates at a quarter of the data rate and itselectrical interface can be user-configuredto be either LVTTL or LVDS.

In order to support the widest range ofapplications, the SPI-4.2 Lite core offersyou a choice of either a 32-bit or 64-bituser interface. The user interface operatesat up to 150 MHz for both the 32-bit and64-bit core configurations. With the 64-bitinterface at frequencies greater than 100MHz, the user interface can operate at ahigher bandwidth than the SPI-4.2 inter-face. You can transmit and receive datafrom two FIFOs implemented in dual-portSelectRAM blocks that each support inde-pendent read/write clock domains.

This interface is designed with standardFIFO handshaking signals to simplify theuser’s logic. For additional flexibility, thesource FIFO status channel interfacecomes in two configurations: the address-able interface and the transparent interface.The addressable calendar can be pro-grammed to indicate the order and fre-quency of the channel’s status on the userinterface, enabling a polling implementa-tion. The transparent calendar has a 2-bitinterface for all channel configurations andis updated in the order that it is received bythe sink interface, allowing minimal laten-cy in the flow control implementation.

Quick Start to Implementation Two Xilinx implementation documents areprovided with the core: the SPI-4.2 DesignExample Guide and the SPI-4.2 Quick Start

Guide. These documents help you quicklyintegrate the SPI-4.2 core into your design.

The SPI-4.2 Design Example Guideprovides RTL code (along with a user’sguide) that enables you to simulate thecore immediately with automatically gen-erated SPI-4.2 packet data. This illustrateshow to connect to each of the core’s inter-faces. The provided code is also synthesiz-able so you can run it through Xilinximplementation tools. This allows you toinstantly view the layout of the core in theFloorplanner, simulate the core with back-annotated timing information, and quick-ly evaluate performance compliance.

The SPI-4.2 Quick Start Guide con-tains the information necessary for you tomodify the core to meet your designrequirements. It walks you through theprocess of selecting the correct designs andnetlists, customizing the timing and con-straints necessary for their particular appli-cation, and running the automatedimplementation scripts.

ConclusionThe compact SPI-4.2 Lite core combinedwith the low-cost Spartan-3 architectureprovides a powerful SPI-4.2 interconnectsolution that helps telecommunicationsand networking infrastructure providersrespond to the pressure to deliver low-costsolutions in today’s marketplace. The SPI-4.2 Lite core is packaged with the full-ratecore and is offered at $18,000 (USD).Customers with an in-maintenance licensefor the full-rate core are entitled to receivethe new SPI-4.2 Lite core as an update.

For more information, or to evaluatethe new SPI-4.2 Lite core, please contactyour Xilinx sales representative.

References

[1] PMC-Sierra, Inc., POS-PHY™ Level-4, ASaturn Packet and Cell Interface Specificationfor OC-192 SONET/SDH and 10Gb/sEthernet Applications. Issue 5: June 2000.

[2] OIF-SPI4-02.0 System Packet InterfaceLevel-4 (SPI-4) Phase 2: OC-192 SystemInterface for Physical and Link Layer Devices.


SPI-4.2 Lite Source Core

SPI-4.2 Lite Sink Core

Source

Interface

FIFO

Interface

Sink

InterfaceStatus

Registers

CalendarBuffer

UserInterface

Sink Status

Interface

Sink Calendar

Interface

FIFOInterface

StatusRegisters

Calendar

Buffer

SPI-4.2

ReceiveInterface

User

Interface

Source StatusInterface

Source Calendar

Interface

SPI-4.2

Transmit

Interface

Figure 3 - Block diagram of SPI-4.2 Lite and full-rate core

It’s another industry first from

Xilinx®_a Platform FPGA with

IBM PowerPC™ processors and serial transceivers ranging from

622Mbps to 3.125 Gbps today, and 10 Gbps just around the corner.

ALL THE SUPPORT YOU NEED

The high-performance Virtex-II Pro™ RocketIO™ serial transceivers are

implemented on the industry’s most widely adopted FPGA fabric, including

high-speed DSP and processing for the complete solution. Our extensive

library of serial IP cores and reference designs supports all major standards.

The reconfigurability of the Platform FPGA can dynamically accommodate

any spec changes. And together with industry leading partners such as

Mentor and Cadence, Xilinx provides all the tools and training you need.

THE PROVEN SOLUTION. THE FAST TRACK TO SAVINGS.

Using serial technology, you can significantly reduce system costs through

fewer pins, smaller PCBs, smaller connectors, lower EMI, better signal

integrity and noise immunity. The Xilinx “Serial Tsunami”

initiative brings you simplified designs, scalable band-

width, and risk-free programmable serial solutions. For

volume production, Xilinx offers Virtex-II Pro EasyPath

devices to further your cost savings.

SERIAL DESIGN MADE EASY

Take advantage of our in-depth serial training courses, complete with

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hands-on labs, and dedicated web portal. Ride the Serial Tsunami today.

Visit www.xilinx.com/serialsolution.

The Programmable Logic CompanySM

www.xilinx.com/serialsolution©2003, Xilinx, Inc. All rights reserved. The Xilinx name, the Xilinx logo are registered trademarks. RocketIO and SelectIO, Virtex-II Pro are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc. All other trademarks and

registered trademarks are the property of their respective owners.

by Robert BielbySenior Director, Strategic Solutions MarketingXilinx, [email protected]

On May 5, 2003, Xilinx unveiled anotherkey first in the programmable logic indus-try – the RocketPHY family of 10 GbpsCMOS Physical Layer (PHY) transceivers.Designed for a wide range of applicationsand markets including MAN, WAN, LAN,and SAN, the RocketPHY family repre-sents the next milestone in our commit-ment to supporting the imminenttransition to serial signaling technologies.

The Xilinx serial I/O technologies,named the “Serial Tsunami Initiative,” arecausing a virtual tidal wave of new stan-dards to emerge, bringing you the signifi-cant benefits of lower cost, lower powerconsumption, reduced electromagneticemissions, and simplified PCB design.

The Serial Tsunami InitiativeFive years ago, it was clear that the tradi-tional approach to scaling I/O performancewas reaching its limitations; industry stan-

dards such as PCI halted its traditionalapproach of scaling bandwidth by dou-bling both bus width and frequency withthe introduction of the 64-bit, 133 MHzPCI-X node. PCB layout constraintsrestricted PCI-X to a bus width of 64 bitswhile standard single-ended signalingtechnologies capped out at 133 MHz.With the introduction of PCI Express, theindustry signaled the end of the parallelI/O era – serial signaling technologies arenow becoming mainstream.

Xilinx has responded by delivering inno-vative solutions that address these industry-wide transitions. In 1999, Xilinx led thecharge with the introduction of theVirtex™ FPGA family. The Virtex familyintroduced SelectIO™ technology, anindustry first, to support multiple I/O sig-naling standards that were programmableon a pin-by-pin basis. The Virtex familyprovided direct support for a wide range ofnew high-performance I/O signaling tech-nologies, including GTL, STTL, HSTL,and BTL. These standards were rapidlygaining market acceptance in chip-to-chipinterfacing, memory interfacing, and back-

planes, as the performance limitations ofLVTTL signaling became too great.

The benefits of the SelectIO solutionwere clear – high-performance signalingtechnologies integrated on an FPGA plat-form that allowed for direct communica-tion with the higher speed I/O interfaces.With SelectIO technology, you could sim-plify bridging between standards, eliminateexternal transceivers, improve cost, andreduce board area, all the while deliveringhigher performance I/O signaling.

Xilinx expanded upon the vision of pro-viding integrated support for high-speedI/O signaling in subsequent FPGA familieswith the introduction of the Virtex-II andthe more recent Virtex-II Pro™ families.The Virtex-II family opened up the reach ofhigh-speed I/O signaling through the inte-gration of LVDS I/Os capable of operationsup to 622 MHz using a source-synchronousclocking topology. In conjunction withRocketIO™ technology, the Virtex-II Profamily extended the I/O signaling capabili-ties to 3.125 Gbps using CML-based differ-ential serial signaling technologies withintegrated clock recovery.

A new family of 10 Gbps serial I/O transceivers dramatically cuts costs in light-speed applications. These transceivers make it possible to create unique optical connectivity designs.

New RocketPHY Transceiver Family Debuts at 10 Gbps


New RocketPHY Transceiver Family Debuts at 10 GbpsA new family of 10 Gbps serial I/O transceivers dramatically cuts costs in light-speed applications. These transceivers make it possible to create unique optical connectivity designs.

Introducing RocketPHY TransceiversThe latest in our comprehensive portfolio ofhigh-speed serial I/O solutions is theRocketPHY family of Physical Layer trans-ceivers. Designed on a standard 0.15 µmCMOS process, RocketPHY devices are thefirst Xilinx family of Physical Layer trans-ceivers that support SONET-compliant jitterand are optimized for a wide range of 10Gbps optical interconnect applications.

The RocketPHY family of low-cost,low-power CMOS transceivers consists ofthree family members that support multi-rate operation from 9.9532 Gbps to10.709 Gbps; they include aserializer/deserializer (SERDES), an inte-grated clock multiplication unit (CMU),and clock/data recovery (CDR) circuitry.The parallel interface of the RocketPHYfamily is directly compliant with XilinxVirtex-II Pro FPGAs and other industryframers and media access controllers(MACs), through XSBI and SFI-4, 16-bitdifferential LVDS interfaces.

RocketPHY FeaturesRocketPHY devices offer:

• Multi-rate 9.9532 Gbps to 10.709Gbps integrated CMOS transceiver(MUX/DeMUX, CDR, CMU)

• SONET OC-192/SDH STM-64/Telcordia compliant

– 9.9532 Gbps SONET data rate

– 155.52 MHz or 622.08 MHz refer-ence clock

– Exceeds OC-192 jitter generation,jitter transfer, and jitter tolerancespecifications, as shown in Figure 1

• SONET FEC support

– 10.709 Gbps data rate (G.709)

– 167.33 MHz or 669.325 MHz refer-ence clock

• IEEE 802.3ae 10 Gigabit EthernetStandard (Base R, W) compliant

– 10.3125 Gbps data rate

– 161.13 MHz or 644.53 MHz reference clock

• Line and diagnostic loopback modes

• On-chip CML and LVDS termination

• Seamless interfacing to Virtex FPGAfamilies and ASSPs via Versatile ParallelInterface

– Back clocking mode (622 MHz or311 MHz)

– Forward clocking mode (622 MHzor 311 MHz)

• Transmitter/receiver lock detection

• 17 mm x 17 mm, 256-ball, fine-pitch,plastic BGA package

• CMOS manufacturing process

• Power supplies: 1.8V and 3.3V

– 1.5W typical power consumption.

• 16-bit LVDS parallel interface compli-ant to OIF SFI-4 and IEEE 802.3aeXSBI (3.3V supply)

• Differential CML driver for PMDinterface

• FIFO to de-couple transmission clock

• Multi-rate 10 GHz transmit clock output

• Parallel interface bit order swapping

• Serial data polarity inversion (on transmit)

• Three transmitter reference clockmodes with clean-up PLL

– TX reference clock

– RX recovered clock (line timing)

– TX parallel input clock


RocketPHY Family Member Supported Standards Target Applications Parallel Interface

RocketPHY 10G Ultra MSATM SONET OC-192 MSA Modules XSBISDH STM-64 XFP Modules SFI 4G.70910Gbs Ethernet10Gb Fibre Channel

RocketPHY 10G SONET/SDH OC-192 SONET/SDH-based SFI 4 SDH STM-64 transmission systems,

ADMs

RocketPHY 10GbE/FC 10Gbs Ethernet Transmission equipment, XSBI10Gb Fibre Channel NICs, test equipment,

edge routers, storage, area networks

Table 1 - RocketPHY family overview

Figure 1 - RocketPHY is OC-192 jitter compliant

ApplicationsEach of the three RocketPHY devices isoptimized for specific applications asshown in Table 1. A basic applicationblock diagram is shown in Figure 2.

SONET OC-192 and SDH STM-64 In SONET/SDH operation, the trans-ceiver connects to the SONET/SDHframer via the parallel 16-bit LVDSinterface. It receives and transmitsSONET-framed 16-bit words at a rate of622.08 Mbps. The 16-bit words are con-verted from/to a serial bitstream at9.9532 Gbps. An LVPECL referenceclock of either 155.52 MHz or 622.08MHz may be used (see Figure 3).

Optical Transport Network Operations(SONET + FEC) In Optical Transport Network (OTN)operation for OC-192 applications, thetransceiver connects to the SONET/SDHframer via the parallel 16-bit LVDS inter-face. It receives and transmits SONET-framed 16-bit words at 669.325 Mbps.The 16-bit words are converted to a serialbitstream at 10.709 Gbps. An LVPECLreference clock of either 167.33 MHz or669.325 MHz may be used (see Figure 4).

10 Gigabit Ethernet – 10G Base-R and 10G Base-W Ethernet In 10G Base-R operation, the transceiv-er forms the PMA (Physical MediumAttachment), which is located below thePCS (Physical Coding Sublayer). Itreceives and transmits 64B/66B encodeddata in 16-bit words at 644.53 Mbps.The serial data rate is 10.3125 Gbps. AnLVPECL reference clock of either161.13 MHz or 644.53 MHz may beused. No frame detection or alignmentoccurs.

In 10G Base-W operation, the trans-ceiver forms the PMA, which is locatedbelow the WIS (WAN InterfaceSublayer). It receives and transmits64B/66B-encoded and SONET scram-bled data in SONET-framed 16-bitwords at a rate of 622.08 Mbps. Theoperation is the same as that describedfor SONET (see Figure 5).

XilinxXGC1120

O/E

OC-192 SONET Optical Module

SFI-4*

16-bitLVDS

9.9532 Gbps

Rx

Tx O/E

SONETFramer

16-bitLVDS

*SFI-4 = SERDES Framer Interface per the Optional Internetworking Forum (OIF) for OC-192 SONET systems. Uses a 622.08 Mbps data rate on 16 LVDS channels.

XilinxXGC1120

O/E

OC-192 SONET + FEC Optical Module

SFI-4*

16-bitLVDS

10.70926 Gbps

Rx

Tx O/E

FEC/Framer

16-bitLVDS

*SFI-4 = SERDES Framer Interface per the Optional Internetworking Forum (OIF) for OC-192 SONET systems. Uses a 669.325 Mbps data rate on 16 LVDS channels.

XilinxXGC1120

O/E

10GbE Optical Module

XSBI*

16-bitLVDS

10.3125 Gbps

Rx

Tx O/E

10GBase-RPCS/MAC

or10GBase-W

VAS/PCS/MAC

16-bitLVDS

*XSBI = 10 Gbps 16-Bit Interface per IEEE 802.3a for 10 GbE systems. Uses a 644.53 Mbps data rate on 16 LVDS channels.

XilinxXGC1120XFP

16-bitLVDS

Rx

Tx

SONETFramer

10GbE MAC10GFC MAC

16-bitLVDS


RocketPHYO/E Physical

LayerTransceiver

FramerMAC

Virtex-II Pro

Virtex-IIInterfacing

Virtex-II Interfacing

Virtex-II ProInterfacing

NPUVirtex-II Pro

Control Plane

Backplane

Memory

Virtex Interfacing

Virtex-IIInterfacing

Figure 2 - Basic RocketPHY application block diagram

Figure 3 - SONET OC-192 and SDH STM-64 Application

Figure 4 - Optical Transport Network Operations (SONET + FEC) Applications

Figure 5 - 10 Gigabit Ethernet: 10G Base-R and 10G Base-W Ethernet applications

Figure 6 - XFP and MSA module applications

10G Fibre Channel and Proprietary DesignsThe RocketPHY transceivers support pro-prietary applications with serial data ratesranging from 9.6 Gbps to10.709 Gbps, inaddition to emerging standards such as10G Fibre Channel. The transmit referenceclock can be either R/16 or R/64 where Ris the serial data rate.

XFP – The Future of 10 Gbps Optical NetworkingOne of the latest innovations occurring inthe optical module market is the transitionfrom the relatively large, costly, 300-pin,multi-source agreement (MSA) opticalmodules to a new, lower-cost, smallerform-factor optical transceiver named“XFP” for 10 Gbps Form-Factor Plugable.

The XFP standard promises to offer halfthe size, one-third the cost, and one-fifththe power requirements; it will serve tofurther fuel the 10 Gbps optical revolu-tion, as seen in Figure 6. XFP not onlydefines the dimensions of the optical mod-ule itself, but also a standard signalinginterface called XFI, ensuring interoper-ability with industry-standard PhysicalLayer transceivers. The RocketPHY familyis compatible with both XFP and MSAoptical modules standards (see Figure 7).

Virtex-II Pro X – RocketPHY Technology Built-inXilinx will also introduce the new Virtex-II Pro X architecture in May 2003, withintegrated 10 Gbps RocketIO SERDESsupport. The Virtex-II Pro X SERDES

provides continuous serial signaling sup-port from 2 Gbps through 10 Gbps withan enhanced Physical Coding Sublayer(PCS) and CMU supplying extended sup-port for telecom-based applications,including those requiring OC-48 SONETjitter compliance. Combined with thenew RocketPHY family, Xilinx offers thebroadest range of serial solutions address-ing the various connectivity hierarchiesfor a wide range of markets and applica-tions (see Figure 8).

ConclusionOver the past five years, it has become evident that core logic performance has far exceeded the capabilities of tradi-tional LVTTL signaling technologies.Furthermore, the approach to scaling I/Obandwidth by simultaneously increasingfrequency and bus width has also reachedits limitations, principally because of bothcost and technical feasibility.

Through the introduction of innova-tive products such as the Virtex FPGAfamily and its subsequent generations,Xilinx has been able to provide solutionsthat address the ever-changing landscapeof I/O signaling and interfacing. Themore recent trend in the industry, serialsignaling, has not gone unnoticed; withthe introduction of Virtex-II Pro andVirtex-II Pro X FPGAs, Xilinx hasdemonstrated technical and market lead-ership in delivering seamless solutions forserial signaling applications ranging from622 Mbps to 10 Gbps.

Now, with the introduction of theRocketPHY family of Physical Layer trans-ceivers, Xilinx is further expanding itsrange and breadth of serial solutions bydelivering the FPGA industry’s first 10Gbps, OC-192 SONET-compliant trans-ceiver optimized for multi-market opticaltransceiver applications. With this line up,Xilinx is delivering a suite of serial solu-tions that are unparalleled in the industry.

For additional product details, seewww.xilinx.com/phy/.

For applications, block diagrams,demonstration boards, intellectual proper-ty, and other solutions for RocketPHYapplications, see www.xilinx.com/esp/.


XAUI

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NETWORKING

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Figure 7 - 300 MSA vs. XPF cost comparison

Figure 8 - Seamless serial solutions from 622 Mbps to 10 Gbps

by Derek R. CurdAPG Technical Marketing ManagerXilinx, [email protected]

The shift to high-speed serial I/O technol-ogy has enabled designers to push the per-formance of systems well beyond that oftraditional parallel bus-based architec-tures. Multi-gigabit serial links are capableof transmitting data at substantiallygreater speeds, with significantly lowerpower, and with a fraction of the pinsrequired for system-synchronous (com-mon clock) or source-synchronous (clockforwarding) schemes.

However, with all the advantages ofserial I/O technology, you must address anumber of new design challenges whenintegrating high-speed serial links intoyour design. Board design, for example,becomes a more involved issue when deal-ing with signal integrity and transmissionline effects of multi-gigabit serial signals.In addition, standards compliance andinteroperability testing require new char-acterization techniques and additionalresources during the development process.

The Xilinx “Adaptive I/O” solution forthe Virtex-II Pro™ family of PlatformFPGAs gives you the power and flexibilityto meet these serial I/O design challengeshead-on. Leveraging the combination ofthe RocketIO™ multi-gigabit trans-ceivers (MGTs) and the IBM PowerPC™405 embedded processor core, theAdaptive I/O solution gives you the per-formance and system-level managementfunctions you need to accelerate the devel-opment of your high-speed serial design.

The solution is delivered in the formof three pre-engineered reference designsthat can be easily integrated into yourexisting design environment to providerapid prototyping ability, enhanced char-acterization and diagnostic testing, andin-system performance optimization ofyour high-speed serial links. Although thereference designs take advantage of theintegrated processor in the Virtex-II Prodevice, no PowerPC or C-programmingexpertise is required to use the AdaptiveI/O solution.

The Xilinx “Adaptive I/O” solution enables rapid prototyping,enhanced diagnostic testing, and in-system performance optimization for high-speed serial I/O designs.

Accelerate Your Multi-Gigabit Serial Design


Multi-Gigabit Signal IntegrityDesigning with multi-gigabit serial I/Otechnology requires greater attention toissues that affect signal integrity, such asattenuation, noise, and reflections. Atmulti-gigabit frequencies, board tracesbehave like transmission lines, introducingthe need for a more detailed understandingof the signal topologies and characteristicsof the transmission medium. Jitter effects,dielectric losses, and impedance matchingissues must all be carefully considered toensure reliable data transfer across a seriallink at the intended baud rate.

Serial I/O technology provides benefits atvarious levels within a system, enabling thecreation of high-speed links from chip tochip, board to board, and box to box.Clearly, signal topologies and even the trans-mission medium can vary significantlydepending on the type of application. Thecomplexity of the design challenge and levelof signal integrity analysis required will alsovary accordingly. For example, transmittingover several feet of coaxial cable presents dif-ferent challenges than transmitting over afew inches of FR4 laminate board.

Consider the example of a serial back-plane (Figure 1) in which the distance a sig-nal must travel can change substantiallydepending on which slot a board is pluggedinto. The signal attenuation and determin-istic jitter imposed on the longer backplanetrace will be greater than on the shortertrace. In scenarios such as this, it is oftendesirable to modify or “tune” the drivecharacteristics of the MGT transmitter tomatch the characteristics of a particular signal path, ensuring the highest possiblesignal quality and reliable recovery of thedata at the receiver end.

Solving the Backplane DilemmaThe RocketIO MGTs in Virtex-II Prodevices include many advanced features tosimplify the development of serial I/O-basedsystems. The MGT blocks are composed oftwo distinct sub-blocks (Figure 2): the phys-ical media attachment (PMA) block and thephysical coding sub-layer (PCS) block. ThePMA is responsible for the serialization anddeserialization (SERDES) of the data streamas well as the actual physical interface for the

table through the RocketIO primitiveattribute TX_DIFF_CTRL. The peak-to-peakswing at the output of the MGT transmit-ter can be varied from approximately 400mV to 800 mV (800 mV to 1600 mVpeak-to-peak differential) in increments of100 mV. Adjusting the swing control levelgives you the flexibility to meet the require-ments of a wide range of serial I/O stan-dards and ensures interoperability withmany other devices over a variety of signallengths and topologies.

Programmable Pre-EmphasisHigh-speed serial signals experience signifi-cant attenuation (signal loss) due to the “skineffect” and dielectric losses of the transmis-sion medium, particularly over longer dis-tances. Pre-emphasis is a technique wherebythe highest-frequency components of theserial signal are boosted to compensate for

these losses, significantly extending the dis-tance the signal can be reliably transmittedover a given type of conductor.

Virtex-II Pro MGTs have four levels ofprogrammable pre-emphasis (from 10% to33%) selectable through the RocketIOprimitive attribute TX_PREEMPHASIS. Atmaximum pre-emphasis, RocketIO MGTsare capable of transmitting a 3.125 Gbpsserial signal error-free over more than 40”of standard FR4 printed circuit boardmaterial (Figure 3).

The Adaptive I/O solution solves thebackplane dilemma by giving you the abil-

MGT transmitter and receiver. The PCSinterfaces with the FPGA fabric and man-ages encode/decode functions, clock syn-chronization, clock correction, and channelbonding operations.

Among the list of other commonSERDES functions, there are two pro-grammable features contained within theMGT blocks to optimize transmission overa wide variety of signal topologies andtransmission media:

• Programmable differential swing control

• Programmable pre-emphasis.

Programmable Differential SwingControlVirtex-II Pro MGTs have five levels of pro-grammable differential swing control selec-


Short Trace

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Figure 1 - The backplane distance dilemma

Figure 2 - RocketIO multi-gigabit transceiver

ity to dynamically adjust the programma-ble swing control and pre-emphasis levelsof the MGTs in response to changing sig-nal topologies, while leaving the rest of theFPGA design unchanged. For example,referring again to Figure 1, the Virtex-IIPro MGT transmitter can be automaticallyconfigured to have different swing controland pre-emphasis settings in response tothe changing trace length associated witheach slot location.

Application Note XAPP660 (www.xil-inx.com/xapp/xapp660.pdf), with completereference design files, provides you with anentirely self-contained solution for dynam-ic configuration of the MGT swing controland pre-emphasis attributes (Figure 4). ThePowerPC 405 core is used to performreconfiguration of the MGT attributes viathe internal configuration access port(ICAP), an interface similar to SelectMAP,which allows the FPGA configuration logicto be accessed over general interconnectsinside the device.

After power-up and initial configura-tion with a base FPGA design, thePowerPC processor reads a 4-bit slot IDregister to determine the swing controland pre-emphasis settings that should beassigned to each MGT for the given sig-nal topology. The PowerPC core thenmodifies the MGT attributes by manag-ing a partial reconfiguration of select con-figuration bits over the ICAP interface,leaving the rest of the FPGA designunchanged.

The slot ID can be a static code deliv-ered from the backplane or a dynamic valuedriven by internal logic or another device.

The MGT attribute settings for each slotID value are predefined with simple modi-fications to a “C” file array structure. Theend result is that the MGTs can adapt to upto 16 different signal topologies automati-cally and provide optimal signal transmis-sion without the need for separatebitstreams. The use of the PowerPC 405core to manage the MGT attribute modifi-cations results in a very resource-efficientdesign. The total solution consumes only67 slices (about 2% of an XC2VP4 device),and can thus be easily integrated intoalmost any Virtex-II Pro design.

Enhanced Characterization and Diagnostic TestingIn addition to managing the signal integri-ty aspects of multi-gigabit serial I/Odesign, significant time and resources canbe spent on standards compliance, inter-operability testing, and general characteri-zation of the serial links during thedevelopment process. Furthermore, multi-gigahertz oscilloscopes, bit-error rate test(BERT) modules, and other required testequipment can quickly consume a goodportion of your program budget.

The Adaptive I/O solution again offers a pre-engineered solution for simplifying the development and reducing the overall cost of MGT-based designs.Application Note XAPP66 (www.xilinx.com/xapp/xapp661.pdf), with associated referencedesign files, describes the Xilinx bit-error ratetest (XBERT) module for enhanced charac-terization and diagnostic testing (Figure 5).The XBERT module includes a pattern gen-erator capable of generating eight differentpseudo-random bit sequence (PRBS) pat-terns as defined by ITU-T (InternationalTelecommunication Union-StandardizationSector) Recommendation 0.150. It alsoincludes a built-in error detector andframe/bit-error counters for tracking thetotal number of transmitted frames and totalnumber of associated bit-errors.

The XBERT module is controlled andmonitored by the PowerPC core over theprocessor local bus (PLB) interface. Inaddition, the PowerPC core reads the statusof the frame and bit-error counters andthen transmits this information to the

PLB-attached universal asynchronousreceiver transmitter (UART). Using a stan-dard serial cable connection to a PC, theUART can communicate with a simple PCterminal program such as Hilgraeve Inc.’sHyperTerminal, giving you the ability tocontrol the bit-error rate testing from yourkeyboard and see the test results continu-ously updated on your PC screen.

Using the results from the XBERTmodule, a practical bit-error rate (forexample, < 10-12) can be calculated foryour multi-gigabit serial links. And,because the XBERT is a soft implementa-tion built from FPGA logic resources, itcan be used for characterization or diag-nostic testing and then removed from thefinal design. The XAPP661 referencedesign solution gives you the ability toperform sophisticated bit-error rate test-ing more efficiently and at a fraction ofthe cost of other solutions.

Putting It All TogetherThe XAPP660 reference design provides theability to automatically adapt the MGTtransmitter attributes to meet changing sig-nal topologies or other system requirements.And XAPP661 enables enhanced character-ization or diagnostic testing of serial linkswith an interactive user interface.

However, the Adaptive I/O solutiontakes things one step further. ApplicationNote XAPP662 (www.xilinx.com/xapp/xapp662.pdf) combines the XBERT char-acterization module of XAPP661 with theMGT partial reconfiguration capability ofXAPP660 to provide a complete MGTdevelopment platform for real-time per-formance optimization, adaptive systemcalibration, and field diagnostic testing.

The XAPP662 reference design adds anICAP controller interface to the internal PLBof the system described in XAPP661, addingthe ability to modify the MGT differentialswing control and pre-emphasis settings dur-ing characterization and diagnostic testing(Figure 6). Using a standard intellectualproperty interface (IPIF) module availablefrom Xilinx, the ICAP controller module iseasily integrated into the PLB-based system.

With this solution, you have the powerto perform an iterative loop, alternating


Figure 3 - 3.125 Gbps over 44” of FR4 with 33% pre-emphasis

between MGT attribute changes and bit-error rate testing through a command lineinterface on your desktop PC. The endresult is a complete solution for real-timeperformance optimization and reliability

testing of your MGT serial links.Portions of the XAPP662 reference

design can also be easily integrated intoyour final design. The IPIF-to-ICAP inter-face module, for example, can be used in

any PLB- or OPB- (on-chip peripheral bus)based system to provide MGT attributereconfiguration under control of thePowerPC core. This can be a preferred solu-tion to XAPP660 for systems that alreadyincorporate a PLB or OPB bus structure. Inaddition, any in-system communicationlink can interface to the on-chip UART,introducing the possibility of remote systemupgrade or field diagnostic testing.

Managing the Product Life CycleTogether, the three components of theXilinx Adaptive I/O technology provideyou with solutions to help you manage yourhigh-speed serial systems in all phases of theproduct life cycle. In the developmentphase, the ability to perform real-time per-formance optimization with interactivecontrol over MGT attributes and theXBERT module provides you with rapidprototyping and efficient characterization.

In your fielded production design, theMGT partial reconfiguration controller ofXAPP660 or XAPP662 gives you thepower to automatically adapt your MGTtransmitter characteristics in response todifferent signal topologies or changing sys-tem environments on the fly. This ensuresthat every link is optimized for perform-ance and minimum bit-error rate withoutthe need for multiple bitstreams or externalcomponents.

Lastly, the Adaptive I/O solution givesyou the ability to perform in-field systemcalibration or diagnostic testing to ensureyour end product is maintained for maxi-mum reliability and performance.

ConclusionThe Xilinx Adaptive I/O solution enablesrapid prototyping, enhanced characteriza-tion, and in-system performance optimiza-tion of your multi-gigabit serial I/Odesigns. The combination of RocketIOMGTs and the IBM PowerPC 405 coreprovides you with a complete platform fordeveloping, optimizing, and deliveringworld-class, high-speed serial solutions.

To learn more about the three referencedesigns that make up the Adaptive I/Osolution, visit www.xilinx.com/search/vsearch.htm.


+ +- -

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Figure 4 - Dynamic reconfiguration of MGT differential swing control and pre-emphasis attributes

Figure 5 - XBERT module for enhanced characterization and diagnostic testing

Figure 6 - Complete platform for real-time optimization of MGT serial links

by Bill OkuboSolutions Marketing Manager, Global ServicesXilinx, [email protected]

With the tremendous increase in connec-tivity bandwidth requirements, ourindustry is experiencing a rapid moveaway from parallel interface architecturestoward high-speed multi-gigabit serialstandards.

Serial interfaces will ultimately bedeployed in nearly every electronic productimaginable – including chip-to-chip inter-facing, backplane connectivity, systemboards, and box-to-box communications.Serial interfaces reduce system costs, sim-plify system design, and provide scalabilityto meet new bandwidth requirements.These emerging technologies sometimesrequire special knowledge in order to createhigh-speed serial I/O solutions – skills andexperience that may be new to traditionalprogrammable logic designers.

Service organizations play an increasing-ly important role in providing the knowl-edge about programmable systems neededto solve high-performance architecturalchallenges.

To ensure the success of design teams,while keeping overall cost down, XilinxGlobal Services offers a complete portfolioof services for the Virtex-II Pro™ FPGAfamily. Xilinx Education Services, XilinxDesign Services (XDS), and support.xilinx.com all provide the experience andskills to help you successfully develop high-speed serial solutions and embedded sys-tems, as well as FPGA logic design.

Designing with RocketIO TransceiversHigh-speed serial I/O channels can replaceparallel buses in many systems and willresult in lower overall costs – if designedcorrectly. These channels can significantlyreduce board space and simplify boarddesign while freeing I/O resources for otherapplications. To teach you how to createthese high-speed serial designs efficiently,Xilinx provides training designed to reducesignificantly the rigors of getting up tospeed on this new technology.

High-Speed Serial Interface Design: Learn Fast, Finish Faster


High-Speed Serial Interface Design: Learn Fast, Finish Faster Xilinx Global Services provides you with the skills, courses, and information needed to meet the design challenges of FPGA programmable systems that interface embedded processors with multi-gigabit serial transceivers.

Xilinx Global Services provides you with the skills, courses, and information needed to meet the design challenges of FPGA programmable systems that interface embedded processors with multi-gigabit serial transceivers.

Designing with RocketIO Multi-Gigabit Transceivers is a two-day coursethat teaches how to fully utilizeRocketIO™ transceivers in Xilinx Virtex-II Pro FPGAs. By mastering the details ofhigh-speed serial designs, you learn todevelop fast and efficient serial interfacesthat will operate flawlessly. In addition toclassroom instruction, more than half ofthis class is taught in the lab, where youlearn how to efficiently synthesize, imple-ment, and debug designs.

Designing with RocketIO Multi-Gigabit Transceivers teaches you the skillsnecessary to:

• Fully utilize the ports and attributes ofRocketIO transceivers

• Effectively use advanced RocketIO fea-tures such as CRC, channel bonding,clock correction, comma detection,8b/10b encoding, programmable ter-mination, and pre-emphasis

• Use the Architecture Wizard to instan-tiate RocketIO primitives in designs

• Achieve compatibility with high-speedI/O standards using RocketIO

• Recognize and understand the datastreams of popular communicationsstandards such as Gigabit Ethernet andPCI Express.

Xilinx Design Services Has RocketIO ExpertiseDesigners who work with Virtex-II ProFPGAs need to know with certainty thatthe RocketIO multi-gigabit transceivers(MGTs) will perform according to theirspecific requirements. To allow the meas-urement design parameters such as bit-errorrate, latency, and resynchronization time,and physical-layer characterization involvesthe building and reuse of embedded hard-ware and software systems on Virtex-II ProFPGAs. XDS has experience with andaccess to various Xilinx characterizationboards to carry out such measurements.

Experience with partial reconfigurationof RocketIO MGTs is also importantwhen you’re designing Virtex-II ProFPGAs. For example, electrical transmis-sion characteristics commonly vary fromserial link to serial link depending on the

you use, such as data sheet updates forVirtex-II Pro FPGAs.

Tech Tips for RocketIO is a new sup-port tool that includes information such as:

• RocketIO FAQ

• Documentation about RocketIO

• Top Answers for RocketIO.

ConclusionBefore you start your next high-speedserial design, save yourself time and effortby taking advantage of the skills andexperience offered by Xilinx GlobalServices. Learn more about the servicesavailable for RocketIO MGTs at:www.support.xilinx.com/support/gsd.

The course description for Designingwith RocketIO MGTs is available at:www.support.xilinx.com/support/training/abstracts/rocketio.htm.

For information about the serial I/Oexpertise of Xilinx Design Services, see:www.support.xilinx.com/xds.

RocketIO Tech Tips are available on support.xilinx.com at: www.support.xilinx.com/xlnx/xil_tt_home.jsp.

distance of the link. Partial reconfigura-tion offers you a way to avoid storing mul-tiple bitstreams on a system, allowing eachsystem’s RocketIO configuration to bepersonalized using either on-boardswitches or software control. Partialreconfiguration can also be used to switcha RocketIO channel from one physicalstandard to another without any servicedisruption on the unaffected channels.

In addition to providing partial recon-figuration under software control, XDS hasembedded software expertise to help youdeliver fully integrated and dynamicallyconfigurable systems. XDS can help youdevelop the high-level communicationsprotocol for FPGA programmable logicand embedded software.

Web-Based Tech Tips A comprehensive support resource isessential to fast design cycles and first-timesuccess for a new serial I/O design.Available 24/7, support.xilinx.com hasonline information on the latest down-loads, techXclusives, and other recent sup-port-related news. MySupport.xilinx.comcan be personalized so that you see onlythe information related to the devices that


by Xcell Staff

More than 500 designers and engineershave downloaded the Xilinx RocketIO™Design Kit for Cadence Design Systems’SPECCTRAQuest™ design and analysisenvironment for high-speed digital sys-tems. Customers have clearly been pleasedwith the kit’s results in shortening time-to-market and reducing costs.

The design kit helps reduce the timeneeded to implement Virtex-II Pro™RocketIO transceivers because it takesadvantage of concurrent design efficienciesusing technologies that address silicon,package, and board design.

The kit acts as an electronic blueprintthat enables you to create, implement,

and verify gigahertz-speed serial linksquickly. Operating within the CadenceSPECCTRAQuest Signal IntegrityExpert environment, the kit is a provenapproach for characterizing the interac-tions between the Xilinx Platform FPGAand the rest of the system.

The design kit is the result of analliance between Xilinx and Cadence tohelp you exploit the capacity and perform-ance of the Xilinx Virtex-II Pro FPGAfamily. “Our customers’ ability to quicklydesign-in the Virtex-II Pro Rocket IOtechnology is critical,” said Rich Sevcik,senior vice president and general managerof FPGA products at Xilinx. “By workingwith Cadence, we can minimize thedesign-in time for our mutual customers.”

Unique Features The RocketIO Design Kit for SPECCTRA-Quest allows you to develop optimal con-straints for PCB systems. The constraintsdrive the PCB floorplanning, routing, andverification process. The RocketIO DesignKit for SPECCTRAQuest includes:

Price and AvailabilityThe RocketIO Design Kit forSPECCTRAQuest is provided free to Xilinxcustomers who have signed the appropriatenon-disclosure agreement. More informa-tion is available at www.support.xilinx.com/.The Cadence SPECCTRAQuest SignalIntegrity Expert product starts at a U.S. listprice of $24,200 for a one-year license. Forpricing outside of North America, contactyour local Cadence office or distributor.More information regarding other SerialTsunami design resources is available atwww.xilinx.com/serialsolution.

Instead of taking weeks, you can now create and verify gigahertz-speed serial links on PCBs in days.

Kit for Cadence SPECCTRAQuest Tools Speeds RocketIO Designs


• Ready-to-simulate system-level topologies for typical use of the device on theboard/system

• Verified I/O buffer models

• Large package model

• Test-bench and correlation data

• Connector models for backplane applications

• Device-specific scripts and tools to evaluatesimulation results

• Instructional video describing how to getstarted with the design kit.

It’s a never-ending cycle: Every new generation of processors and

buses means a new need for speed—in your customers and in you.

As edge rates go sub-nanosecond and schedules get shorter, signal

integrity problems get tougher just when you need to solve them

faster and with fewer compromises. Perhaps we can help.

Working with designers around the world, we’ve seen scope probe

loading lead many people down a wrong road. Probe impedance

varies with frequency, so it can cause errors in bias, amplitude,

offset, rise time and propagation delay. The circuit may even stop

or start whenever you connect the probe.

You can reduce or eliminate these problems with an active probe, which

provides high resistance, low capacitive loading, a flat response—

and a more accurate view of what’s really happening in your circuit.

Sharing tips like this is just one of the ways Agilent can help you

find the causes of signal integrity problems now and design them

out next time.

There’s more where this came from at www.agilent.com/

find/moresi, where you can download application notes

about probing, normalization, de-embedding and more,

order a CD-ROM, and attend a series of FREE signal

integrity eSeminars.

Eye displays in a logic analyzer can show voltage and

time data from multiple channels simultaneously, helping

you spot sub-nanosecond problems in much less time

than conventional methods.

©2002 Agilent Technologies ADEP3471209

good information,right under your nose.

u.s. 1-800-452-4844, ext. 1000canada 1-877-894-4414, ext. 7728

www.agilent.com/find/moresi

by Chris SullivanDirector of Strategic AlliancesCeloxica, [email protected]

Milan Saini Technical Marketing ManagerXilinx, [email protected]

Okay, so none of us will claim to beEinstein, but programmable systemdesign might be the next developmentchallenge we face.

With the advent of the Xilinx Virtex-IIPro™ Platform FPGA and theMicroBlaze™ soft processor, we now haveaccess to unrivalled levels of product flexi-bility and performance. This technology –for the first time – enables us to partitionand re-partition systems between hardwareand software at any time during the devel-opment cycle. We can even re-partitionthe hardware and software mix after theproduct has gone to market. This com-plete reprogrammability means the systemcan be optimized over and over again.

But for design teams looking to usethis powerful technology, system designcan be a challenge. Exploring whether adesign is even feasible can cost manymonths of time, effort, and expense, letalone finding the optimal design. And ifsystem verification does not begin rightfrom the start, projects can miss theirspecifications or take too long to get tomarket – reducing your ability to com-pete, your business credibility, and your all-important bottom line. It’s adesign headache you don’t need.

Celoxica and Xilinx have partnered to fine-tune software-compiled system design for the benefit of designers using Virtex-II Pro and MicroBlaze programmable systems.

Software-Compiled System Design Optimizes Xilinx Programmable Systems


We cannot solve our problems with the same thinking we used when we created them. – Albert Einstein

Meeting the Design ChallengeA remedy for this headache is thesynergy of software-compiledsystem design and programmablesystems technology. Software-compiled system design is amethodology that provides aseamless bridge between hard-ware and software (Figure 1). Itenables the system partition, ver-ification, and hardware/softwareco-design to be driven directlyfrom the system specification.Software-compiled system designwas specifically developed forprogrammable systems and pro-vides an efficient, cost-effective,and quality driven co-designsolution.

Software-Compiled System DesignAt the heart of software-compiled system design is theprinciple of providing a directlink between the programmableplatform and the originallydefined system functionality.This provides the necessary sys-tem verification flow and offers confidence tothe designer who wants to fully explore thedesign space – pushing the envelope of designinnovation and product differentiation.

The methodology also deploys novel technology that permits more informed andflexible hardware/software partitioning. Thisenables tradeoff analysis, partition and re-partition at any stage in the design, and byusing higher level languages (HLLs) for bothhardware and software design, the methodolo-gy allows the system specification to be writtenin a form that both teams can immediately use,without costly and time-consuming rewrites.

So Prove ItTo demonstrate the capabilities of software-compiled system design, Celoxica and Xilinxpartnered to undertake the co-design of aJPEG 2000 codec (compressor/decompres-sor) for implementation in a Virtex-II ProFPGA. In particular, we wanted to addressthe design challenge of system partitioning,co-verification, and the easy integration ofhardware and software.

• Demonstrate a complete system verification flow

• Deliver competitive Qualityof Results (QoR)

• Exceed time-to-market expectations

• Support design re-use strategies

• Maximize current EDA and IP investments.

Project PlanPhase 1: Profile and verify

Phase 2: Partition and verify

Phase 3: Design and verify

Phase 4: Implement and verify

Tools• Celoxica Nexus PDK• Celoxica DK Design Suite• Wind River Xilinx Edition

toolset• Xilinx ISE 5.1i

Phase 1: Profile and VerifyA multitude of applications can benefitfrom hardware acceleration and productflexibility. To demonstrate this, we selectedJPEG 2000; our starting point for thedesign was the C specification code.

To drive our system verification flow, weran the specification code through anappropriate target – in this instance theIBM PowerPC™ 405 GP. From this wesimulated and verified the functionality ofour system and established a test benchthat remained constant and consistentthroughout the design.

We then began code profiling to estab-lish where our program spent its time anddetermine which functions called otherfunctions during execution. We foundprofiling was useful, as it quickly identi-fied the functions in a program that wereprocessor hungry or compute intensive.That made them possible candidates foroffload into the FPGA fabric. However,the profiling does not analyze dataflowbetween hardware and software, nor burst

JPEG 2000 is a standards-based imagecoding system that uses state-of-the-artcompression techniques based on wavelettechnology (Figure 2). Its architecturelends itself to a range of uses from con-sumer electronics, such as digital cameras,to medical imaging, remote sensing, sur-veillance systems, and scanners.

Project Specifications• Maximize overall system performance

• Innovate and differentiate from thecompetition

• Demonstrate an efficient and effectiveco-design environment

• Use software specification as a startingpoint for system design

• Improve communication betweenhardware and software design teams

• Simplify partitioning and migration ofcode between software and hardwarefor better overall Quality of Design(QoD)


Figure 1 - Software-compiled system design flow

length or frequency, so designer interventionis mandatory to understand the dynamics ofour hardware/software interaction.

Using Wind River’s WindView™ visual-ization and diagnostic tool, we determinedthat the DWT (discrete wavelet transform)and Tier 1 encoder were the processor-inten-sive functions, consuming 87% of processingtime (Figure 3). We selected them for furtherscrutiny and tradeoff analysis.

Phase 2: Partition and Verify Validating the system partitionagainst the requirements of thedesign specification is cardinal inprogrammable system design.Typically the system designermaps a system-level architectureinto specific hardware and soft-ware components, making directreference to the project specifica-tion and factors such as compo-nent availability, cost, andtechnical feasibility.

The consequences of the sys-tem partition cascade through thedesign flow to physical implemen-tation and final system perform-ance is greatly dependent uponpartitioning decisions. It makeslittle sense to invest time, money,and effort optimizing and refiningan incorrect partition – it is inher-ently sub-optimal.

Uniquely, software-compiledsystem design provides the designerwith a flexible partitioning capabil-ity that permits partition and re-partition at any stage in the designprocess. Moreover, it is linked to averification flow that enables the

designer to confidently explore and innovatein the design space, analyzing hardware/soft-ware tradeoffs, and identifying the optimalsystem partition for the best QoD.

Facilitating this is the data streamingmanager (DSM), a portable co-design API(Figure 4) supplied with Celoxica’s DKDesign Suite. Developed specifically forprogrammable system partitioning and

hardware/software integration, the DSMallows the designer to iteratively explore,test, and verify multiple partition alterna-tives. The designer can quickly create andeasily move ports that are used to send databetween the software and hardware byusing the API standard (Figures 5 and 6).As each option is explored, the designer canverify the partitioning with the softwareused as a test bench throughout the project.

In our project, the DSM validated theprofiling information determined in Phase1 of our design flow. It helped analyze thedata flow and the burst length and fre-quency between our hardware and soft-ware, and fine-tuned the partition to meetthe project’s criteria. Moreover, the DSM’sinherent portability meant the designcould be repartitioned at any stage in thedesign flow, redefining the system archi-tecture and easily accommodating late

specification changes.

Phase 3: Design and Verify With the optimal partition deter-mined and verified, we began thedesign optimization phase of ourproject. Software-compiled systemdesign makes use of HLLs for bothhardware and software design.HLLs allow the system specifica-tion to be written in a form thatboth the hardware and softwareteams can immediately use – with-out costly and time-consumingrewrites. Additionally, HLLs sim-plify the migration of code betweenhardware and software. Becausethere is a common language baseand common level of abstractionbetween the hardware and software,there is improved communicationand shared understanding betweenthe development teams.

As we did in our partitioningphase, we used the DSM through-out the design optimization phase.The DSM provided a functionallyaccurate simulation environmentthat allowed our hardware and soft-ware to interact – keeping themconnected throughout design opti-mization (Figure 7).


100100001110010CodedImage

Tier-2 Encoder

Tier-1 Encoder

RateControl

RGB to YUVConversion

WaveletTransformPre processingOriginal

Image

Quantization

Handel-C Application Handel-C Application

Hardware DSM Library

Software DSM Library

Hardware Bus Controller

Software Bus Controller

Software Application Software Application

FPGA

Processor

Interface

Figure 2 - Top-level block diagram for JPEG 2000 operation

Figure 3 - WindView trace ofentire JPEG 2000 algorithm

Figure 4 - DSM portable codesign API

The software was run as a native exe-cutable on the PPC 405 GP, and thehardware was run using the simulationand debugging capability of Celoxica’sDK Design Suite. We used a utility pro-gram to monitor the data passingbetween the applications to assist withdebugging. Because all of the API func-tions were provided, this allowed com-plete system development to begin –without the development platform beingavailable. Once we got it working, theapplication was easily transferred to the target platform for final testing. Co-simulation between hardware and soft-ware was made possible by connectingDK with the Tornado™ environmentfrom Wind River (Figure 8).

As our system specification wasdescribed in ANSI-C, we progressed ourdesign in ANSI-C and used hardware lan-guage extensions defined in Handel-C todescribe our hardware. These hardwareextensions enable, for example, efficientcontrol over area, timing, clocks, RAMs,ROMs, and interfaces.

Combining multiple DSM calls, wemade optimizations to the software. Andwe applied hardware optimization tech-niques, such as increasing parallelism,replacing for() loops with while() loops,pipelining, and syntax duplication.

Specification ChangeAt this stage in the design, a specificationchange was introduced. A novel liftingalgorithm was developed that performs atwo-dimensional DWT and thus providesfaster processing time. The algorithm wasreadily available as a HDL IP block, andwe decided, with respect to design timeand maximizing IP investment, to inte-grate the IP into the design as a blackbox. The integration was simplified byusing the interface declaration availablein Handel-C for connecting third-partyIP into a software-compiled systemdesign flow (Figure 9).

Phase 4: Implement and VerifyImplementation to the target platform wassimplified by using the platform abstractionlayer (PAL). The PAL shields designers from


my_32bit initialize_coder (mq_coder_state *mq_coder){

macro proc initialize_coder (mq_A, mq_B, mq_C, mq_CT){

par // execute statements in parallel{

mq_A = 0x00008000;mq_C = 0x00000000;

if (mq_B == 0xFF) mq_CT = 13;else mq_CT = 12;

mq_coder->A = 0x00008000;mq_coder->C = 0x00000000;

if (mq_coder–>B == 0xFF)mq_coder–>CT = 13;

mq_coder–>CT = 12;else

return 0;} }

}

Step 1: Port the software code to hardware:“initialize_coder()”, from MQ coder

Software “C” code Hardware “Handel-C” code

my_32bit DSMinitialize_coder(mq_coder_state *mq_coder){ int Count; DsmWord Values[3]; // registers for I/O to HW

// set up data to send to hardware: Value[0] = (DsmWord) mq_coder–>B;

// send data to hardware DsmWrite (PortS2H, Value,1, &Count);

// read data back from hardware DsmRead (PortH2S, Value,3, &Count);

mq_coder–>A = Value[0]; mq_coder–>C = Value[1]; mq_coder–>CT = Value[2];

return 0;}

// local registersDsmWord mq_A, mq_B, mq_C, mq_CT;

while (1){ // read mq_coder–>B from software DsmRead (PortS2H, &mq_B);

// call Handel–C macro to do the work... initialize_coder(mq_A, mq_B, mq_C, mq_CT)

// write mq_coder–>A,C,CT back to software DsmWrite(PortH2S,mq_A); DsmWrite(PortH2S,mq_C); DsmWrite(PortH2S,mq_CT);}

Step 2: Create a DSM interface to transfer and verify data:

Software “C” code Hardware “Handel-C” code

HW SW

DSM

Hardware codeoptimizationE.g., pipelining to increasethroughput

Software codeoptimizationE.g., combiningmultiple DSM callsinto single call

Figure 5 - Porting software to hardware

Figure 6 - Setting up the DSM interface to test and verify partition alternatives

Figure 7 - Functionally accurate simulation environment

Figure 8 - Co-simulation between Celoxica’s DK Design Suite and Wind River’s Tornado visualization and debugging environment

low-level hardware interfaces, easing theintegration of FPGAs with physicalresources. This is done by developing alibrary of low-level interfaces to specific plat-form resources, such as I/O or memory. Thislibrary, called the platform support library(PSL), is then accessed by the hardwareapplication on the FPGA using a simple andconsistent application programming inter-face – the PAL API (Figure 10).

The target platform was a Wind RiverSBC405GP (single board computer refer-ence design) with a Proteus FPGA daugh-ter card, effectively a Virtex-II Proprototyping platform (Figure 11). Thisdevelopment environment supported tim-ing simulation, emulation, and block opti-mization, and it was used prior to finalimplementation in a Virtex-II Pro ML300Evaluation Platform (Figure 12).

Object code was compiled into thePPC405GP under Wind River’sVxWorks™ RTOS, with the hardwareimplementation using the direct EDIF out-put generated by Celoxica’s DK DesignSuite. This EDIF netlist was optimized forthe Virtex-II Pro Platform FPGA (Figure13), ensuring maximum efficiency for bestQoR. Optionally, the DK Design Suite canalso output RTL-level VHDL or Verilog,pre-optimized for traditional synthesis toolflows (Figure 14).

ResultsThe results (Tables 1 and 2) from theCeloxica DK Design Suite were com-pared to the handcrafted VHDLauthored by a JPEG 2000 domain expert.Handel-C’s systematic and ANSI-C-likeapproach to the problem led to substan-tial savings in design time. An expertHandel-C engineer with no prior knowl-edge of the JPEG 2000 standard was ableto get the algorithm to a working hard-ware implementation in less than half thetime it took to code the VHDL.

The other key success we had was thatthe design was easily able to meet the sys-tem timing constraints. The results pro-vide clear validation that designabstraction leads to increased designerproductivity without necessarily compro-mising performance or area.

Handel-C Application

PAL-CORE

Peripheral 1 Peripheral 2

Platform Abstraction LayerApplication Programming Interface

Platform Support Library (PSL)

Board

Handel-C Application

PAL-CORE

Peripheral 1 Peripheral 2

Platform Abstraction LayerApplication Programming Interface

PAL Sim

Board

Design quickly implemented in hardware for prototyping and timing verificationDirect hardware implementation from Handel-C optimized for target devicePlatform abstraction encourages application portability and supports strategies for design re-use


Figure 9 - Interface declaration “black-boxed” HDL IP into a software-compiled system design flow

Figure 12 - Virtex-II Pro ML300 evaluation platform

Figure 10 - PAL block diagram

Figure 11 - Virtex-II Pro prototyping platform ▼

▼

ConclusionSoftware-compiled system design is aproven methodology for programmablesystem co-design. It provides a solution forsystem partitioning, co-verification, andhardware/software integration across aspectrum of design styles and applications.

For use by all members of your designteam, from the system architect to the ver-ification engineer, software-compiled sys-tem design enables code sharing betweenhardware, firmware, and software design-ers from system specification through toimplementation.

The Celoxica DK Design Suite is afully featured development toolset thatenables a complete implementation of asoftware-compiled system design. It isinteroperable with popular third-partytools and languages and provides fast co-simulation between C/C++, Handel-C,HDLs, instruction set simulators (ISSs),and modeling languages such as OpenSystemC™ and MATLAB™.

Software-compiled system designmethodology offers you compelling benefits,and it is an efficient and effective designstrategy for Xilinx programmable systems.

Celoxica 1st passSlices 646

Device utilization 6%

Speed (MHz) 110

Lines of code 386

Design time (days) 6*Lena used as testbench throughout,input bit width 12, max 1k image

*Doesn’t includepartitioning spec.

development

2nd pass546

5%

130

386

7 (6+1)

Final758

7%

151

395

7 (6+1)

ObservationsHDL800

7%

128

435

20*

Comparable

HC faster

HC quicker

Expert vs. Novice

Celoxica 1st passSlices 1.347

Device utilization 12%

Speed (MHz) 89.5

Lines of code 310

Design time (days) 10

Average cycles per code block 108

Processing time (per code block ms) 1.206

Simulation time for Lena JPEG 5 mins

Celoxica Final1.999

18%

115.5

330

12 (10+2)

108

0.939

5 mins

ObservationsHDL620

6%

76

800

30*

67.5

0.888

Hours

HDL smaller

HC faster

HC quicker

HDL faster

Expert vs. Novice

Table 2 - Rapid Handel-C implementation for performance optimization


Table 1 - Rapid Handel-C (HC) implementation for area efficiency

Figure 13 -Optimized EDIFoutput for Virtex-IIPro directly generat-ed by the DKDesign Suite

Figure 14 -OptionalVHDL/Verilogoutput from theDK Design Suiteoptimized to feedtraditional syn-thesis flows

*Doesn’t include partitioning spec. development

by Dale Riley Systems EngineerTarari, [email protected]

Traditional methods of porting algo-rithms for hardware acceleration usuallyrequire many steps that are both difficultand time-consuming. The algorithmsmust be ported to a hardware language,simulated by themselves, and then proto-typed on FPGAs.

During this prototype stage, theFPGA must also connect to the softwareenvironment. The complete task oftenrequires a team of hardware engineerswell-versed in FPGA development,another hardware engineer to develop theplatform, and a software engineer to writethe interfaces from software to hardware.In addition, software developers mustwait for the hardware to be completedand tested before integration.

Software developers can get a head starton developing and debugging software usingthe Tarari Content Processing Platform™(CPP) and the Celoxica DK Design Suite toco-simulate the algorithm and quickly con-vert new or existing C code to hardware forsignificant acceleration. Celoxica’s C-to-gates technology eliminates the languageconversion step. Tarari’s CPP eliminates theneed to understand the complexities ofinterconnects and software interfaces,enabling developers to concentrate on per-formance rather than functionality.

Hardware acceleration speeds the entire design cycle, and the combination of Tarari’s Content Processing Platform and Celoxica’s DK Design Suite makes it fast and painless.

Tarari and Celoxica Deliver Fast and Easy Algorithm Acceleration


Tarari and Celoxica Deliver Fast and Easy Algorithm Acceleration

Tarari Content Processing PlatformThe concept of hardware acceleration is asimple one: Create a piece of hardware ded-icated to completing tasks much faster thansoftware or general-purpose hardware. Thereality of creating that piece of dedicatedhardware, however, is much more complex.

Consider just a PCI interface. It has abus with several possible configurations,such as 32- or 64-bit buses, or 33- or 66-MHz clocks. During operation there aremany states and conditions to keep trackof and control. Even SDRAM has some-what complex controls. You could buyeach of these elements of the design, butthen you would have to create interfacesand control mechanisms between themand tie them all together.

All of this work has been completedwith the Tarari CPP.

Figure 1 shows a block diagram of theTarari CPP that includes:

• A half-length PCI-compliant card

• 32- or 64-bit bus width operating at33- or 66-MHz bus speeds

• 256 MB of DDR SDRAM for high-capacity global storage

• LEDs for status and debug

Xilinx FPGAs are located under the fan/heatsink/shroud assembly as shown in Figure 2.This placement ensures that the componentsdon’t overheat. The FPGAs require externalcooling because they are pushed to their per-formance limits in terms of clock speed andthere is little to no airflow to cool them.

All data flow and control logic is imple-mented on the CPC. Using DMA technol-ogy, the CPC can act as a PCI bus master,allowing data transfer between the host sys-tem memory and the onboard DDRSDRAM. The bandwidth of the DDRSDRAM is approximately four times thebandwidth of the PCI or CPE buses. Thishigh bandwidth allows the CPC to multi-plex accesses to the memory and makes itappear that multiple devices are simultane-ously accessing the memory. Finally, theCPC controls programming of the CPEsfor fast reconfigurability.

The Tarari CPP contains the entire sup-port infrastructure needed to deploy a PCIsolution, allowing you to focus on algorithmdevelopment rather than on hardware imple-mentation details. Another key advantage istime to market; using the Tarari CPP allowsyou to skip the work involved in designingthe PCI infrastructure and bypass all of themanufacturing steps as well. The card is

• 4 MB of ZBT SSRAM for high-speed,low-latency local storage

• A 2M-gate XCV2000 Virtex™-IIPlatform FPGA performing as the con-tent processing controller (CPC) that:

– Provides all connectivity between thePCI Bus, DDR SDRAM, and con-tent processing engines (CPEs)

– Dynamically reconfigures FPGAs

– Hosts core content processing logic

– Has maximum total data throughputof 4 GBps

– Supports bus-master direct-memory-access (DMA) mode.

• Two independent content processingengines (CPE) each consisting of:

– A 1M-gate XC2V1000 Virtex-IIPlatform FPGA

– Independent busses for fast algorith-mic processing and continuous oper-ation during reconfiguration

– Dynamic reconfigurability, allowingupgrades via software.

The Tarari CPP is a fully developed PCIcard with three Virtex-II FPGAs. The three


CPLD

ContentProcessing

Engine (CPE)

XC2V1000

ContentProcessing

Engine (CPE)

XC2V1000

Flash

EEPROM

DDR SDRAM256 MB

Serial

EEPROM

Temp

Sensor

ContentProcessingController

(CPC)

XC2V2000

ZBT SSRAM

1 MB

ZBT SSRAM

1 MB

ZBT SSRAM

1 MB

ZBT SSRAM

1 MB

2.128 GBps64-bit

I2C Bus

8 LEDs

8 LEDs

CPE Bus532 MBps

16-bit

266 MBps18-bit

266 MBps18-bit

CPE to CPE bus 64-bit

CPE Bus532 MBps

16-bit

528 MBps64-bit

PCI Bus

Figure 1 - Tarari Content Processing Platform block diagram

delivered to you ready for productiondeployment. Your algorithm firmware canbe downloaded to the card at runtime, andno hardware customization is required.Plug it in and start accelerating.

Development Flow The first step is to select an algorithm forhardware acceleration. Selection is usuallydone using profiling tools that identifysoftware bottlenecks. The next step is todetermine memory usage, dataflow, andsuitability of the identified code sectionsthat will be implemented in an FPGA. Thefollowing step is to estimate the size, speed,and performance metrics at each stage ofthe design cycle. With so many parametersto consider, designers increasingly relyupon hardware/software co-design, co-simulation, and prototyping as essentialelements of the development flow.

The Tarari CPP is built on the develop-ment framework shown in Figure 3 to meetthese needs. The flow emphasizes rapiddevelopment with a common C-based lan-guage for both hardware and software com-ponents. This allows maximumexperimentation and exploration of thedesign space for better quality of design.

Using this framework, you can:• Create system models directly from the

original software application and verifythe functionality and characteristics ofa system.

• Quickly identify and extract criticalportions of the algorithms as candi-dates for hardware implementation.

• Make informed partitioning decisionsfor optimum use of hardware resourcesand verify performance and function-ality in simulation.

• Perform cycle-accurate hardware simu-lations.

• Directly implement C-based hardwaredesigns onto the Tarari CPP.

This approach reduces the time it takesto design accelerated applications, thuslowering cost, improving time to market,and minimizing risks.

ApplicationsThe best candidate algorithms for hard-ware acceleration with Tarari’s CPP boardfit one or more of the following criteria:

• High operation-per-byte ratio

• Benefits from running multiple instantiations (parallel processing,multi-threading)

• Capable of being pipelined

• Takes advantage of wide data widths

• CPU execution time far exceeding datatransfer time over PCI.

Where these criteria are met, there hasbeen considerable success with FPGAsolutions for the following applications:

• Security/encryption – RSA, DES/3-DES, SHA, MD5, AES/Rijndael

• Streaming applications – video pro-cessing, pattern matching/filtering,compression/decompression

• Vector engines.

Candidate products and applicationsincorporating these basic hardware blocksinclude:

• Network security

• Media streaming

• XML/Web services accelerations

• Image processing

• High-performance computing applications.

Algorithm ExampleThe GZIP (GNU zip) algorithm is acommonly used utility that compressesand decompresses data files using the“Deflate” and other patent-free algo-rithms at www.gzip.org. The key featureof GZIP decompression is that it operateson a 1-bit wide stream of data, requiringthat all operations reading from the inputdata stream are performed sequentially.Although GZIP decompression fulfills alimited number of the algorithm selectioncriteria described above, the resultsdemonstrate that the general technique ofoffloading a CPU and exploiting algo-rithm parallelism can improve systemperformance.

Porting GZIP C Source Code to Handel-CTo reduce the time required to implementthe GZIP decompression, GNU C sourcecode was used for the example. The majori-ty of the algorithm was used with little or nomodification to provide an immediate basisfor prototyping and a controlled test frame-work in which to enhance and optimize the


Figure 2 - Tarari PCI card with three Xilinx Virtex-II FPGAs located underneath heat sink/fan shroud

algorithm. Making use of Handel-C’s simplesupport for parallelism via the par{} con-struct is an example.

The process for porting the GZIPalgorithm to hardware was to write thecode for one “module” of the system at atime in Handel-C. Note that the modulescorrespond to algorithmic stages in thedecompression algorithm, as shown inTable 1, rather than more traditionalhardware blocks.

Optimized Block Memory AccessesThe Handel-C language supports the useof block RAM by adding the specificationwith {block=1} after a RAM declaration.This specification results in using blockmemory to build the RAM and generat-ing a RAM clock at double the algorithmclock rate, which is used to implementsingle-cycle access to the block RAM.This process provides a quick route tohardware prototype for the design.

However, using the single-cycle blockRAM access limits the algorithm clockrate to half of the RAM clock rate. Someportions of the GZIP decompressionalgorithm are sequential in nature, so ahigh clock rate is desirable to achieve

maximum performance. Consequently,for this improved performance, a simpleinterface eliminated the double clockconstraint by using pipelined access tothe block RAM.

LZ77 DecompressorThe main component in the hardwareimplementation is the “sliding window,”which is 32 KB in size with byte-wideaccess. The sliding window is built using

the pipelined block RAM access macrosmentioned above. Copy operationsresulting from a length/distance pair areperformed using a pipelined loop asshown in the code in Figure 4, whichreads from one port of the sliding win-dow block RAM and writes back to theother port. This results in fast operationby processing one byte every clock cycleonce the pipeline is full.

Simulation Testing of GZIP ModulesA significant advantage of developing aGZIP decompression algorithm inHandel-C is that the simulator can be usedto test the functionality of the designbefore implementation. These simulationsare performed rapidly – a model of theentire GZIP decompression algorithm cansimulate 100 KB of compressed data in 25seconds or less on a Pentium™ III 850MHz system. During development of eachGZIP module in Handel-C, we conductedsimulations to verify their operation. Thesoftware GZIP source code was modifiedto produce test harnesses implemented asC functions called directly from theHandel-C code.

Data ThroughputGiven the maximum clock rate of thedesign to be 133 MHz – verified by usingthe Xilinx ISE 5.1i timing analyzer – thedata throughput of the GZIP decompres-sion algorithm was calculated from simula-


Minimal Tool Chain

Similar Languages

Standardized APIs

Platform Abstraction

Tarari CPP Host CPU

External IP (optional)

HDL

EDIF

HW

LIB

Handel-C CSW

C

LIB

DK SW Tool

BSP

Specification

Implementation

BSP

OS

BIT OBJ

void Decompress(….) { … while(1) par { //1 byte per cycle once pipe is full … ReadW indowAddr(CopyPos); // Pipe Stage 1 - Set address ReadW indowData(TempData); // Pipe Stage 2 - Read W riteW indow(CurrentPos,TempData); // Pipe Stage 3 – W rite … } … }

Figure 3 - Tarari CPPdevelopment framework

Figure 4 - Example of pipelined loop code for Handel-C for LZ77 sliding window


tion results in terms of the number of clockcycles required to decompress given files.

Table 2 shows the theoretical peakand maximum sustained decompresseddata output rate from the GZIP decom-pression algorithm. The actual data out-put rate depends on the level ofcompression – highly compressed filesresult in a higher rate.

In comparison, software GZIP has apeak data output rate of approximately25 MBps on an average Pentium III-based system.

ImplementationThe Handel-C GZIP decompression algo-rithm was synthesized directly to EDIFusing the compiler. Xilinx ISE 5.1i toolswere used to place-and-route the circuitryand to configure the Xilinx FPGAs on theTarari CPP. A board-support package(BSP) of function calls is provided in theTarari Content Processor DevelopmentKit. The BSP provides a layer of abstractionthat shields users from “low-level detail”and is used during both simulation andimplementation of the design.

The final implementation size was 40%of one Virtex-II 1000 Platform FPGAwith speed exceeding the 133 MHzrequired for maximum DDR data accesson the Tarari CPP card.

ConclusionApplication acceleration is simplified usingthe combination of the Tarari CPP and theCeloxica DK Design Suite. Together theyprovide the ability to deliver hardwareacceleration products with much lowerNRE costs than traditional methods andwith a quicker time to market.

The GZIP decompression algorithmwas used to demonstrate the platform’sability to deliver significant accelerationand an overall performance improvementfor applications. The Celoxica DK DesignSuite allowed interactive simulation anddebugging of the GZIP decompressionalgorithm. Interactive simulation deliversboth rapid proof of concept and the com-pletion of development in only twomonths. The Celoxica DK Design Suite –along with the other design tools, exam-ples, and documentation from Celoxica –enable you to quickly develop and deployhighly accelerated products.

You could continue to optimize per-formance for a specific algorithm or, moreimportant, incorporate additional algo-rithms to deliver even higher applicationperformance benefits. Systems deployed atcustomer sites with Tarari CPPs can takeadvantage of these enhancements due tothe built-in reconfiguration capabilities ofthe Virtex-II FPGAs, resulting in an overalllower cost of ownership.

To find out more about hardware acceler-ation using the Tarari Content ProcessorDevelopment Kit, visit www.tarari.com/products-cpdk.html. To discuss how yourapplications can be accelerated, contactTarari at [email protected].

Module Function

1 Main Detects the type of a compressed data block, and calls theappropriate modules to decompress it. Coordinates operationof all other modules in the application.

2 Optimized block Provides a simple interface for pipelined access to blockmemory access RAM on Xilinx FPGAs. Required to achieve high clock rates.

Used to provide RAMs for Huffman tables and LZ77 slidingwindow.

3 Bitstream reader Reads a variable number of bits from the input bitstream.

4 Builder for tree description For dynamic compressed blocks. Uses the treeHuffman decoder description generated from the input bitstream to build a

Huffman decoder table for the tree descriptions for the mainHuffman decoders.

5 Tree description For dynamic compressed blocks. Decodes the HuffmanHuffman decoder codes from the input bitstream, generating tree descriptions

for the “literal/length” and “distance” Huffman decoders.

6 Builder for “literal/length” Uses the tree description generated from the input Huffman decoder bitstream or the static bit-length codes to build a Huffman

decoder table for the “literal/length” Huffman decoder.

7 Builder for “distance” Uses the tree description generated from the input Huffman decoder bitstream or the static bit-length codes to build a Huffman

decoder table for the “distance” Huffman decoder.

8 “Literal/length” and “distance” Decodes the Huffman codes from the input bitstream, Huffman decoders generating “literal” values and “length/distance” pairs.

9 LZ77 decompress Uses the LZ77 algorithm on the stream of “literal” valuesand length/distance pairs to reconstruct the original uncom-pressed data.

GZIP DecompressionRate (Mbytes/s)

Theoretical peak 130

Maximum sustained 116

Table 1 - Modules and descriptions for Handel-C GZIP decompression algorithm

Table 2 - Performance results for GZIP decompression

FPGA

Design

©2003 Mentor Graphics Corporation. All Rights Reserved. Mentor Graphics is a registered trademark of Mentor Graphics Corporation.

Avoid messy timing mistakes.Use Mentor Graphics®

FPGA design tools.

PRECISION SYNTHESIS As any FPGA designer can tell you, achieving precise timing is their single most critical challenge. That's why

Mentor Graphics® created Precision Synthesis, a powerful new tool suite that lets designers close on timing faster than ever. Precision

Synthesis provides the most comprehensive analysis for complex FPGAs with the only complete, built-in incremental timing analysis.

Quickly find and optimize the most critical paths and avoid frustrating trial-and-error design iterations. Visit www.mentor.com/fpga

today or call 877.387.5873 for more information on how Precision Synthesis can help you find the fastest path to a completed design.

TM

TM TM

TM

by Tom HillProduct Manager – Precision SynthesisMentor [email protected]

In the fast-moving world of programmablelogic, EDA vendors face the persistent chal-lenge of creating design tools and method-ologies to keep pace with the increasingcomplexity and capacity of silicon.

ASICs have historically provided a cost-effective solution for the electronics indus-try; this technology is responsible forconsiderable growth and innovation. Thepopularity of ASIC technology has providedthe driving force in the EDA industry anddictated the direction for software develop-ment. ASIC development is, however, mov-ing beyond the reach of many mainstreamdesigners due to high upfront (NRE)charges and a longer time-to-market.FPGAs are filling this void and will becomethe dominant approach for designers andthe new driving force in the EDA industry.

FPGA GrowthFPGA design methodology has manyadvantages. You control the entire designand layout processes. Design cycle timesare faster, photo-mask costs are non-existent, and there are no minimum orderrestrictions. On the other hand, the lowperformance, comparatively smaller gatedensities, and high unit costs of FPGAshave historically relegated them to small,low-volume designs. ASICs claimed theremainder of the market.

Xilinx is overcoming these market bar-riers by developing reconfigurable, system-level FPGAs such as the Virtex-II Pro™Platform FPGA, which integrates embed-ded microprocessor cores, memory, andhard and soft macros. These features pro-vide you with the benefits of reduced sys-tem-development times, improved powerconsumption, increased volume, andexpanded board space, as well as the flexi-bility to make changes right up to produc-tion time. These dramatic technological

breakthroughs, however, add design andverification challenges and require newmethodologies and debug capabilities.

For designers to take full advantage ofFPGA technology, the supporting softwaretools must be capable of solving designers’toughest challenges. Mentor Graphicsintroduced its Precision™ Synthesis plat-form to solve this new set of problems.

Precision Synthesis ConceptsThree major considerations drove thedevelopment of the Precision Synthesisplatform’s architecture:

1. Intuitive user interaction

2. Excellent Quality of Results (QoR)

3. Advanced analysis.

Intuitive UseWhen you interact with an EDA product,the tool should add speed and reliability tothe development, analysis, and debug of adesign. Although the tool must drive the

The same breakthroughs that make FPGAs competitive with ASICs also impose design and verification challenges that require advanced methodologies and debug capabilities. Mentor Graphics’ Precision Synthesis tool provides them.

Next-Generation FPGA SynthesisRequires ASIC-Level Capabilities


Next-Generation FPGA SynthesisRequires ASIC-Level CapabilitiesNext-Generation FPGA SynthesisRequires ASIC-Level CapabilitiesThe same breakthroughs that make FPGAs competitive with ASICs also impose design and verification challenges that require advanced methodologies and debug capabilities. Mentor Graphics’ Precision Synthesis tool provides them.

design process, it must also be capable ofadapting to each user’s design style. ThePrecision Synthesis platform was constructedwith this in mind. You see only the tasks anddata that are relevant to a particular point inthe design process. Extraneous data is hiddenuntil needed. Selective visibility allows you toconcentrate on the task at hand and providesan intuitive approach to synthesis (Figure 1).

The Precision Synthesis platform alsooffers push-button synthesis flow withoutcompromising results or flexibility. Thisease-of-use feature was achieved by replacinguser-configured synthesis options with auto-mated configuration. Optimization algo-rithms configure options based on ananalysis of a design against its constraints,thus eliminating the need to specify effortlevels or optimization “goals.”

Intuitive use can be enhanced by utiliz-ing industry standards and knowledgewhenever possible. We adopted, for exam-ple, the Synopsys Design Constraint(SDC) format for defining timing con-straints. As many ASIC designs are nowcompleted in FPGAs, the SDC formateases the migration of designs between thetwo design environments.

Excellent Quality of ResultsThe Precision Synthesis tool includes a suiteof unique algorithms called ArchitectureSignature Extraction (ASE) optimizationthat automatically focuses specific optimiza-tions on those areas of the design that aremost likely to hinder overall performance,such as finite state machines (FSM), cross-hierarchical paths, or paths with excessivecombinational logic. The ASE technologyuses an automated, heuristic approach todeliver smaller and faster designs withoutiterative manual user intervention.

The Precision Synthesis platform’s ASEtechnology takes full advantage of Xilinxdevice features by providing the smallestdesign that meets your target frequency. Thissaves you time by reducing design iterations,and money by helping you fit into smallerdevices or lower speed grades in the process.

Advanced AnalysisFPGA devices are now being used toimplement highly complex designs for a

optimization at each level of abstraction.They will benefit from a seamless method-ology that allows easy migration through-out each phase of the design.

The Precision Synthesis product desig-nation represents a synthesis technologyplatform that encompasses a family of syn-thesis products created by MentorGraphics to address high-end FPGA designissues from different levels of abstraction.

Built to keep pace with the ever-changing programmable logic world, thePrecision Synthesis platform is a choiceworth considering for next-generationFPGA implementations. By incorporatingan intuitive user interface, excellent QoR,and unparalleled accuracy, it can handle thetoughest FPGA designs.

Mentor Graphics is committed to pro-vide you with the latest set of EDA tools toenable electronic design innovation. Formore information about the PrecisionSynthesis platform or Mentor Graphics’complete FPGA-design product family,visit www.mentor.com/fpga/.

wide range of applications. Thecomplexity of large systems resultsfrom the detailed timing andclocking requirements beingdesigned into these devices. Thistiming complexity can lead toexcessive design iterations or evenundetected timing problems affect-ing printed-circuit-board debug.

To solve these new timing issuesand guarantee a reliable design, thePrecision Synthesis platformincludes a timing engine anddesign analysis capabilities. ItsPreciseTime™ timing engine pro-vides a completely interactive,standalone timing analysis envi-ronment designed to handle themost complicated clockingschemes with speed and accuracy.The PreciseTime engine’s capabili-ties extend beyond timing analysisto include:

• Reports of internal clocks,including clock propagationinformation through simplegates, dividers, and DCMs

• Reports of missing constraints that pre-vent comprehensive timing analysis

• Reports of timing paths that crossasynchronous clock domains (Thesereports help you verify clock isolationor the existence of metastable safe syn-chronization logic.)

• Powerful schematic viewing withschematic-fragment-generation capabil-ities and multiple critical-path viewing(Figure 2).

First-time success on your printed cir-cuit board requires a fully and accuratelyconstrained design during synthesis;PreciseTime was designed to do just that.

Next-Generation FPGA SynthesisThe FPGA synthesis domain is rapidly

expanding beyond the RTL space toencompass the architectural and physicalrealms. This expansion will produce signif-icant gains in both designer productivityand chip performance. Designers willrequire tools with powerful algorithms for


Figure 1 - Precision Synthesis Design Center

Figure 2 - Critical path schematic

NSPICE Bridges Simulation Gap


NSPICE Bridges Simulation Gap A next-generation, mixed-domain SPICE tool with directly integrated S-parameter data capability provides the most accurate simulation of combined silicon and system behavior.

NSPICE Bridges Simulation Gap A next-generation, mixed-domain SPICE tool with directly integrated S-parameter data capability provides the most accurate simulation of combined silicon and system behavior.

by Yu LiuDirector of Simulation ProductsApache Design [email protected]

Streamlining the simulation of entire com-plex system environments – from chip, topackage, to board, to connector, to back-plane, and back again to chip – has becomeone of the most urgent needs of designerstoday. The problem becomes even morechallenging because the supply chain formulti-gigabit serial I/O connectivityrequires tighter integration among manydifferent parties: chip and board designers,system integrators, and backplane and con-nector suppliers.

Internet applications for data, audio,video, and graphics have spawned a myriadof competing standards to relieve the serialI/O bottleneck, including 10 GigabitXAUI, InfiniBand™ and PCI Express™.

The only effective way to address thedesign, simulation, and integration ofmulti-gigabit serial I/Os on multiport net-works is to bridge the circuit simulation gapbetween chips and systems. NSPICE, anext-generation SPICE (Simulation Pro-gram with Integrated Circuit Emphasis)tool developed by Apache, co-simulatesnonlinear SPICE models for the transmitterand receiver circuitry. Together with linearscattering parameters (S-parameters) forconnectors and backplanes, NSPICEbridges the simulation for chip-to-chip andother complex topologies.

Limitations of S-Parameter Lumped RLC At high frequencies, the S-parameter is themost accurate form of broadband frequencyrepresentation for such off-chip, passive net-works as packages, boards, and backplanes.S-parameters are preferred over other fre-quency domain parameters (Y and Z, forexample) primarily because S-parametersrange between the values of 0 and 1, andthey are well behaved across a broad frequen-cy range. In addition, S-parameters are theeasiest parameters to measure using a vectornetwork analyzer. By matching the signalimpedance without reflection and saving theresults to a standard file, you can directlyaccess S-parameter data for simulation.

end of this prolonged process, it is likelythat the system will be inaccurate andrestricted to a limited frequency rangebecause the poles/zeroes will have to bereduced and approximated.

Benefits of S-Parameter Integrated NSPICEAs shown in Figure 1, integrating S-parameter data directly into a mixed-domain, high-capacity SPICE tool offers afaster and more accurate alternative tolumped approaches. NSPICE is fully com-patible with HSPICE (an analog circuitsimulator marketed by Synopsys). It per-

forms mixed-domain simulation withdirect S-parameter data, generating accu-rate eye diagram patterns and output wave-forms. NSPICE co-simulates the nonlinearSPICE models for the transmitter andreceiver circuitry together with linear S-parameters for connectors and backplanes,thereby bridging the simulation for chip-to-chip and other complex topologies.

Figure 2 depicts a typical application: a3.125 Gbps SERDES system consisting ofa transmitter with PLLs (phase lockedloops, represented by a SPICE netlist),connectors, backplanes, linecards (repre-sented with S-parameter models), cables(represented with transmission-line mod-els), and a receiver (represented by a SPICEnetlist). The entire system requires simulat-ing more than 10,000 devices, on top ofhundreds of thousands of RLC parasitics.

As shown in Figure 3, the total turntime using NSPICE, from reading in S-

However, most existing SPICE tools stillrequire you to model S-parameter datafrom backplanes, boards, and transmissionlines into lumped RLC (resistance, induc-tance, and capacitance) “black box” models,or SPICE subcircuits. This timewornlumped RLC approach is necessitated bythe inability of existing time-domainSPICE tools to take in the frequency-domain S-parameter data directly.

There are two main problems with thisapproach. First, lumped models do notaccurately represent distributed frequency-dependent effects, particularly in the high

frequency range. Second, the model gener-ation process can result in a massive quan-tity of elements, taxing both you and theSPICE tool.

To illustrate the modeling complexity,let’s examine a simple two-port passive linearnetwork that has four S-parameters: reflec-tion at both ports, as well as forward andbackward transmission. Correspondingly, afour-port network contains 16 S-parameters.A passive structure such as an FR-4 back-plane can possess hundreds of poles/zerosacross a broad frequency range. Using thelumped approach, you must generate mod-els by fitting and optimizing each pole/zerocombination from S-parameter data. Thisprocess can result in hundreds of thousandsof elements in large multiport networks.The lumped model development timealone can take up to several weeks, notcounting the SPICE simulation time andresulting convergence issues. And at the


Figure 1 - Comparison of S-parameter lumped RLC approach with S-parameter integrated in NSPICE

parameters to generating eye diagrams, is atleast 10 times faster than lumped modelgeneration and simulation approaches,which can consume several weeks. Forsmaller circuits that are less than a fewthousand elements, the turn time inNSPICE for an eye diagram can be shrunkdown to only a few minutes.

Until recently, some connector, back-plane, and board suppliers provided onlyfitted lumped models to their customers,because that was the only way to simulatethe effects in SPICE. Unfortunately,

accuracy has already been lost in the fit-ting process, so customers are nowrequesting vendors to provide the S-parameter data directly. NSPICE cansimulate the system using whatever mod-els are available for each component, inany combination of lumped models,transmission models, and S-parameters.

NSPICE is written in C++ and employshierarchical algorithms offering improvedperformance, memory efficiency, and bet-ter convergence using advanced matrixsolver technology. The product is fully

compatible with HSPICE and SPICEmodels and netlists. NSPICE also supportspseudo-random bit stream (PRBS) genera-tion and eye diagrams.

Working with NSPICETo illustrate the typical usage of NSPICE,assume that a channel simulation configura-tion has the following components: encrypt-ed models from the IP vendor for thetransmitter and receiver, S-parameter modelsfor the backplane, and lumped models forthe connectors and packages from the man-ufacturer. After constructing a SPICE netlistthat represents your channel configuration,you can run transient time-domain simula-tion on the entire system using NSPICE –without translating the S-parameter models– and generate eye diagrams directly fromthe simulation results. In addition, NSPICEsupports advanced analysis, such as frequen-cy modulation, to simulate the on-chip PLLresponse together with off-chip resonanceeffects, thereby enhancing the accuracy ofthe PLL simulation.

The Xilinx flagship Virtex™-IIPlatform FPGA demands simulation thataccurately correlates the RocketIO™ serialtransceiver behavior and performance withactual silicon. By modeling serial back-plane, chip-to-chip, and other topologieswith direct S-parameter data, NSPICEprovides the most accurate simulation ofsilicon behavior.

ConclusionAdapting to the ever-increasing demands ofnetworking bandwidth requires the use oftechnology that seamlessly bridges the time-domain and frequency-domain aspects oflarge systems. A true, mixed-domainSPICE, integrated with actual S-parameterdata, benefits the entire supply chain formulti-gigabit serial connectivity by provid-ing the most accurate prediction of siliconand system behavior. Predicting behavioraccurately ensures significant system costsavings, easier integration, and, mostimportant, accurate and consistent opera-tion across a broadband frequency range.

To learn more about NSPICE, visit www.apache-da.com or [email protected].

Tx Rx

FR-4 Backplane Line Card

Connectors

Vdd

Coax Cable

Figure 2 - Typical 3.125 Gbps SERDES system with S-parameters

Figure 3 - Turn time using NSPICE, from reading in S-parameters to generating eye diagrams


by Robert Chatwani Vice President of MarketingProduct Acceleration, [email protected]

Sanjay Thatte ConsultantProduct Acceleration, [email protected]

According to the International Tech-nology Roadmap for Assembly andPackaging, sponsored by InternationalSEMATECH, the package pin count forhigh-performance ICs is expected to reach4,009 by year 2007. With densities of thismagnitude, proper pin assignment isessential to maximize the component,board, system performance, and to deliver products on time and on budget. Xilinx’sSerial Tsunami Initiative addresses densi-ty-related problems from the FPGA com-ponent perspective, but you also need theright board-level EDA tools. Most oftoday’s EDA board-level tools focus solelyon schematic and layout issues. In doingso, they fail to address many of the com-plex problems – such as board perform-ance, cost, and schedule slippage – that are created by sub-optimal pin assignment.

By minimizing wire crossing and printed circuit board route complexity, DesignF/X pin assignment software reduces routing layers and enables your systems to run faster and come to market sooner.

Optimize Pin Assignments Early


Optimize Pin Assignments Early

In addition to enhancing per-formance by reducing routing layers,automating pin assignments at thefront end of the design process givesyou more time for signal integrityanalysis, functional simulation, andeven system packaging activity. Theend result is higher quality productswith significant reductions in designtime, engineering costs, and productmanufacturing costs.

The DesignF/X™ automateddesign and optimization tool fromPAI (Product Acceleration Inc.) helpsyou analyze and optimize the compo-nent pin assignments very early inthe product development cycle –during concept development, deviceselection, early component architec-ture and placement, and early FPGAdevice floorplanning. The DesignF/Xtool helps shorten development timeand time-to-market, improves theperformance of the finished product,and reduces the costs of developmentand of the finished product as well.

DesignF/X BenefitsThe DesignF/X tool suite enhances productfeasibility, reduces engineering time andcosts, and improves operational metrics.

Product FeasibilityOften, high-density PCB routing challengesare solved through thinner traces combinedwith extremely small, blind, or buried viasand increased PCB layers. These solutions,however, can result in significantly degrad-ed system performance and forced opera-tion at lower system clock speeds. In somecases, the degradation is so bad it results inthe loss of market relevance for a product.

With the DesignF/X tools, these issuesare avoided through earlier, smarter, andfaster analysis and optimization of pinassignments on critical system compo-nents. In turn, this enables fundamentalproduct viability and increases the odds ofmarket success.

Engineering Costs and TimelinesEngineering costs are driven by individ-ual task lengths, inter-task relationships,

Operational Metrics Apart from the costs of R&D, other keyoperational metrics that determine productsuccess are the cost of production andtime-to-market.

The choice of an FPGA-based designapproach implies that time-to-market is akey operational metric for the success ofyour project. However, poor pin assign-ment can result in PCBs that are moreexpensive to manufacture, with up to a10% cost increase with each additionalboard layer. In addition, increased PCBlayer counts may result in longer ordercycles and a narrow supply base. Thisbecomes extremely important when layercounts rise above 24, and critical at morethan 40 layers, at which point the PCBitself represents a significant portion of theoverall system cost.

By avoiding increased order cycles andextended development cycles, DesignF/Xtools help you gain significant time-to-market advantages. By helping to reducethe complexity of the PCB and its layercount, the DesignF/X software lets you

and labor costs. The use of FPGAs clear-ly implies a desire to control engineeringcosts. However, traditional approachesrequire the FPGA designer to interactwith and wait for task completion by asystems hardware designer and a PCB lay-out engineer. Only then can the FPGAdesigner analyze and optimize pin assign-ments, using a manual and iterativeprocess. These delays and iterations affectthe direct cost of the activities, creatingunnecessary task dependencies, forcingextensive change management overhead,and impacting the overall projectmomentum.

The DesignF/X tool suite employs intelli-gent algorithms to create an accurate impactanalysis and optimize pin assignment early,before you spend time creating symbols,schematics, and developing the PCB layout.Consequently, the FPGA designer handlesboard-level issues regarding pin assignmentdirectly, without the task and process delayimposed by traditional processes. The resultis an immediate improvement in projectengineering costs and timelines.

DESIGNF/X VALUE CALCULATORExample - Board Design Using FPGA

Current With DF/X Benefits

Time required Time required

Fully loaded labor rate

Time savings

Cost savings

Worker weeks Worker weeks $ / hour Worker weeks DollarsProduct Design

Architecture & delivery 6.0 5.0 80.0$ 1.0 3,200$

Simulation closure 6.0 4.0 80.0$ 2.0 6,400$

FPGA design flow iterations 3.0 0.0 80.0$ 3.0 9,600$

PCB LayoutComponent placement 2.0 0.4 80.0$ 1.6 5,120$

Optimization setup 0.0 0.2 80.0$ (0.2) (640)$

Board layout 8.0 7.0 80.0$ 1.0 3,200$

Totals 25.0 16.6 8.4 26,880$

= Input

= Output

Avg designs per engineer per yr = 3.0

Dollar savings per design = 26,880$

Total savings per month = 6,720$

Total savings per year = 80,640$

Margin improvement per design = 33.7%

Time improvement per design = 33.6%

Key Metrics


Figure 1 - Analysis of cost saving using DesignF/X tool suite

reduce recurring product costs, improveorder cycles, and expand the pool of avail-able suppliers.

Figure 1 compares the cost of designinga product with – and without – theDesignF/X package. In this example, theDesignF/X tool suite enables an organiza-tion to reduce costs by nearly $27,000 perdesign and shorten product design cycletime from 25 weeks to just over 16 weeks.This reflects a greater than 33% improve-ment in margin per design and a savings ofmore than eight worker-weeks. By usingDesignF/X tools early in the designprocess, you can help avoid costly iterationsdue to improper pin assignments andreduce the time of your FPGA design flowiterations to nearly zero.

Design Flow Using DesignF/XBegin by importing your component infor-mation or creating it rapidly from yourdatasheet or ASCII pin file. You then spec-ify the connectivity between the targetFPGA and other major components, aswell as their approximate placement. Thisprocess includes a definition of pin/signalmobility and basic constraint information.

The DesignF/X software then performs

a “situation analysis” based on various com-binations of component connectivity andplacement, resulting in optimized pinassignments. The optimization is per-formed in terms of the board itself and ofthe system as a whole, with special atten-tion paid to detecting and reducing wirecrossing. Figure 2 illustrates the effective-ness of DesignF/X detection and reductionof wire crossing.

Once you are satisfied with the results,you can create output files consisting ofoptimized component pin assignments andrelated reports. These individual compo-nent pin assignments can then be used aspin assignment constraints for the internaldesign of those components.

Original pin assignments can be writtenin the Xilinx PAD file format. TheDesignF/X program outputs the optimizedpin assignments in the corresponding for-mat, enabling DesignF/X software to fitseamlessly into your FPGA design flow withminimal disruption to existing processes.

Future releases of the DesignF/X toolsuite will support bidirectional dataexchange with Xilinx PACE software tocreate pin and area constraints. In this

case, an NGD file is used as input toPACE. Any additional FPGA pin andarea constraints can then be developedusing PACE and saved for use in theXilinx place-and-route flow.

Figure 3 illustrates how DesignF/X-generated pin assignment constraints canbe used easily in an FPGA design flow.

ConclusionUnlike other EDA board-level design tools– which focus on schematic and layoutissues – the DesignF/X suite from PAI pro-vides you with what you need to reducedesign time and costs through pre-layoutpin optimization. With an intuitive userinterface, Java-based design, powerfulalgorithms, and accurate analysis capabili-ties, DesignF/X software enhances thequality, performance, and cycle-timeparameters of board design projects. ThePAI product suite is designed to coexistwithin existing methodologies – protect-ing your investment in tools, skills, and processes. For more informationabout DesignF/X and PAI’s software solu-tions, visit www.prodacc.com or [email protected].


Concept ReleaseBoard & System Verification

Board Design

FPGA/ASICDesign &

Verification

Logical / Physical Test Synthesis

Place and Route

Timing Analysis / Post Route Verification

Design Goals Met ?

Design Constraints

No

Yes

FPGA/ASICDesign &

Verification

HDL Design Timing Physical Pin Assignments

Concept ReleaseBoard & System Verification

Board Design

FPGA/ASICDesign &

Verification

Logical / Physical Test Synthesis

Place and Route

Timing Analysis / Post Route Verification

Design Goals Met ?

Design Constraints

No

Yes

FPGA/ASICDesign &

Verification

HDL Design Timing Physical Pin Assignments

Figure 2 - Before and after DesignF/X wire-crossing reduction

Figure 3 - Typical board/system design flow

Learn how to obtain visibility into the pins of a ball grid array package using Boundary Scan and the Universal Scan debugging tool.

Got the BGA Blues?


Got the BGA Blues?Learn how to obtain visibility into the pins of a ball grid array package

using Boundary Scan and the Universal Scan debugging tool.

by Rick Folea CTORicreations, [email protected]

The first prototype of a board populatedwith BGAs returns from assembly. Youattach the Xilinx download cable, applypower, attempt to download test data, andyou get – nothing. Debugging is easy whenyou have access to signal pins – but thisboard has BGAs, so you can’t probe the pinseffectively. You wish you could:

• Monitor how mode-select pins are set

• Check continuity across BGA solderconnections

• See if the oscillator is connected to the part

• Check the DIN/DONE/CCLK line continuity

• See if the data/address or other signalsare active or connected to the part.

It would be wonderful if you could peel thechip open. But you can’t. There are, however,more sophisticated ways to access BGA pins.This article introduces Universal Scan™ – a new tool that takes advantage of IEEE1149.1 Boundary Scan, commonly known asJTAG, a feature already built into every Xilinxdevice. It provides visibility and control overthe pins under that BGA – or any JTAGdevice – quickly, easily, and inexpensively.

JTAG Background – The BasicsYou are probably already familiar with theJTAG interface – TCK, TDI, TDO, andTMS – and how JTAG is used to configureXilinx devices. You may not be as familiarwith Boundary Scan, another powerful testtechnology.

Boundary Scan OverviewUnderstanding and using Boundary Scanrequires only three basic pieces of information:

• How the scan chain is connected –Where does Boundary Scan reside insideyour Xilinx device?

• How the scan cells are connected –How does Boundary Scan interface withyour signals?

configure the part). Two of the registers areshown in Figure 1: the instruction registerand the bypass register.

To use Boundary Scan, you simply shiftan instruction into the instruction registerand then shift data in/out of the associateddata register.

The bypass register is used to skip over apart in a scan chain. Skipping parts of thescan chain allows you to bypass the bound-ary register and exit in a single TCK cycle.

Scan logic in each of the scan cellsconsists of a group of registers that cap-tures the state of signals entering and exit-ing the device, and a group of registersthat can drive these same signals. Theoperation of these cells depends on theBoundary Scan mode.

Manufacturers may define manyBoundary Scan modes for a given device,but only the three required by the IEEE1149.1 standard are necessary for success-ful debugging. These modes are: SAM-PLE/PRELOAD, EXTEST, and BYPASS.

SAMPLE PRELOADIn the SAMPLE/PRELOAD mode ofBoundary Scan, the logic inside the yellow

• Boundary Scan operational modes –What are they and how do they affectthe scan cells and the information youcan access?

The Scan ChainAt the most fundamental level, BoundaryScan is illustrated in Figure 1. Logic occu-pies the interior of the device. Pins occu-py the perimeter, or boundary. Theinterconnects between each pin and theinternal logic pass through the BoundaryScan logic blocks (yellow in Figure 1).Boundary Scan blocks are on the logicside of the IOB (input/output block).They are normally transparent to theoperation of the device; signals flowunimpeded through them.

Each of these blocks is connectedaround the boundary of the part to form agiant shift register (the boundary register).When in Boundary Scan mode, TDI isconnected to one end of the shift register,and TDO is connected to the other end.TCK and TMS are used to shift data in andout of this giant shift register.

TDI and TDO can be connected tonumerous registers (such as those used to


IOB

IOB

IOB

IOB

IOB

IOBIOB

IOB

IOB

IOB

IOB

IOBIOBIOBIOB

TDI TDO

Scan Cells

INTERNALLOGIC

Instruction Register

Bypass Register

Figure 1 - The yellow Boundary Scan cells are located between the analog front end of the IOB and the internal logic.

blocks of Figure 1 is represented in greaterdetail in Figure 2.

One capture register is dedicated toeach signal typically associated with anI/O buffer (INPUT, OUTPUT, TRISTATE).On a command set by the test engineer,these registers, or scan cells, capture thestate of all three signals (or however manythere are for the pin). Once data is cap-tured, it is shifted out (the red path inFigure 3), and the state of the pin is dis-played. Data can be captured at any time.It is asynchronous with signals flowing inand out of the device. The captureprocess does not interfere with the circuit’s operation.

EXTESTWhen a part is in EXTEST mode, data thatthe test engineer wants to apply to theOUTPUT, TRISTATE – and in some cases,INPUT – signals is shifted into the scanchain. Although the capture registers fromSAMPLE/PRELOAD still capture the statesof the signals flowing through the device,they never go anywhere. The signals are cutoff from their normal function and thedata shifted into the update registers isapplied to the signals, as shown in Figure 3.Captured data is shifted out as update datais shifted in.

BYPASSWe have already touched on BYPASS. Inthis mode, the Boundary Scan chain isbypassed and all TDI data flows throughthe part in one TCK cycle.

Applying Boundary Scan to Access PinsUsing the JTAG state machine to imple-ment Boundary Scan can be tedious. Butthe new Universal Scan debug tool fromRicreations Inc. automates much of thework. You simply drop virtual parts on thescreen, connect the JTAG signals to theparallel port, and hit the SCAN button.Instantly, the activity of every pin underthe BGA (or around any JTAG part)appears on your PC display.

Each of the red or black dots in Figure 4represents a pin. Red represents a logic High;black a logic Low. Blue is a pin that can’t bescanned (power, ground, and such).


D

LE

Q1

0

D

LE

Q

1

0

D

LE

Q1

0

DATA IN (TDI)

IOB.I

IOB.Q

IOB.T

SHIFT/CAPTURE DATA OUT

(TDO) CLK-DR

D

LE

Q1

0

D

LE

Q

1

0

1

0

1

0

1

0D

LE

Q

D

LE

Q

D

LE

Q

D

LE

Q1

0

DATA IN (TDI)

IOB.I

IOB.Q

IOB.T

SHIFT/CAPTURE DATA OUT

(TDO) CLK-DR

UPDATE EXTEST

Update Registers

Figure 2 - In SAMPLE/PRELOAD mode, the scanlogic consists of three capture registers. I/O signals

captured in the latches are shifted out serially.

Figure 3 - In EXTEST mode, normal signal flow is interrupted and data that had been shifted into the update registers by the test engineer is applied to the signals.

If a pin is toggling, that means there issignal activity on that pin. Typically, this isall we want to know when we use an oscil-loscope to debug – whether the pin is high,low, or toggling. The Universal Scan tool isan activity indicator. You instantly see – inreal time – if the mode select pins are setcorrectly, if the oscillator is connected, if thedata bus or address bus is active, and so on.

Universal Scan software does notrequire netlists, test executives, testfixtures, or other board-test periph-erals. You don’t have to maintain aparts library, because the UniversalScan program doesn’t need it. Yousimply supply the BSDL files,which are freely available from ven-dor websites, and the UniversalScan tool builds a virtual part onthe fly. All that is required is aJTAG-enabled part; packagingdoesn’t matter.

A valuable aspect of BoundaryScan testing is that, while in SAMPLE/PRELOAD mode, you canmonitor all the pins while your circuit is running at full speedwithout any impact on the system. SAMPLE/PRELOAD mode is completelytransparent to the system. How often haveyou touched an oscilloscope probe to a pinonly to create probe loading that changesthe circuit’s operation, especially with newhigh-speed circuits? Boundary Scan doesnot have that problem – it is completelyunobtrusive.

Because watching pins blink on thescreen can be tedious, the Universal Scanscreen display offers virtual indicators(LEDs) that you connect to the pins toorganize those aspects of the circuit’s activ-ity that interest you. It also has virtualswitches that allow you to manually drive apin to a known state.

To perform a continuity test betweentwo devices, put one device into EXTESTmode and toggle the virtual switches con-nected the output buffers. The LEDs con-nected to the other device’s input bufferswill show the result. Performing a continu-ity test this way is quick, easy, and does notrequire touching the board.

To monitor results on an oscilloscope,

you can drive signals from the BGA to a con-nector. This gives total visibility and controlover every scan-enabled pin on the part. Youare only limited by your imagination.

Because Boundary Scan is independentof internal activity, the part does not haveto be configured for this testing. You cantake the board right off the factory floorand start testing it before theVHDL/Verilog/firmware is ready.

ConclusionUsing Boundary Scans to probe otherwiseinaccessible pins under a BGA is an easy,three-step process with the UniversalScan tool:

1. Drag and drop the parts under test on the PC screen.

2. Connect the JTAG chain to the parallel port.

3. Hit the Scan button.

Instantly you can monitor the activityof every JTAG-enabled BGA pin (oraround any scan-enabled device) on yourPC display.

You don’t need test fixtures, netlists, ortest executives. The devices don’t have to beconfigured. You can start testing the boardright off the factory floor before thefirmware is complete.

You’ll find information on the UniversalScan toolset on the www.xilinx.com websiteby following this click chain: Products/SystemResources/Configuration Solutions/Third-PartyTools/Universal Scan. Or you can go directlyto www.UniversalScan.com.


Figure 4 - Virtual switches and LEDs help organize and control the pin information.

R

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in the Xcell Journal!

by Rob SchreckSenior Marketing ManagerXilinx, [email protected]

Today’s high-performance chips with fastsignal rates require termination to preventsignal reflections and to maintain signalintegrity. Historically, engineers have usedexternal termination resistors. However,with advanced packaging technologies andavailability of hundreds of I/Os, externaltermination resistors are no longer viable,especially for ball grid array packages.

To solve this problem, Xilinx pioneeredadaptive on-chip termination with XCITE(Xilinx Controlled Impedance Technology)in Virtex™-II Platform FPGAs. XCITEdynamically eliminates drive strength vari-ation due to process, temperature, andvoltage fluctuations. XCITE uses twoexternal high-precision resistors per I/Obank to incorporate equivalent input andoutput impedance internally for hundredsof I/O pins. Not only is the cost of theresistors saved (and the additional manu-facturing costs that accrue with them), butwith fewer printed circuit board respins thecost of developing PC boards also decreas-es, as illustrated in Figure 1.

Reduce Resistor Counts and Lower Costs


Second-generation XCITE

technology provides controlled

impedance drivers and on-chip

termination for single-ended and

differential I/Os for Virtex-II Pro

Platform FPGAs.

Reduce Resistor Counts and Lower Costs Second-generation XCITE

technology provides controlled

impedance drivers and on-chip

termination for single-ended and

differential I/Os for Virtex-II Pro

Platform FPGAs.

Increase Signal Integrity With XCITE, you can eliminate hundredsof external resistors and increase the signalintegrity of your boards for single-endedconnectivity solutions such as low-voltagecomplementary metal-oxide semiconduc-tors (LVCMOS). With higher performanceI/O becoming more pervasive, you needthis capability not only in single-ended con-nectivity, but in differential signals as well.

Now, Xilinx offers second-generationXCITE technology in the Virtex-II Pro™Platform FPGA family, extending to popular connectivity standards like low-voltage differential signaling (LVDS), asshown in Figure 2.

Second Generation XCITE technologySecond-generation XCITE for Virtex-IIPro FPGAs provides controlled imped-ance drivers and on-chip termination forsingle-ended and differential I/Os.

XCITE can be used on any I/O blockin any bank, thus offering absolute flexi-

bility and independent operability on eachI/O bank. When applied to inputs, XCITEprovides controlled impedance input paral-lel termination.

When applied to outputs, XCITE pro-vides controlled impedance series as well asparallel termination. Each of the eightVirtex-II Pro I/O banks supports XCITE,controlled by just two external referenceresistors per bank.

ConclusionAs shown in Table 1, Virtex-II Pro PlatformFPGAs offer second-generation XCITEtechnology that gives you increased signalintegrity for both single-ended and differ-ential signaling. Using XCITE technologyallows you to dramatically reduce the num-ber of resistors to lower your componentcosts. The increased signal integrity of eachVirtex-II Pro Platform FPGA designreduces the risk of board re-design, deliver-ing even more cost reduction. Simplify yourdesigns and lower your costs with Virtex-IIPro FPGAs with XCITE. For more infor-mation, go to www.xilinx.com/xcite/.


Second-Generation Technology Proved in the field and used extensively by customers means youcan rest assured about its functionality – another Xilinx innovationfor lowering risk, improving design efficiency, and maximizing performance.

Lower Costs By using XCITE, you need fewer resistors, fewer PCB traces, and less board real estate – all resulting in lower PCB costs.

Absolute I/O Flexibility Use any termination on any I/O bank. Non-XCITE technology alter-natives deliver limited functionality with compromising bankingrestrictions. XCITE input buffers support full and half impedance.

Support for Popular Standards Wide support for many I/O standards, including LVDS, LVDSEXT, LVCMOS, LVTTL, SSTL, HSTL, GTL, and GTLP.

Maximum I/O Bandwidth With less ringing and reflections, you can maximize your I/O bandwidth.

Immune to Temperature Temperature and voltage variations lead to significant impedanceand Voltage Changes mismatches. XCITE provides complete immunity by dynamically

adjusting on-chip termination with digitally controlled impedance at all temperatures and voltages.

Eliminates Stub Reflection XCITE technology improves discrete termination techniques by eliminating the distance between the package pin and resistor.

Increased System Reliability With fewer components on board, XCITE delivers higher reliability.

Figure 1 - Reduced component count with XCITE

Figure 2 - Increased signal integrity with XCITE

Table 1 - XCITE benefits for Virtex-II Pro Platform FPGAs

Smooth Out Signals

Signal Integrity

Reduce Resistors

Improve PCB Layout

by Frank TothMarketing Manager, Advanced ProductsXilinx, [email protected]

Once a working prototype is developed,designers using high-density FPGAs need arisk-free method of reducing the cost ofcomponents used in their end-marketproducts and systems. The traditionalASIC approach is expensive and errorprone. The designer typically relies on anASIC conversion methodology provided byeither the FPGA or the ASIC supplier.These methods are supported by a widerange of claims for conversion accuracy andperformance. Typically, 30 to 40 weeks isrequired to accomplish such a conversionfor mass production.

Xilinx attacks this problem head-onwith our introduction of the Virtex-IIEasyPath™ series solutions, including aVirtex-II Pro™ version, as the newestmember of the Virtex™-II family ofPlatform FPGAs. The EasyPath solutionslashes the conversion time to 10 to 12weeks (Figure 1), and delivers a 30% to80% cost reduction without risk andwithout additional investment of engi-neering time or other resources.

Traditional Conversion: Trial and ErrorConventional conversions require directtime and expense for the services of theASIC manufacturer for fabrication masksand test programs, and for the engineer-

The Virtex-II and the Virtex-II Pro EasyPath solutions are a cost-effectivealternative to ASIC conversion– saving you money whilesignificantly decreasing yourtime to market.

Get theEasyPath Solution


ing cost of verification and simulation.When the completed system is transferredinto production, further system engineer-ing time and expense are needed torequalify the final production systemwith this new ASIC.

As systems become faster, timing andclocking budgets are tighter, and any slightchange in critical paths brought about byASIC conversion can cause timing mis-matches and race conditions. All of thesefactors introduce substantial risk of delayand escalating cost.

Risk-Free, Quick, and EasyThe Virtex-II and Virtex-II Pro EasyPathFPGAs emerge from the conversionprocess ready for full production withoutany need for a requalification or proof ofperformance that would normally berequired of new ASIC silicon. EasyPath sil-icon is identical to the FPGA prototype,with the logic and routing resources usedby the customer design completely testedfor functionality and performance at speed.

Streamlined ProcessOnce the design is settled and the qualifi-cation completed, you can simply submitfour design files (Figure 2), which are stan-dard outputs from any Virtex-II andVirtex-II Pro design.

The EasyPath product is tested for per-formance and functionality using the sametechniques as those applied to the prototypeFPGA. Designers order the same speedgrade, package, and density as they did forthe original FPGA. Typical lead times forproduction quantities range in weeks ratherthan months – from the engineering confir-mation of the design submittal to full pro-duction silicon (thousands of units).

There is no need for the customary firstarticle testing and no risk of the delays thatresult from multiple spins of ASIC silicon.

Test CoverageThe manufacturing test of EasyPath siliconis based on a foundation of proven FPGAtest techniques that assure complete testingof the customer design.

Typical ASIC testing relies on the com-pleteness of vectors generated by the cus-


Custom ASIC Conversion

EasyPath Conversion10-12 weeks

6-8 weeks 6-8 weeks 8-12 weeks

30-40 weeks

Design Prototype Build

EasyPath

Proto Eval Production

10-12 weeks

NCD PCF

BGN BIT

CustomerSpecifies V-II &

V-II Pro:Density, Speed

& Package

AssignPart

Number

TestCoverage

Report

Generate TestProgram

Test, Assembleand MarkEasyPath

per Customer

ImmediateProduction

Ships

CustomerDesign

File

AnalyzeResources

Used inDesign

VerifaultFault

GradedTest

LibraryTest

Library

GenerateTest

CoverageReport

AggregateTest

Coverage

TestGeneration

PullRequiredTests for

CustomerDesign

RequiredTests

Figure 1 - EasyPath conversion time compared to custom ASIC conversion.

Figure 2 - EasyPath flow

Figure 3 - EasyPath test program

tomer or the ASIC supplier. The ASIC sup-plier works in conjunction with the design-er to cover all the possible test cases withvectors to assure correct operation.

In contrast to this approach, EasyPathtesting is based on instrumenting and test-ing all of the resources used by the cus-

tomer design, as well as testing criticalstructures at speed. Using multiple bit-stream loads, each resource is instrumentedusing a library of Verifault™ verified testdesigns (Figure 3).

The resources used in the EasyPathdesign are matched against this proven test

library, with each routing resource testedusing “source” and “load” techniques(Figure 4). The “source” provides the stim-ulus, and the “load” evaluates the response.

The EasyPath solution takes advantageof some of the unique architectural featuresof the Virtex-II and Virtex-II Pro FPGAs.

When testing routing, for example, youcan allow unused routing resources to betied to a known state to test for shorts.

As for complicated circuitry such as blockRAMs and multipliers, we use multiple bit-streams to instantiate built-in self-test (BIST)structures (Figure 5) designed to thoroughlytest these complex circuits.

Error detectors (Figure 6) check for thecorrect operation of each circuit. Criticalresources within the device are speed testedusing standard FPGA techniques to guar-antee the device operates at the desiredspeed grade.

ConclusionThe Virtex-II and Virtex-II Pro EasyPathsolutions eliminate your risk, and give youcomplete control over the expense of con-verting to a lower cost solution foradvanced systems. Now you can reducetotal system cost without the need for addi-tional engineering resources. You won’thave to requalify the system for new sili-con, or worry about the cost and delay ofASIC silicon respins. You can confidentlypredict the crossover point for realizing thecost savings of the conversion.

In light of current market pressures andtight inventory management, a conventionalASIC will not always be the optimum costreduction solution. The Xilinx Virtex-II ProEasyPath solution provides you with a risk-free, rapid, and easily implemented costreduction alternative. Check it out atwww.xilinx.com/easypath/.


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ResourceUnder Test

(Block RAM,LUT RAM,DDL, etc.)

ErrorDetector

Figure 4 - Routing test using source/load library

Figure 6 - IFA13 BIST circuit

Figure 5 - FPGA testing using self tests

Industry’s bestFPGA fabric

Industry-leading ISE software solutions

Comprehensive family of 10 devices

Xtreme DSP solutions

Over 200 IP core solutions

World-class partners and services Embedded PowerPC

processing solutions

Ultimate connectivity solutions

Virtex-II Pro™ FPGAs deliver more capabilities and

performance than any other FPGA.

In a single device, you get the highest density, most memory,

best performance, and at no additional charge 400MHz Power PCTM

processors and 3.125 Gbps RocketIOTM serial transceivers. This

gives you the fastest DSP, connectivity and processing solutions in

the industry.

The Power to Develop Your Design

The Xilinx ISE 5.2i software tools are the easiest to use solution for

high-density logic. With over 200 IP cores,

ChipScope Pro debug environment, and compile

times up to 6x faster than our nearest competitor,

you can quickly take your Virtex-II Pro FPGA

design from concept to reality.

Virtex-II Pro EasyPath Solution forLower Production Costs

For high-volume system production, Xilinx offers a lower cost path

with Virtex-II Pro EasyPath. You can immediately take advantage of

dramatic cost reduction at no risk

and no effort. No other company can

offer you this flexibility for design

and production.

Visit www.xilinx.com/virtex2pro today to get the price and

performance you’re looking for.


www.xilinx.com/virtex2pro

©2003, Xilinx, Inc. All rights reserved. The Xilinx name, the Xilinx logo are registered trademarks. Rocket I/O and SelectI/O, Virtex-II Pro are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc. The following are

trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM, IBM logo, PowerPC, PowerPC logo, and CoreConnect. All other trademarks and registered trademarks are the property of their

respective owners.

DESIGN CHAIN

WWW.CADENCE.COM/PARTNERS/ROCKETIO.HTML

Network equipment designers face many design challenges, but integrating multi-gigabit

transceivers into the system doesn’t need to be one of them. The Xilinx RocketIO Design Kit

for SPECCTRAQuest™ includes a complete electronics blueprint that allows you to simulate

and implement Virtex-II Pro RocketIO transceivers on your PCB. Together, Cadence and Xilinx

provide the technology to speed your time-to-volume and reduce your development costs.

Using a Virtex-II Pro for your next design? Make a note to call us.

© 2003 Cadence Design Systems, Inc. All rights reserved. Cadence and the Cadencelogo are registered trademarks, and SPECCTRAQuest is a trademark of CadenceDesign Systems, Inc. All others are properties of their respective holders.

by Xcell Staff

Late last year, Canadian-based AlcoholCountermeasure System (ACS) introducedthe Elan™ personal breath tester, whichmeasures an individual’s blood alcohol con-centration. Developed in collaborationwith Xilinx, the Elan tester demonstratesthe creative potential for new mass marketproducts that exploit low-cost, low power-consuming FPGAs.

The Elan tester analyzes and displaysblood alcohol (%BAC) test results on a 3-digit LCD display within 10 seconds, yetit’s not much bigger than a cigarette lighterand costs just $49 USD.

Stopping Repeat OffendersACS and Xilinx have also developed ahigh-end, voice-recognition alcohol breathtester that will help law enforcement man-age repeat offenders. Available today inbeta form, the ACS WR3 ignition inter-lock device locks the auto ignition until thedriver passes a sobriety analysis by breath-

ing and humming intothe mouthpiece.

What makes thisnew technology uniqueis the voice recognitionfeature – enabled byXilinx chips – whichmakes it impossible forthe offender to cheatand activate the vehiclewith the breath ofanother individual.

Xilinx FPGAs Key Component“Xilinx low-cost programmable chips pro-vided the technology we required to produce the most advanced alcohol breathtesters on the market today,” said NigelCorreia, operations manager at AlcoholCountermeasure Systems. “We needed leading-edge technology combined with lowpower and low cost, and Xilinx delivered.”

ACS partners with North American andEuropean law enforcement agencies in thedeployment of its technology. The Elanalcohol breath tester is available to the pub-lic and can be ordered directly from ACSonline at www.acs-corp.com.

Low-cost high-performance Xilinx technology powers development of inexpensive alcohol breath testers for drivers and law enforcement.

Xilinx Chips Fight Drunk Driving


Figure 1 - The Elan alcohol breath tester from ACS.

Digital signal processing with Virtex-II Pro FPGAs from Xilinx enables a wide range of sophisticated electronics designed to make driving safer.

FPGAs Are the Brains Behind “Smart” Cars


FPGAs Are the Brains Behind “Smart” CarsDigital signal processing with Virtex-II Pro FPGAs from Xilinx enables a wide range of sophisticated electronics designed to make driving safer.

by Robert GreenEuropean MarketingXilinx, [email protected]

Karen ParnellProduct Marketing Manager, AutomotiveXilinx, [email protected]

According to a study carried out byVisteon Corporation, safety is the numberone concern of vehicle customers. It’s atthe heart of the consumer priority hierar-chy (Figure 1).

Increasingly, equipment designers areturning to programmable technology tomake cars – and driving – safer. Farbeyond the more familiar tire and brakingtechnology, side impact protection, andairbags, today’s “driver assistance” systemshave evolved from the physical to theelectronic domain. The latest electronics-rich vehicles use sensors to continuouslyevaluate surroundings, display relevantinformation, and in some instances, eventake control of the vehicle.

Safer, More Efficient – and More ComfortableDriver assistance systems can offer basicsafety features, such as adding infrared(IR) cameras to improve visibility, but themore advanced equipment can warn thedriver of potentially dangerous situations.Using a wider array of sensors, these elec-tronic systems enable the vehicle to beaware of surrounding traffic, lane direc-tion, and potential collisions. The ulti-mate aim is to enable the vehicle to reactautomatically – whether this involves giv-ing the driver information or assistingwith car control – so that occupants arekept safe.

For example, some of the latest trucksare equipped with video cameras that cap-ture images of the lane ahead. If the vehi-cle changes lanes without using indicators– a sign, perhaps, that the driver isfatigued – an alert is sounded through thecabin loudspeakers.

Driver assistance can also make driversmore comfortable by automating routineactions. Conventional cruise control, for

output control signals, each under thecontrol of its own processor (a XilinxMicroBlaze™ 32-bit soft processor, forexample, or even an embedded IBMPowerPC™ in a Virtex-II Pro™ FPGA,Figure 2).

The high-speed section is dedicated tothe real-time processing of video coming

from the cameras mounted at the front ofthe vehicle. Given the critical nature ofthe application – crash avoidance, emer-gency procedures, and alerts – real-timeprocessing is absolutely essential.Typically, two or more cameras will beused to capture a stereo image, thusenabling calculation of image depth(directly related to real distances fromobjects) in the FPGA. This information,combined with radar and laser measure-ments, plus the information collectedfrom gyros and wheel sensors to detectmotion, yields a very accurate map of thevehicle’s surroundings and its path.

Capturing and processing this informa-tion in real time requires the use of math-intensive digital signal processing (DSP)algorithms. Software processing cannot

example, has now evolved into adaptivecruise control (ACC), which automatical-ly controls the throttle. ACC brakes tomatch the speed of the vehicle in frontand keep a safe distance from it. If thevehicle ahead accelerates or changes lanes,ACC returns to the pre-set speed of thecruise control.

Other new developments may alsoserve to make traffic more efficient. The“electronic tow bar,” for example, willenable truck convoys in which the leadvehicle is driven manually and the follow-ing trucks are driven automatically. Inaddition to taking some of the burdenfrom drivers, the distance between truckscan be greatly reduced because the elec-tronic driving device reacts faster than ahuman. Not only does this save valuableroad space, but by traveling in the slip-stream of the vehicle in front it saves fuelas well.

Xilinx FPGAs in Driver Assistance Systems A driver assistance system is partitionedinto very high-speed input processing andrelatively low-speed sensor inputs and


ENTERTAINMENT

INFORMATION/COMMUNICATION

ADVANCEDSAFETY

NAVIGATION

SAFETY

DVD

E-mail

News,Sports,Stocks

Personal Data Accesse.g., contacts, calendar

Video-On-Demand

WebSurfing Vehicle

DiagnosticsVoiceControl

Remote Car Functions

Games Real-TimeTraffic Reports

GPS

PanicButton

AutoDistressSignal

Vehicle Tracking

Safety is at the coreof consumer needs

Figure 1 - Hierarchy of consumer needs (courtesy Visteon Corporation)

meet these performance requirements, andit often takes several conventional DSPprocessors to perform such high-speedtasks. Frequently, even ASSP (application-specific standard product) video processorscannot match the extremely high-speedDSP performance of Xilinx FPGAs, alsoknown as XtremeDSP™ processing.

In addition, using fully flexible FPGAsrather than off-the-shelf video compo-nents enables equipment manufacturers to

easily develop the unique, optimized edgedetection, image depth, and enhancementalgorithms that will differentiate systemperformance from the competition.

After processing the video, the decisiontree mechanisms can be partitionedbetween hardware (for speed-critical algo-rithms such as sudden object avoidance)and processor software (for soundingalerts such as lane drift warnings).Partitioning speed-critical processes into

FPGA hardware also enables testing atreal-time rates, something that is impossi-ble to do in software.

XtremeDSP – Real-Time Image ProcessingSo why can Xilinx FPGAs offer fastervideo processing than conventional DSPs?The fundamental reason has to do withthe FPGA architecture’s inherent ability toprocess data in parallel. In contrast, a DSPprocessor takes in successive instructions

and data, and processes them ina serial fashion.

In addition, the latest Virtex-II Pro family of devices fromXilinx also has an array ofembedded, high-performancemultiplier blocks to increaseimage-processing power evenfurther. This enables the FPGAto be configured as a large arrayof multiply-accumulate (MAC)engines performing multipleoperations concurrently (in asingle clock cycle) as opposed tomultiple cycles through the sin-gle or few MAC engines avail-able in conventional DSPs(Figure 3).

Another advantage of XilinxFPGAs is that you can size thearray precisely to suit the calcula-tion requirements, which is idealfor performing calculations on


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Conventional DSP FPGA Performance Advantage

• Fixed inflexible architecture– Typically 1-4 MAC units– Fixed data width

• Serial processing limits datathroughput– Time-shared MAC unit– High clock frequency creates

difficult system challenge

Loop Algorithm256 times

Data Out

Data In

Reg Reg Reg RegData In

MAC unit

e.g., 256 Tap FIR Filter = 256 MAC operations per sample256 MAC operations in 256 clock cycles in DSP

Performance Limitations

• Flexible architecture– Distributed DSP resources (LUT,

registers, multipliers, and memory)

• Parallel processing maximizesdata throughput– Support any level of parallelism– Optimal performance/cost

tradeoff

C0 C1 C2 C255

e.g., 256 Tap FIR Filter = 256 MAC operations per sampleAll 256 MAC operations in 1 clock cycle in FPGA

Figure 2 - Concept of FPGA in ACC driver assistance system, with pre-verified Controller Area Network (CAN) interface core

Figure 3 - Xilinx FPGAs offer unrivaled DSP performance.

images. Calculations can be performed onclusters of pixels, such as discrete cosine trans-form (DCT) macroblocks, concurrently withother blocks in the picture instead of havingto scan the entire picture sequentially. Andbecause processing can now be done in realtime, less memory is needed for bufferingpixel values when using FPGAs.

In addition to real-time performance,the reprogrammability of Xilinx FPGAsalso offers superb system flexibility,enabling algorithm upgrades even afterdeployment. This is important, as currentdriver support systems are still in the earlystages of research and development. Asedge- and object-detection algorithmsimprove over time, hardware upgrades canbe accomplished in a matter of minutesand with no board redesign.

Bridging Automotive Networks Today, multiple network technologieshave emerged that cover various functionsand features in the car. These technologiesrange from multimedia networks, such asmedia oriented systems transport(MOST) in the cockpit, to car controlnetworks like FlexRay™ automotive con-trol systems. As vehicles evolve into a trulynetworked arena, equipment manufactur-ers must determine which standard will bethe most successful or offer the greatestadvantage over other network protocols.

However, one of the real benefits ofusing an FPGA rather than an ASSP isthat it allows you to produce designs thatprecisely match interfaces and peripheralsto the system requirements – particularlyuseful when trying to interface with pro-tocols in the early stages of development.When you’re trying to get a product tomarket quickly, a chipset or ASIC (appli-cation specific integrated circuit) re-spinis both costly and time-consuming.

With an FPGA, if the specification of anetwork protocol changes during a stan-dard’s early days, all it takes to support thelatest revision is a relatively simple redesignin software and a download of the newhardware configuration. You can even do itover a wide area network using XilinxIRL™ (Internet Reconfigurable Logic)technology, which means the hardware can

be revised during maintenance withoutcostly recalls or extra manpower.

IQ Solutions for Automotive ApplicationsTo address the needs of automotive elec-tronics equipment designers, Xilinx hascreated a new range of devices with anextended industrial temperature rangeoption. Called the “IQ” range (Table 1), itcomprises current Xilinx industrial grade(I) FPGAs and CPLDs qualified to a newextended temperature grade (Q).

The first products qualified to operateat the new temperature grade areSpartan™-XL 3.3V FPGAs ranging from5K gates to 30K gates, and the 36 and 72macrocell XC9500XL3.3V CPLDs. In thecoming months, the IQfamily will be expandedto include FPGA devicesup to 300K gates, andCPLDs up to 512 macro-cells in density (Table 2).

ConclusionThe new wave of driver assistance systemsrequires high-performance image process-ing without sacrificing flexibility, espe-cially during early stages of research anddevelopment of object detection andautomotive network technologies. Theuse of Xilinx FPGAs at the heart of suchsystems offers the industry’s best DSPperformance, unrivaled support for net-work connectivity standards, and givessystem architects a fully flexible designplatform with which to work. Working inreal time, these systems provide emer-gency driver alerts, assist car control, andsignificantly increase safety.


Temperature Grade/Range °C

Product C I Q

FPGA TJ = 0 to +85 TJ = -40 to +100 TJ = -40 to +125

CPLD TA = 0 to +70 TA = -40 to +85 TA = -40 to +125

Xilinx IQ Solutions Silicon Selector

Product Family Packages Voltage Density Range

XC9500XL CPLDs VQ44, VQ64, TQ100 3.3V 36 - 72 Macrocells

CoolRunner XPLA3 CPLD VQ44, VQ100, TQ144, PQ208 3.3V 32 - 512 Macrocells

CoolRunner-II CPLD VQ44, VQ100, TQ144, PQ208 1.8V 32- 512 Macrocells

Spartan-XL FPGA VQ100, TQ144, PQ208, BG256 3.3V 5K - 40K Gates

Spartan-II FPGA TQ144, PQ208, FG256, 2.5V 15K - 200K Gates

Spartan-IIE FGPA TQ144, PQ208, FT256, FG456 1.8V 50K - 300K Gates

Further Information

www.xilinx.com/esp/technologies/consumer/automotive.htm Xilinx Emerging Standards and Protocols (eSP)

www.xilinx.com/automotive Xilinx Automotive Products – The IQ Range

www.xilinx.com/dsp Xilinx DSP Central

www.xilinx.com/products/logicore/coredocs.htm#DSP Xilinx DSP Core Solutions Documents

www.xilinx.com/ipcenter Xilinx IP and Core Solutions Catalog

www.visteon.com Visteon Corporation Home Page

Table 1 - Temperatures supported by Xilinx products

Table 2 - Xilinx IQ solutions silicon for automotive applications

Using IP cores and a pre-integrated IP platform, engineers at SoC Solutions built a custom microcontroller platform – in less than two weeks.

How to Design a 3DES Security Microcontroller

by James BruisterPresidentSoC Solutions, [email protected]

Today’s seemingly limitless access toinformation has also brought forth a needto secure personal and corporate informa-tion from unauthorized access and to pro-tect privacy. This need for secure data notonly applies to securing wired and wire-less communications, but is also impor-tant in applications where access control,data integrity, confidentiality, andauthentication are required. For this rea-son, cryptography will find its way into ahost of common devices, including bankATMs, kiosks, information portals, videosurveillance equipment, building accesscontrols, and the like.


How to Design a 3DES Security MicrocontrollerUsing IP cores and a pre-integrated IP platform, engineers at SoC Solutions built a custom microcontroller platform in less than two weeks.

The problem of securing data is a com-plex one, and applications requiring cryp-tographic processing are varied. Manydevices need 3DES (Triple DataEncryption Standard) hardware accelera-tion, because software implementations aresimply too slow. In addition, most designsrequire a combination of features not read-ily available in off-the-shelf components.

To implement a custom interface or pro-tocol that meets the product’s specific func-tional requirement, you must either developwith FPGAs or spin an ASIC. In both cases,the most common approach is to first codethe design in a hardware description lan-guage such as Verilog or VHDL, and thensynthesize the design to the targeted silicon,such as a Xilinx Virtex™ FPGA.

In this article, we will describe how webuilt a secure microcontroller platformusing our PiP-EC02 Embedded Con-troller IP platform with the addition ofour 3DES core.

A Better ApproachAt SoC Solutions, we believe the bestapproach to implementing these securedesigns is to start with an IP platform, orIP reference design, which we define as apre-developed, pre-integrated Verilog orVHDL design. Also known as softdesigns or soft cores, these can be target-ed to FPGA devices.

3DES Secure DataEncryption/Decryption ApplicationMany applications, such as online privateinformation transfers, require that datafiles or streamed information be securedby encrypting the payload data. 3DES isconsidered to be very secure because it canuse three separate keys to encrypt data.

Our secure microcontroller imple-ments a smart device that stores 3DES-encrypted data in memory; it thendecrypts the data before storing it back tomemory. This is useful where data is pro-vided as medium to large data files (orstreams) and where the microprocessorhas limited bandwidth to do the math-intensive encryption (or decryption)while simultaneously processing othertasks or applications.

stored result. In a typical application, acommunications port such as Ethernet,PCI, USB, or a simple COM port wouldbe used as a data I/O port.

The design includes a direct memoryaccess engine to read and write datafrom/to the 3DES core to internal FPGASRAM or external memory. Also includedare an internal SRAM controller, aninterrupt controller, timers, UARTS, andan external bus interface.

The process of encrypting or decrypt-ing a file is simple. The microprocessorfills memory from data acquired eitherunder software control or through a

COM port. The microprocessor then setsup the DMA engine with a sourceaddress, destination address, and a blocklength. The processor writes a start bit tothe DMA engine and then “lets ‘er rip.”The DMA engine reads a sub-block fromthe source address, sends it to the 3DEScore for processing, and then writes theprocessed sub-block results to the desti-nation address.

Timers can be used to poll the DMAengine dma_done flag to know when theoperation is complete. The interrupt con-troller can also be used to signal the endof the 3DES operation.

The 3DES core uses a three-key con-catenated DES algorithm to provide 192bits of security. Keys can be stored in mem-ory or input through a software application,which is run on the secure microcontroller’smicroprocessor core. The microprocessorcontrols data movement to and from mem-ory. It also sets up the 3DES engine. Extramicroprocessor bandwidth is available foradditional application software. We used a32-bit microprocessor, although a XilinxMicroBlaze™ core could also be used inour secure microprocessor design. Figure 1is a flow diagram of an encryption/decryp-tion microcontroller device.

Reference DesignThe two main hardware components ofthe reference design are the microproces-sor core chip and a platform FPGA, suchas a Xilinx Spartan™ or Virtex device. Allof the functions (excluding the micro-processor) are implemented in the FPGAusing SoC Solutions’ IP platforms andsoft cores.

The secure microcontroller referencedesign provides the basis, or startingpoint, for the custom design. This imple-mentation uses the microprocessor toload memory, control the start of encryp-tion/decryption, and then verify the


EncryptedData In

DecryptedData Out

I/Oor

COMPort

µPControl

Memory

3DESCryptographic

ProcessorFigure 1 - Secure microcontroller data flow diagram

Co-Development is the KeyWe developed our secure microcontrollerin less than two weeks. Figure 2 shows thedevelopment method we used.

Week 1To get the design started quickly, we usedthe SoC Solutions PiP-EC02 pre-integratedembedded controller platform. The PiP-EC02 contained the needed microprocessorcontroller subsystem, which included anadvanced high-performance bus (AHB) andARM™ peripheral bus (APB) on-chip,interrupt controller, two timers, internalSRAM controller, 16550 UART, AHBarbiter, and external memory controller

(EBI). The IP block implementation isshown in Figure 3.

Next, we designed an interface for the3DES core to the AHB. We selected theAHB to enable fast DMA for 3DES pro-cessing. The 3DES interface and wrapperconsisted of a combination of a customDMA controller, input FIFO (16x32), out-put FIFO (16x32), and the 3DES core.The PiP-EC02 provided the AHB arbitertemplate. Using the arbiter template tomake the DMA connection to the systembus was a very simple design process.

The complete design was then simulatedusing a Mentor Graphics Modelsim XE(Xilinx Edition) simulator supplied byXilinx. The PiP-EC02 provided the AHBfunctional model (BFM), as well as all thetest fixtures we needed to test the micro-processor subsystem. We wrote a simple testbench to load memory, start the DMAengine, and then check the encrypted (ordecrypted) results that were stored backinto memory.

Week 2Now we were ready to try our design inreal hardware. To debug our secure micro-controller, we chose the SoC RDS02Rapid Development System – illustratedin Figure 4 – which allowed us to useMicrosoft Visual Studio™ tools to quicklymake software changes and debug thehardware on the fly. We used the XilinxChipScope™ integrated logic analyzer(ILA) to debug the actual design on theVirtex-E development board, shown inFigure 5. All of these tools were run on thesame computer. Stepping through codeand triggering the ILA was very easy.

Using the RDS02 proved to be anideal way to debug, because we triedmany, many software iterations. Eachiteration took only seconds to recompileand re-run. By comparison, the samesoftware iteration would have been farmore time-consuming if we had used typ-ical microprocessor development tools. Itwould have taken up to five minutes to

Started with PiP-EC02 as abase RTL design

Designed and integratedthe RTL code for 3DES

wrapper and DMA engine.

Simulated with Modelsim XE,

Synthesized with Synplify,

Routed with Xilinx ISE.

Designed a simple C/C++program using RDS02 API to

control secure micro hardware.

Debugged the hardware andsoftware using the RDS02.

Ported the design to a specificmicroprocessor.

Used the same FPGA hardwareand C/C++ code debugged with

the RDS02.

Week 1RTL Design and

Verification

Week 2Board Level Verification

and Debug


Watchdog

Timers

InterruptController

AHBifµP

AHBArbiter

EBI &SDRAM

Controller

FLASH

SRAM

SRAM

APBBridge

UARTs

GPIO

SDRAM

3DESCryptographic

Processor

SRAMController

DMA

FIFO

AP

BA

HB

PiP-EC02 + DES Engine

Figure 2 - Secure microcontroller development flow

Figure 3 - IP block implementation of secure microcontroller

reload the system flash memory using theJTAG port.

Once we were satisfied our securemicrocontroller hardware was solid and thesoftware was debugged, it was time to portthe design to a microprocessor. In ourexample, we ported the design to anARM7™ board called the “Brain Board,”shown in Figure 6.

Here again, we took advantage of thePiP-EC02. The PiP-EC02 package pro-vided the boot code and software driverswe needed for the UART, memory con-trollers, timers, and interrupt controller.As for software, all we had to do was addC/C++ code developed on the RDS02 –and modify the RDS02 API functioncalls to call ARM7 load and store func-tions. To do this, we used software-defined macros to retarget the APIfunction calls – nothing much to it.

The hardware port was also just a mat-ter of a simple edit to the AHB micro-processor interface and a Verilog,Synplicity, and Xilinx recompile.

We then retested the secure microcon-troller design on the Brain Board runningARM code, and we were done – a proto-type in less than two weeks.

Secure Microcontroller Features• PiP-EC02 embedded controller platform

• AHB, SRAM controller, interrupt con-troller, UART, timers, AHB – APBbridge, external bus interface, generalpurpose I/O

• 3DES cryptographic processor core

• DES – DMA controller

Conclusion3DES security is just the kind of value-addour customers are turning to as a way ofdifferentiating their products from thecompetition. By using a co-developmentapproach instead of coding the design firstand then synthesizing it, we were able todesign in security in less than two weeks.

For more information on SoCSolutions, visit www.xilinx.com/products/logicore/alliance/soc/soc.htm or [email protected].


Figure 6 - SoC Solutions’ “Brain Board”

Figure 5 - Virtex-E development board by Avnet

Figure 4 - SoC RDS02 Rapid Development System

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by Andrey Filippov, Ph.D.PresidentElphel, [email protected]

Just recently, Gordon Moore “renewed” hislaw for another decade, predicting that thedensity of integrated circuits will continueto double every 18 months. At this daunt-ing pace, how is it possible to keep up withthe ever-growing challenges of electronicsdesign? One answer is to effectively reusewhat others have done before, so you canfocus on the really new issues.

The growing number of successfuladoptions of the Free Software and OpenSource Software (FS/OSS) developmentmodels has proved the effective reuse ofsoftware in applications development.

Xilinx programmable logic devices rep-resent a “frontier” between the hardwareand the software worlds. They offer aunique opportunity to apply FS/OSS solu-tions to hardware design.

I strongly believe that the potential forsuccessful applications of the FS/OSSmodels to hardware design is even higherthan for software itself – you can alwaysmake a profit by selling the actual hard-ware. In this article I’ll show how thisapproach helped me to create a high-speed, high-resolution network camera (aclass of cameras that do not need addition-al computers to serve digital images andvideo over the LAN or the Internet).

BackgroundI had my first experience withGNU/Linux less than two years ago whenI realized I would have to program the net-work cameras I designed around theETRAX100LX processor. The processor,made by Axis Communications AB, wasoptimized for running GNU/Linux.Having the experience of designing manymicroprocessor-based systems that weremostly programmed in assembly lan-guages, I was really amazed that in just acouple of weeks my camera was able toserve JPEG images over a LAN usingHTTP protocol. It was possible to controlacquisition and view images using anystandard web browser.

Looking to bring the Free Software/Open Source Software movementinto the realm of hardware design, Andrey Filippov built a low-cost,high-performance network camera using a Spartan-IIE FPGA and freeWebPACK development software from Xilinx.

How to Use FreeSoftware in FPGAEmbedded Designs


That Model 303 camera combined soft-ware from multiple sources – GNU/Linuxitself, specific code for the ETRAX plat-form, and many, many others. I just had toadd specific drivers for my hardware andmodify some of the existent programs.What impressed me the most was the easeof navigation in big, third-party softwaresystems where I could find just the rightplace to insert small patches of code tomodify functionality.

Being primarily an electronics designer, Istarted to think it was possible to make sim-ilar productivity enhancements to the hard-ware/FPGA part of the camera system.

Design GoalsStarting the design of a new camera –Model 313, shown in Figure 1 – I had thefollowing goals in mind:

• A high-performance, simple networkcamera that fully supports the framerate/resolution of megapixel CMOS sen-sors. That means 15 fps at 1280x1024resolution (or proportionally, 60 fps at640x512 resolution, for example).

• Use a reconfigurable FPGA for imageacquisition/processing/compression –as opposed to two specialized ASICchips and one-time-only programma-ble devices (as was used in the model303 camera). That goal came from thefollowing requirements to:

– Simplify the product development.I estimated if that if I were to com-

I did not use that IP, however, because itwould prevent me from having an opensource design. So, I just used the IP specs as atemporary substitute for my own lack ofexpertise in Xilinx devices.

Knowing that my project was doable interms of hardware, I downloaded for freeWebPACK™ 4.2i software from the Xilinxwebsite to try it out. I wanted to see if therewas anything else I was not aware of, at themoment, that would prevent me from follow-ing my plan.

To get some initial experience with bothXilinx devices and software, I read XilinxApplication Note XAPP610 and decided totry an 8x8 DCT core (needed for JPEGcompression). The application note provid-ed Verilog sources, which allowed me tosynthesize, map, and place-and-route thedesign – but I had problems trying to simu-late the design.

It turned out that the “lite” version of athird-party simulator bundled for free withthe WebPACK software had limitations ondesign complexity. The most obvious prob-lem was the 500-line limit on the source code.The XAPP610 DCT implementation alonewas bigger, but I was able to try simulation byremoving comment lines and combiningmultiple lines into one.

The “lite” simulator did run, but thatworkaround trick would not work for mycomplete project, so I had to forget about thatsimulator and use something different.

All the rest of the WebPACK softwareworked just fine for me. Eventually, I was ableto utilize more than 98% of the chip’sresources to meet all of my timing constraints.

System ArchitectureNow that I knew I could fit my design to aSpartan-IIE, I switched to the schematicand PCB design. The Model 313 cameraconsists of two boards, shown in Figure 2.The small board has just the CMOS imagesensor and closely related circuitry.

The main board consists of a 1.48 by3.50 inch, four-layer PCB that has the fol-lowing principal components:

• 32-bit, 100 MHz processor(ETRAX100LX, AxisCommunications) running a

pletely troubleshoot a one-time pro-grammable FPGA by simulation, itwould be too difficult and time con-suming. On the other hand, theXilinx Spartan™-IIE XS300E chipwas five times higher (in gate count)than the biggest anti-fuse FPGA Iwas able to design. Having theoption to switch between simulationand actual hardware testing provedto be much more efficient.

– Make the system flexible withupgradeable “hardware” algorithmsin the same way as it is done withsoftware – this would significantlyincrease the lifespan of the product.

– Increase the number of possibleproduct applications by providing acustomizable development platform.

• Use free, downloadable developmenttools so you could customize my prod-uct without spending thousands ofdollars on software.

Selecting the Right FPGAWhen I started to think about the new cam-era design, my only FPGA experience waswith anti-fuse devices of up to 60K gates. So,I was open to consider different FPGAs thatmatched my design goals. (At that point, Iwas not even sure it was possible.)

Soon I came upon a good candidate. Itwas the largest (at that time) member of theXilinx Spartan-IIE family – a 300K-gateXS300E.

To find out if the XS300E wascapable of handling JPEG com-

pression of 1.3 megapixel imagesat 15 fps, I “window-shopped”for commercial IPs that per-formed similar tasks. I was ableto find some device utilization

specs that indicated that I wouldhave enough room to implement

all the functions I needed: frame bufferSDRAM control, image fixed patter noiseelimination, color space conversion, andCPU interfacing.


Figure 1 - Model 313 Elphel network camera

GNU/Linux operating system. Theprocessor has multiple embeddedperipherals, including a network MAC.

• 10/100 Mb Ethernet PHY(BCM2521A4KPT, Broadcom).

• 16 MB (4Mx32) SDRAM systemmemory (MT48LC4M32LFFC-8,Micron).

• 8MB (4Mx16) flash memory(MT28F640J3FS-12, Micron) used tostore GNU/Linux, applications, Webpages, configuration files, as well asbitstreams for the FPGA configuration.

• Spartan-IIE, 300K-gate, reconfig-urable FPGA (Xilinx XC2S300E-6FT256) used to controlimage acquisition, pro-cessing, frame storage inSDRAM, image compres-sion, and transfer to thesystem memory using theprocessor DMA channel.The FPGA is configuredusing JTAG pins con-nected to the general-purpose parallel port ofthe processor.

• Image memory, 16 MB(8Mx16) SDRAM(MT48LC8M16LFFF-8,Micron) connected direct-ly to the FPGA so thataccesses do not interferewith the system bus. Thismemory is dedicated tothe image frame bufferthat is used to store boththe uncompressed imagedata as well as calculatedcoefficients for the on-

the-fly FPN (fixed pattern noise) elimi-nation (subtraction of the backgroundframe and multiplying each pixel by itsreverse sensitivity).

• 3-PLL programmable clock generator(CY22393FC, Cypress). This part pro-vides fixed frequencies that have to beavailable during system startup (20MHz processor PLL input and 25MHz for the network PHY). It alsogenerates two programmable clocksthat add extra flexibility for FPGAoperation (in other words, it is possibleto compare simulation results with theactual maximal operation frequency forany particular module).

• IEEE 802.3af compliant power overLAN uses an isolated DC-DC convert-er to supply 3.3V from the input 48VDC. An additional converter pro-vides 1.8V to the Spartan core.

FPGA CodeMost of the system functionality is imple-mented in the Xilinx Spartan-IIE FPGA.The code is written in Verilog HDL and isavailable for download at my Elphel websiteunder the GNU/GPL (general publiclicense) license. It is designed around a four-channel SDRAM controller that usesembedded block RAM modules as “ping-pong” buffers to provide quasi-simultaneousblock access for the following data sourcesand receivers:

• Image data from the sensor, eitherprocessed or raw, one- or two-bytes perpixel, arranged as 256 (128) pixel lines

• Calibration data to the FPN eliminationmodule prepared by software in advance,128x16-bit blocks

• Data to the JPEG compressor, arrangedas square blocks of 16x16 bytes


Figure 2 - Main PCB of Model 313 camera

Figure 3 - The importance of the JPEG encoder in the Spartan-IIE dwarfs the other components on the PCB.

• CPU access to the SDRAM (normallyused to read raw sensor data and writeback the calibration data for the FPNelimination).

The JPEG encoder uses two-thirds of theFPGA resources, as shown in Figure 3. Theencoder consists of the chain of the process-ing modules, some of which use block RAMfor data buffering and table storage:

– Bayer-to-YCbCr converter

– 8x8 DCT based on the XilinxXAP610, modified to provide block-asynchronous operation and toincrease dynamic range

– Quantizator and zigzag encoder

– RLL encoder

– Huffman encoder

– Bit stuffer.

The output data is transferred to the sys-tem memory using the CPU DMA channel.

ResultsSince the Elphel Model 313 reconfigurable,high-resolution network camera was firstdescribed in the LinuxDevices online maga-zine Dec. 3, 2002 (and Dec. 4, in Slashdot),many of the inquiries I received have beenabout its open nature as a user-customizableplatform.

There are four possible kinds of cus-tomization of the camera. Three of them areinherited from the previous Model 303 cam-era and are related to the open software:

1. Modification of the user interface withWeb design tools

2. Addition of new applications (or modi-fication of existent ones) that can bedownloaded to the camera

3. Modification of the kernel (Linux) toadd new drivers.

However, only the use of the Xilinxreconfigurable FPGA – supported by thefree-for-download ISE WebPACK develop-ment tools – made it possible to increase thecamera performance nearly 100 times. Thishardware/software customization turned outto be the most powerful of the four possibletypes of customization:

4. Modification of the “heart” of the cam-era – the Spartan-IIE XS300E FPGA.

As of now, the camera has only a baselineJPEG compression algorithm implementedin the FPGA, which can serve still JPEGimages and Apple Quicktime movies that aremade of a sequence of the JPEG-encodedframes.

By adding new software to the cameraprocessor and HDL code to the FPGA, youcan use the camera for experiments withadvanced image/video compression algo-rithms – such as 2000JPEG for bettersize/quality still images or MPEG (-1, 2, 4)for video. Additionally, you could programthe camera processor and FPGA for motiondetection, pattern recognition, particle dis-crimination — or whatever else you maythink of.

ConclusionSo how did the FS/OSS approach help me tocreate the Elphel Model 313 camera? Maybeit did not cut my FPGA development time inthe same proportion as it did for the softwaredevelopment – the area where it is reallymature. But the overall FS/OSS co-designtechnique really worked:

• I used free Xilinx 2-d DCT imple-mentation that utilized about 30% ofthe chip resources. It did not meetexactly the requirements of my design– but this is where the advantage offree code is obvious: I could modifythe code in a way I liked. With closedproprietary IPs you can’t do this.

• The resultant product has unique fea-tures that I was desperately looking foras a customer. I wanted a camera Icould modify to fit my needs. In manycases, the required modifications Iwanted were really minor – but stillimpossible in a proprietary camera.

On several occasions I was asked, “Isn’tthat scary to open your design? What ifsomebody will use it and get all themoney?”

• First of all, the license used for theElphel products (GNU/GPL) is not exactly the same as the publicdomain. Any company that wants tomanufacture cameras based on Elpheldesigns will have to play by the samerules – the GPL legal protection is noweaker than that of closed sourceproprietary licenses.

• It is actually impossible to steal thiskind of an open design. Even if some-one in some far-away country (wherethere are no copyright laws and GPL isnot enforceable) manufactured a deriv-ative closed product, it would lack thecritical feature of Elphel cameras –their custom reconfigurability withSpartan FPGAs.

• Elphel has more cameras under devel-opment, and I would consider wideravailability of the products based onthe Model 313 design as free promo-tional material for my company.


URLs for more information:

• www.xilinx.com/spartan2e/ – Spartan-IIE FPGA family

• www.xilinx.com/ise/webpack5/ – latest free ISE WebPACK software

• www.xilinx.com/xapp/xapp610.pdf – Application Note XAPP610 “Video Decompression Using IDCT”

• www.elphel.com – schematics and software for Model 303 and 313 network cameras

• developer.axis.com/products/etrax100lx/ – Axis ETRAX 100LX platform

• www.fsf.org – Free Software Foundation

• www.opensource.org – Open Source™ Initiative

• www.linuxdevices.com – previous articles on network cameras.

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A new minimal HyperTransport™ (HT-Lite) reference design for Xilinx Virtex™-IIPlatform FPGAs enables rapid developmentof designs using Broadcom™ MIPS™-based processors. The Virtex-II FPGA lever-ages Xilinx flexible SelectIO™-Ultratechnology and Broadcom’s minimalHyperTransport IP to create a bridgebetween processors and ASSPs.

This reference design underscores thecompanies’ commitment to a technologyrelationship aimed at providing interopera-ble interfaces for use in communications,networking, and consumer applications.The HT-Lite reference design is one of sev-eral efforts resulting from Broadcom’s mem-bership in the Xilinx Reference DesignAlliance Program.

“Collaboration between companies likeBroadcom and Xilinx – both Hyper-

Transport Technology Consortium mem-bers – ensures that the HyperTransporttechnology will continue to satisfy the ever-increasing need for bandwidth,” saidGabriel Sartori, president of the consor-tium. “The reference design demonstrateshow HyperTransport technology enablesnext-generation networks by providing auniversal connection that reduces the num-ber of buses within a system, provides ahigh-performance link for embedded appli-cations, and enables highly scalable multi-processing systems.”

“By combining the highly flexibleXilinx Virtex-II FPGA solution with ourMIPS-based processors, OEMs can easilyadd additional features with minimalimpact to their design schedules,” saidKrishna Anne, strategic marketing man-ager of Broadcom’s Broadband ProcessorBusiness Unit.

The HT-Lite reference design is used as aslave interface to end an HT chain support-ing an 8-bit link width at a design speed of400 MHz DDR (800 Mbps per I/O). TheHT-Lite core uses fewer than 1,900 slices ina Virtex-II FPGA.

The HT-Lite reference design is availablenow free of charge. Documentation andinstructions for downloading the referencedesign can be found at www.xilinx.com/xapp/xapp639.pdf. Customers in need of afull-featured HyperTransport solution canuse the full HT core, also available now atwww.xilinx.com/ipcenter/.

Xilinx Virtex-II Platform FPGAs and Broadcom’s MIPS-based processors enable rapid development of gigabit Internet protocol products.

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by Grant Stockton President & CEOTechnovare Systems, [email protected]

Tough economic conditions and cost sen-sitivity are making it difficult for designersof commercial and industrial equipmentto provide the one feature customersrequest most – network connectivity.Network connectivity and the ability tomanage systems from a Web interface arehighly valued. But implementing them hasremained elusive because companies donot want to design them in as a standardfeature during an economic downturn.

The proliferation of interface and communication standards from industry to industry has made it difficult to get systems talking to each other. A configurable low-cost board solves the problem.

Low-Cost IP Connectivity Lets Diverse Systems Communicate


Technovare’s Network EnabledProcessor™ (NEP) board shown in Figure 1provides an off-the-shelf solution to thisdilemma by letting system designers inte-grate networking into their feature setquickly and without the expense of anadditional design cycle.

The NEP board integrates an embeddedWeb server that performs all of the process-ing and services required for network con-nectivity such as TCP/IP, SNMP, HTTP,Telnet, and FTP. A key enabling feature ofthe NEP board is a user-definable interfaceimplemented by a Xilinx Spartan™ FPGA.

The Spartan FPGA’s flexibility andconfigurability allows host systems to com-municate with the NEP board using anydigital format, protocol, or standard.

Standard interfaces such as RS-232 andRS-485 are available on all versions of theNEP board. Once TCP/IP processing hastaken place, data can be sent out over astandard network connection consisting ofa single 10/100 BaseT Ethernet port.

Cores for many parallel and serialinterfaces such as I2C, SDLC, EPP, USB,and CAN are available and can be inte-grated on request.

In addition to providing you with anetwork-connectivity solution, the NEPboard is also a generic processing platformthat can offload your host system of com-puting overhead and even run an entireembedded application. Equipped withMotorola’s 5272 Coldfire™ 32-bit RISCprocessor, Wind River Systems’VxWorks™ RTOS, 4 Mbytes of SDRAM,and 16 MB of flash RAM, the NEP boardis a formidable processing platform formany embedded applications. Its primaryfeatures are shown in Table 1.

added, you will find the communicationprotocol that you employ most frequentlyis often not sufficient to handle the system’sbandwidth requirements. To address thisproblem, the NEP board incorporates ahigh-speed Ethernet connection. Systemsthat are now communicating over low-speed interfaces such as RS-232 can easilymigrate to IP-based Ethernet.

The NEP board’s unique user-definedinterface allows applications to take fulladvantage of 10/100 BaseT Ethernet datarates by allowing parallel and high-speedserial connectivity to the host system.

Just as every industry has its own com-munications protocol, every system usu-ally has its own user interface. Theproliferation of interfaces generallyrequires user-interface software on thehost computer that communicates withthe system via RS-232, USB, or someother standard interface. Any other hostcomputer wanting to communicate withthe system must first be loaded with theinterface software and be directly con-nected to the system.

This problem is alleviated with theNEP board’s embedded Web server. Anyhost computer with a Web browser canlog into the system from any location onthe entire Internet – with proper authori-zation – and have access to the user inter-face that runs on the NEP board.

Equipped with a 32-bit RISC proces-sor, 4 MB of SDRAM, and 16 MB offlash memory, the NEP board’s Web serv-er can serve sophisticated Web pages con-sisting of HTML-based pages and Javascript. For systems that require morememory space, a PCMCIA expansioncard will be available shortly.

ConclusionThe NEP board delivers a user-friendly,Web-based interface that creates networkconnectivity to everyday existing systems.The board’s affordable price – about $150for 1,000-unit orders – lets system designersintegrate their applications into existingand future systems without affecting costor product delivery schedules. For moreinformation, visit Technovare’s website atwww.technovare.com.

Solving Problems for Diverse ApplicationsMost commercial and industrial applica-tions have developed their own set of stan-dards, protocols, and communicationinterfaces based upon their own uniquerequirements.

CAN is widely used in the industrial-automation market, for example, and two-wire communication is widely used inbuilding-automation applications. Theconvergence of industry-specific commu-nications protocols such as these with IP-based Ethernet has created a large numberof nodes in which translation from onenetwork to another is required.

The NEP board is ideal for these appli-cations. It provides pre-configured com-munications interfaces for many standardprotocols as well as the ability to createcustom interfaces for ones that do notalready exist. Its interface translation capa-bility between UART and 10/100 BaseTEthernet permits easy integration intoexisting computer and control systems.

As systems mature and more features are


• Programmable interface implemented bySpartan FPGA

• 10/100 BaseT Ethernet interface

• Dual UART interfaces for RS-232 and RS-485 to support serial data transmission,translation, and control

• USB1.1 interface transmits up to 12 Mbpsserial data

• 4 MB SDRAM, 16 MB flash memory

• 32-bit Motorola ColdFire™ microprocessor

• VxWorks™ real-time operating system withembedded TCP/IP stack

• Remote configuration and in-circuitfirmware update capability

• PC/104 form factor.

Figure 1 - NEP board TSINET100BT32C

Table 1 - NEP board features

by Jasbinder BhootSenior Manager, Strategic Solutions Xilinx, [email protected]

Toshio Takahashi Technical Manager International [email protected]

Digital signal processors (DSPs) andmicrocontrollers have traditionally beenused for digital motor-control applicationsin both low-performance AC inverterdrives and high-performance servo drives.But a new generation of applications ispushing their performance limits.

Motor control requires both torqueand speed control. Torque control is

achieved by regulating the motor cur-rent. It requires high-performance com-putation in the range of tens ofmicroseconds. Speed control, on theother hand, requires relatively moderatecomputation speeds, typically in therange of hundreds of microseconds.

Both functions are usually implement-ed by a DSP or microcontroller. A motion-control ASIC is sometimes added tocomplete high-performance functionssuch as the PWM (pulse-width modula-tion) waveform generator, encoder signalinterface, and so forth.

Many demanding servomotor applica-tions such as high-speed factory automa-tion systems and fly-by-wire/drive-by-wirevehicle control systems require higher lev-els of timing performance than ever before.

DSPs and microcontrollers can no longerkeep pace with the new generation of appli-cations that require not just higher perform-ance but more flexibility as well – withoutincreasing cost and resources. InternationalRectifier Inc. provides an answer in itsAccelerator™ Motor Control DesignPlatform. The Accelerator platform lever-ages low-cost Spartan™ FPGA technologyto provide a re-configurable signal-process-ing architecture that uses soft peripherals. It achieves unmatched motor-control per-formance with feedback-control-loop band-widths of up to 5 KHz.

New Challenges in Motor ControlA class of new motor-control applicationsthat require both high performance and theflexibility to support a variety of motor-

Platform Delivers Fast, Flexible AC Servomotor-Control Designs


Platform Delivers Fast, Flexible AC Servomotor-Control Designs New digital motor-control applications exceed the capabilities of conventional solutions. International Rectifier’s Accelerator platform solves this problem and reduces development time by eliminating programming, coding, debugging, and code maintenance.

New digital motor-control applications exceed the capabilities of conventional solutions. International Rectifier’s Accelerator platform solves this problem and reduces development time by eliminating programming, coding, debugging, and code maintenance.

feedback scenarios cannot be served economically by off-the-shelf DSPs andmicrocontrollers. These devices have threeinherent limitations:

1. Traditional DSPs and microcontrollersused fixed hardware logic to imple-ment motion peripherals and commu-nication ports. This limits your abilityto adapt the design to different typesof feedback devices and peripherals.

2. High-end servomotors require signifi-cant computation power for torquecontrol. A single DSP or microcon-troller cannot always meet perform-ance requirements. Multiple DSPs ormicrocontrollers are needed, oftenwith an ASIC to perform the motion-control tasks. This not only adds costbut also introduces complex function-al partitioning.

3. DSPs and microcontrollers require ahigh level of support to maintain thetorque algorithms. Although themaintenance task is easier if the algo-rithms are written in a high-level language such as C, they are typicallywritten in assembly language.

Typical Servo-Drive Control ArchitectureIn a typical digital closed-loop servo controlsystem, functions are divided into subtasksthat operate at different update rates depend-ing on the available bandwidth and process-ing priority. For example, certain tasks needto be implemented in real-time while others

Functions that are far from the machineside and closer to the host communication(or a man-machine interface) requiremuch slower processing. These tasks areusually very complex and require a largeamount of memory. Torque control, forexample, can be implemented using a sim-ple step function, but position coordina-tion and interpolation require many morecontrol parameters and therefore requiremore memory.

Motor control is made even morecomplex by a chain-reaction phenome-non. Torque control requires higher per-formance than speed control, forexample, but the impact on systemrequirements does not stop there. Theintegral of torque is speed and the inte-gral of speed is position. Due to thischain reaction, each parameter requires adifferent processing speed. A real-timeoperating system is needed to satisfy thesevarious processing speeds.

Standalone DSPs Can’t Cut It!In order to meet the challenges, moststandalone motion-control DSPs mustincrease memory resources for program-ming and data. Even this many not solvethe problem because software solutions forlogic peripherals are difficult to implementwithout sacrificing performance.

Stated in numerical terms, the torque-control loop computation update rate for

may be delayed. Or there may be tasks thatare one-time driven events. Each task is con-trolled by a multitasking operating systemthat is closely coupled with a DSP’s or micro-controller’s interrupt structure.

Figure 1 shows a functional overview ofa typical servo-drive system. The computa-tional requirements can be divided intotwo segments:

1. A hardware-rich environment for tasksthat require very fast computation

2. A software-intensive environment fortasks in which performance in lesscritical; software implementation,however, requires additional memorybandwidth and programming effort.

Programmer

Software-IntensiveEnvironment

Hardware-RichEnvironment

- Lots of memory- Fast computation- No dedicated hardware

- Less memory- Fastest computation- Motion Peripheral Hardware

Multi-AxisDrop

UserI/O

Milliseconds Tens ofnano-

seconds

Nano-seconds

Hundreds ofmicroseconds Tens of

microseconds

Micro-seconds

Networking

HostCOMM

SequencingPLC

PositionCoordinate

andInterpolation

SpeedControl

Closed-Loop

TorqueControl

HostCOMM

PowerManagement

Peripheral

Gate Driverand

Protection

CurrentSensing

Power Module

Encoder

BLDCServoMotor

PC

RS-232C

or

RS-422

Parallel

Interface

SPI

Interface

Host

Register

Interface

+ +

+

+ +

- -

-

MonitoringRegisters

ConfigurationRegisters

FLT_CLR

FAULT

BRAKE

select

1/T CounterSpeed

Measurement

QuadratureDecoding

Period/dutyCounters

Period/dutyCounters

DeadTime

DC Bus DynamicBrake Control

A/DInterface

SpaceVectorPWM

Ks

2/3ejθ

ejθ

dt

FPGA (Spartan-II -300)

Accelerator Chip Set

IR2137

IR2175

IR2175

Encoder

or

Resolver

AnalogFilter

ResolverReference

A/D MUX

AC Power

Analog SpeedReference

DC BusFeedback

Multi-AxisHost

or

Other HostController

Motor

Figure 1 - Servomotor drive system functional overview

Figure 2 - Accelerator block diagram


a servo drive must be in the 25-microsec-ond range to achieve 4-KHz torque band-width. There are also a wide range ofemerging motion functions that requirevery specific programming, fast computa-tion, and unique digital logic. Uniquelogic of this type includes dead time compensation, monitoring the tempera-ture of the power devices, accurate motor-phase voltage-feedback sensing, currentsensing, and motor-machine parameters.These functions require speeds in thenanosecond range.

Implementing motion functions in anASIC plus a DSP also presents a challengebecause it requires functional partitioning. Allclosed-control functions (including torquecontrol, speed control, and positioning) are

implemented in the DSP or microcontroller.Motion-peripheral functions are implement-ed in a dedicated ASIC.

Dividing tasks between two ICs is nec-essary because torque control demands amuch faster computation update rate andit becomes extremely difficult to performtorque control and the other controlfunctions. Therefore, the traditionalapproach of using a DSP or microcon-troller – with or without an ASIC – israpidly approaching the point of beingunable to satisfy performance demand,faster development time, and easy, low-cost software maintenance.

The Accelerator PlatformInternational Rectifier’s Accelerator plat-form is a complete reconfigurable motor-drive-control design platform. Based on theXilinx Spartan FPGA family, it providesthe flexibility needed for many motionperipheral types as well as the high band-width needed for torque control. Flexibilityis achieved by providing various object-code sets, which are used to reprogram theFPGA as needed.

Figure 2 shows a block diagram of theAccelerator system. All necessary controlalgorithms are implemented in theSpartan-II FPGA, including the logic for

the communication protocol. The pro-grammable nature of the FPGA I/O allows direct interfacing to InternationalRectifier’s high-voltage ICs, the IR2137and the IR2175, which control and senseelectrical power to the motor.

FPGA Technology Makes the DifferenceSpartan-II FPGAs deliver the performancethat allows critical control functions to beimplemented in hardware rather than soft-ware. By implementing these parameters inhardware, latency and execution time donot vary: The solution is inherently fastand deterministic. The FPGA-based solu-tion provides computation speed of thecurrent-control function well below 5microseconds, which in turn enables highPWM carrier frequency update. The FPGAalso allows the torque-control loopresponse to reach 5 KHz at the -3 dB point.This high-bandwidth torque control loopprovides low harmonic current ripple.Interfacing with recently introduced low-inductance servomotors such as linearmotors becomes much easier.

Customizable Motion-Peripheral LogicServo applications require many differenttypes of interface circuits to accommodatea variety of sensors and feedback devices.


Host

Register

Interface

ConfigurationRegisters

MonitoringRegisters

RS-232C/RS-422Interface

SPISlave

Interface

ParallelInterface

IQLIM+IDREF

IQREF

SPDKI VelocityControlEnableSPDKP

STARTSTOP

DIRFLTCLR

SYNCFAULT

PWM ACTIVE

RCV

17DataAddressControl

CSSDI

SDOSCK

CTSRTS

SND

INT_REF

EXT_REF

AccelRate

SequenceControl

DecelRate

IQLIM-

RAMP+ + +

+

+ +

+- -

-

+

VDLIM+VDLIM-

VQLIM-CURKI

CURKPPI

PI

PIVD VDS

VQSVQ

VQLIM+

I1 x I2I3

I1I2

SlipGain Slip Gain

Enable

Zpol

InitZval

GSenseLGSenseU ModScl

MaxEncCount

SpdScale

AngleScale

InitZ

EncType

OptionalCurrent Sense

OptionalCurrent Sense

FeedforwardPath Enable

4096

40960

IQ Scale

IQ

ID

IV

IW

4096IQ Scale

I3IO

I1 x I2I3

0I2 I3

I1

I1 x I2I3

0I2 I3

I1

CurrentOffset W

MotorPhase

Current V

EncoderA/B/Z

GateSignals

FAULT

BRAKE

MUX

CNVST

8-ChannelSerial A/DInterfaceCLK

DATA

EncoderHall A/B/C

MotorPhase

Current W

CurrentOffset V

DtimePWMmode

PWMen 2Pen

3

3

6

2

2

DCV_FDBK

Closed Loop Velocity Control, Sequencing ControlUpdate Rate = PWM Carrier Frequency / 2

Closed Loop Current ControlUpdate Rate = PWM Carrier Frequency x1 or x2

dt

2/3

IR2175 Interface

QuadratureDecoding

SpaceVector PWM

DC Bus DynamicBrake Control

A/DInterface

DeadTime

IR2175 Interface

ejθ

ejθ

Communication Modules

Figure 3 - The Accelerator motor-control platform

Figure 4 - Detailed control function block diagram

Motor-position sensors may be either anencoder or resolver, for example, dependingon the specific application requirements.There are many different types of encoders,such as incremental, absolute, sine, cosine,or serial-data types. Each requires very dif-ferent logic to implement. By leveraging theprogrammable nature of the FPGA,Accelerator can support multiple types offeedback devices without changing thephysical hardware.

Accelerator Platform – HardwareConstructionThe Accelerator platform is pictured inFigure 3. It is rated to handle up to 1.5-KWoutput with a 300% overload for 1 second.Its continuous power rating is 230V/7Arms.Position feedback is implemented using anincremental encoder interface with an indexmarker pulse. Accelerator can support either115 V or 230 V AC single- or three-phaseinputs. The system is also equipped with avariety of protection circuits ranging fromover-current protection, short-current pro-tection, and over-temperature protection aswell as over-voltage protection.

The Accelerator platform integrates thelatest chipsets from International Rectifier –the IR2137 and the IR2175. The IR2137 isa monolithic 600-V high-voltage gate driverwith built-in over-current protection. The IR2175 is a monolithic 600-V current-sensing IC in a SO8 package. These twohigh-voltage ICs teamed with the XilinxSpartan-II FPGA device simplify the com-plicated design task of analog and powerelectronics circuits such as gate drivers, pro-tection, and current-sensing functions.

System Design Flow and ConfigurationThe Accelerator platform comes with allthe hardware and software needed to designa complete high-performance motor-control system. It supports an encoder-based servo amplifier, resolver-based servoamplifier, and a sensorless control algo-rithm. Each of these products can belicensed from International Rectifier.

You can configure the control structure,tune the regulator control loop, and choosevarious communication protocols withoutrigorous programming effort. Figure 4 shows

a block diagram illustrating configurationcapability. Configuration switches are locat-ed at each control section. An inductionmachine, for example, can be configured byenabling the slip-gain block and adjustingID and IQ current feedback scaling gains.

The Accelerator platform includes atoolbox for designing control algorithmsusing graphically connected control blocks.The toolbox contains the Control BlockLibrary, which is a complete set of controlprimitives available in Simulink™. It canbe expanded when needed to create uniqueperipheral blocks. The Accelerator platformalso uses a unique Matlab™-to-VerilogPorter (MVP) tool, where the Verilog codeis generated, synthesized, and directlydownloaded into the Xilinx Spartan-IIFPGA to configure functionality. Thismethod relieves you of considerable manu-al translation or re-hosting effort.

Accelerator comes with a Verilog librarythat contains servo-specific, parameterized,fully tested motion-peripheral circuit mod-ules. A current-sensing interface module,encoder-feedback module, and PWMwaveform generator are examples of uniquemotion peripheral modules.

Figure 5 shows the impact of theAccelerator platform on the resources neededto develop a servo-drive system in compari-

son to the traditional DSP-based approach. The Accelerator system significantly

reduces the development time of a servodesign by eliminating programming, coding, debugging, and code maintenance.

ConclusionThe Accelerator platform provides a low-cost solution for servomotor drive designsand still maintains the levels required for today’s high-performance, permanent-magnet, and induction machine control systems. The platform is based on a XilinxFPGA device that allows flexibility for cus-tomized functions without compromisingthe time-critical machine control functions.Low cost is achieved in two ways:

• DSP functions are implemented inparallel using FPGA devices. Thisapproach removes the need for usingmultiple standalone DSPs.

• A proven, flexible hardware architec-ture allows rapid development of com-plete systems, which drastically reducesthe resources required for rapid systemdevelopment.

The Accelerator platform is availabletoday directly from International Rectifier.Additional details can be found atwww.irf.com.


Motion Profile/SequencingSystem Integration

Total Manpower= 1.2 man-weeks

Total Manpower= 105 man-weeks

Low-CostCustomized Servo

IRACS201/IRACO201Design Platform

Accelerator Approach

NetworkingHost Interface

Configuration (1 man-day)Mechanical Part Adaptation

(1 man-week)

Motion Profile/SequencingSystem Integration

High-Cost, High-RiskCustomized Servo

Software Design(44 man-weeks)

Hardware Design(28 man-weeks)

Mechanical Design(Nine man-weeks)

Traditional Approach

NetworkingHost Interface

Drive Integration/Verification Test(24 man-weeks)

Figure 5 - Servo-drive design process comparison

by Peter BergsmanAssociate EditorXilinx, [email protected]

On the morning of December 14, 2002,the ground shook at the YoshinobuLaunch Range at the Tanegashima SpaceCentre, on the island of Tanegashima insouthern Japan. The 170-foot H-IIArocket streaked aloft, carrying with it aXilinx XQR4062XL, part of theXC4000XL series FPGA. This radiation-hardened FPGA is the core of the high-performance computing (HPC-I) payloadincorporated in the Australian scientificmission satellite FedSat (Figure 1). Thespacecraft was developed by theCooperative Research Centre for SatelliteSystems (CRCSS) in Australia. TheHPC-I payload (Figure 2) was developedfor CRCSS at the Queensland Universityof Technology.

FPGAs have flown in space before, butHPC-I is the first intentional use byCRCSS of reconfigurable computingtechnology (RCT) in the standard opera-tion of a spaceborne computing system.

A radiation-hardened Xilinx FPGA gives the Australian FedSat satellite powerful reconfigurable computing capabilities.

Xilinx FPGA Blasted into Orbit


Source: National Space Development Agency of Japan (NASDA)

Xilinx FPGA Blasted into OrbitA radiation-hardened Xilinx FPGA gives the Australian FedSat satellite powerful reconfigurable computing capabilities.

According to Anwar Dawood, CRCSSprincipal research scientist and programleader, “Traditional fixed computer hard-ware is designed to perform a diverse rangeof functions. This results in an efficientprocessing for some tasks and a slow pro-cessing for other tasks, especially the recur-sive and intensive computing jobs.”Furthermore, fixed computer hardware isinflexible and unable to adopt changeswhen newly created functions are required,he added.

Dawood pointed out that RCT offersthe promising alternative of flexible hard-ware, which can be reconfigured – eitherby remote command or dynamicallythrough its own internal operations – tospecialize its function to an arbitrary rangeof demanding applications.

The Xilinx-based HPC-1 is the proto-type with which Dawood and his teamexpect to establish the viability of RCT inspaceborne computing – including the tol-erance of the hardware to the intense radi-ation of outer space.

Second-Generation HPC-IIDawood and the HPC team are now devel-oping a second-generation HPC-II, whichis built around the increased capacity andcapability of a Xilinx FPGA. This second-generation project will emphasize criticalspace applications and onboard real-timedata processing.

Dawood has initiated several applica-tion projects to exploit the efficiencies ofspace-based RCT, including:

• Disaster Detection and MonitoringSystem (DDMS) uses HPC technolo-gy for real-time or near-real-timeimage processing for detecting andmonitoring natural disasters,such as forest fires and volcanicplumes.

• Satellite-Based BroadbandServices (SBBS) utilizesHPC technology to pro-vide multimedia commu-nications, Internet access,and education services toboth urban and ruralareas.

The reconfigurability of Xilinx FPGAsenables satellites to be rewired without hav-ing to be retrieved. This raises the promiseof adaptable spacecraft that could be recon-figured remotely to work around problems– or even be able to repair themselves.Retired spacecraft might also be reconfig-ured for new purposes.

An example of a catastrophic satellite losswas described by Mark Long in a February 5article for e-inSITE (www.e-insite.net). In1998, Hughes Space and Communicationsannounced that electrical shorts were themost likely cause of a string of failures

involving the spacecraft control processors(SCPs) onboard its 601 flight models.

The SCPs controlled the satellites’ crit-ical functions, including propulsion

for attitude control, solar wing posi-tioning, and antenna pointing.

Investigators finally traced theproblem to a tin-plated latchingrelay that served as an on/offswitch within the SCPs.Under certain combined con-ditions, the switch was shortedout by a tiny, crystallinegrowth less than the width of ahuman hair.

• Satellite Autonomous NavigationSystem (SANS) deploys HPC technol-ogy in conjunction with advanced GPSfor onboard orbit determination forautonomous navigation.

Fail-Safe DesignAvoiding catastrophic satellite failure is anequally compelling motive for remotereconfiguration. Entire satellite constella-tions have been lost through tiny failures incomputing circuitry.


Figure 1 - FedSat spacecraft prior to launch (courtesy FedSat Project Team)

Figure 2 - HPC-1 payload (courtesy FedSat Project Team)

If the satellite operators had the abilityto reconfigure their SCP systems on the fly,they might have found a way around theelectrical shorts that led to the untimelydemise of their satellite constellation.

Radiation-HardenedIn the same article, Long pointed outanother potential application for radiation-hardened Xilinx products in the onboardsignal processing systems of advanced, next-generation satellite computer platforms.

Later this year, Hughes will launch thefirst of its Spaceway satellite platforms. Theseplatforms will feature onboard processors

developed by TRW. The TRW processorshave been designed to provide high-speed,onboard processing capabilities that willallow signals to pass directly between smallaperture terminals without requiring theintervention of a gateway terminal.

The potent combination of onboarddigital signal processing, packet switch-ing, and spot-beam technologies isexpected to enable single-hop connectivi-ty throughout each of the system’s manybeam coverage areas.

Similar technology is also expected tofly on two Astrolink satellites being con-structed by Liberty Media.

ConclusionThe technology being developed by Xilinxfor space-based applications promises tofurther enhance the capabilities of next-generation satellites to act as broadbandrouters in the sky.

For more information on Xilinx radiation-hardened FPGAs, visitwww.x i l inx . c om/produc t s /mi l i t a r y /radhardv.htm.

To learn more about CRCSS, high-performance computing, and the FedSatsatellite, go to www.crcss.bee.qut.edu.au/comp.shtml and www.crcss.csiro.au/.


Space is a hostile environment. Streams of high-energy particles constantly bombard any exposed object. The Earth’satmosphere provides a strong, protective barrier that absorbs most of this radiation. Satellites, however, are located well outside this protective shield, and their electronic circuitry is especially vulnerable to damage that might lead to catastrophic failure.

According to Howard Bogrow, marketing manager for the Xilinx Aerospace and Defense Products Division, high-energy particles can cause a secondary reaction in untreated silicon-based chips that can cause their circuits to latch up.To address this problem, the XQR4000XL devices utilize a 0.35 micron epitaxial CMOS process that provides latch-upimmunity, high total-ionizing dose (TID) tolerance, and low probability of single event upsets (SEUs) induced by natural radiation in satellite and other space environments.

Radiation-Tolerant FPGAs in Space

Xilinx is currently shipping radiation-hardened versions of two device families:

• 4000XL with up to 130,000 gates, certified radiation tolerant to 60 Krads

• Virtex™ FPGAs with up to one milliongates, certified to 100 Krads.

Later this year, a radiation tolerant line ofQPro™ Virtex-II series FPGAs with up tosix million gates will be released (Figure 3).

To determine the radiation tolerance ofthe company’s products, Xilinx conductsextensive testing of their TID(www.xilinx.com/prs_rls/radhard.html) andSEU characteristics (www.support.xilinx.com/support/techxclusives/1000-techX35.htm).

TODAY 2003 2004 2004

0.18µ

0.22µ

0.35µ

0.15µ

0.13µ

DCM Multiplier XCITE TripleDES 840 Mbps LVDS IP Immersion• Block RAM

• High • DLLs

• RocketIO• PowerPC

••••••

TODAY 2003 2004 2004

0.18µ

0.22µ

0.35µ

0.15µ

0.13µ

100Krads(Si)

5V tolerant buffers

3.3V - 62K gates

2.5V - 1M gates

3.3V tolerant buffers

60Krads(Si)

1.5V - 6M gates

1.5V >10M gates

System-LevelFunction Blocks

Platform FPGA

DCM Multiplier XCITE TripleDES 840 Mbps LVDS IP Immersion

Platform forProgrammable

Systems

• Block RAM• High • DLLs

• RocketIO• PowerPC

••••••

XQR4000XL

Figure 3 - Roadmap for radiation-tolerant FPGAs

by Bill OkuboSolutions Marketing Group, Global ServicesXilinx, [email protected]

The Xilinx Productivity Advantage (XPA)Program is designed to close the “design gap”by providing the tools and skills you need todevelop efficient, effective, FPGA-based programmable systems. Now, MyXPA offersyou a way to manage yourXPA Program to deliverthe highest possible value.

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MyXPA is a convenient, personalized, online management tool that helps Xilinx customers take full advantage of their custom XPA Program.

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I tried to check if she really understood that, so I gave her a different example.

This was the result:

David KutzThree engineering students were gathered together discussingthe possible designers of the human body.

One said, “It was a mechanical engineer. Just look at all thejoints.”

Another said, “No, it was an electrical engineer. The nervoussystem has many thousands of electrical connections.”

The last one said, “Actually it was a civil engineer. Who elsewould run a toxic waste pipeline through a recreational area?”


FUZZY LOGICFUZZY LOGIC

Scott CampbellThree engineers and three IRS agents are traveling by train to a conference. At the station, the three IRS agents each buy tickets and watch as the three engineers buy only a single ticket.

“How are three people going to travel on only one ticket?” asks an agent. “Watch and you’ll see,” answers an engineer.

They all board the train.

The IRS agents take their respective seats, but all three engineerscram into a restroom and close the door behind them.

Shortly after the train departed, the conductor comes around collecting tickets. He knocks on the restroom door and says, “Ticket, please.”

The door opens just a crack and a single arm emerges with aticket in hand. The conductor takes it and moves on.

The agents saw this and agreed it was quite a clever idea. So afterthe conference, they decide to copy the engineers on the return tripand save some money.

When they get to the station, they buy a single ticket for the returntrip. To their astonishment, the engineers do not buy a ticket at all.

“How are you going to travel without a ticket?” says one perplexedIRS agent.

“Watch and you will see,” answers an engineer. When they boardthe train, the three agents cram into a restroom and the three engineers cram into another one nearby.

The train departs. Shortly afterward, one of the engineers leaves his restroom and walks over to the restroom where the IRS agentsare hiding.

He knocks on the door and says, “Ticket, please.”

Keith Dellinger How can you tell introverted engineers from extroverted engineers?

Introverted engineers look at their own shoes. Extroverted engineerslook at your shoes.

lim 1x – 8x 8

= ∞

lim 1x – 5x 5

= 5

In the Spring 2003 issue of Xcell Journal, we asked our readers to find nine “diamonds” on the pages of the magazine. The task was to note the page number where each diamond was found, add up the page numbers of each diamond, and send the sum to us with a good clean joke. The top five winners with the correct number and a joke (that we could print) would each win a HandSpring™ Visor Pro™ PDA.

For the record, the nine page numbers were 14, 17, 36, 45, 52, 61, 66, 96, and 110. The correct sum was 497.

And the winners are:

Xilinx Alliance EDA Members and Products

Alatekwww.alatek.comHardware acceleration (HES)

Altiumwww.altium.com/products/nvisage.htmComplete PCB/FPGA design flow(nVisage) targeting Spartan™ Series FPGAs

Apache Designwww.apache-da.com/Products/nspice.htmHSPICE®-compatible simulator using actual S-parameter data (NSPICE) forVirtex-II Pro™ MGT-based PCB design

Apluswww.aplus.comArchitecture-specific synthesis and layoutoptimization for Virtex™-II series FPGA(PALACE™)

Aptixwww.aptix.comASIC emulation (Prototype Studio™)

Atrentawww.atrenta.comRTL Linter technology for Virtex-II seriesFPGAs (SpyGlass®)

Cadence Design Systemswww.cadence.com/feature/fpga_design.htmlVirtex-II Pro MGT support for high-speedPCB design (SPECCTRAQuest®); NCSimfamily for FPGA design simulation; SPWfor DSP data path development on FPGAs

Celoxicawww.celoxica.comC-level design creation, compilation, andverification for Virtex-II and Virtex-II ProFPGAs

Endeavorwww.endeav.comCo-verification for Virtex-II Pro(CoSimple™)

EVEwww.eve-team.comRTL-level Simulator Accelerator (ZEBU)

Forte Designwww.forteds.comHLL compiler to RTL (Cynlib Tool Suite);timing specification and analysis tool(TimingDesigner)

Future Design Automationwww.future-da.comANSI-C algorithms to RTL models(SystemCenter)

Hierarchical Design Inc. (HDI)www.hierdesign.comHierarchical floorplanning and analysissoftware for Virtex-II series FPGAs

Mentor Graphicswww.mentor.comVirtex-II Pro MGT support for high-speedPCB design (HyperLynx™, ICX™,Tau™); complete FPGA design flow usingthe ModelSim® family of simulators andLeonardo-Spectrum™/Precision® synthesis;Seamless® co-verification support forVirtex-II Pro

Novilitwww.novilit.comDesign partitioning using ISE EDK(AnyWare) for Virtex-II series FPGAs

Product Acceleration Inc.www.prodacc.comFPGA symbol generation(LiveComponent™) and automated pinassignment optimization and PCB layercount control (DesignF/X)

Simucadwww.simucad.comVerilog Simulator for FPGAs (Silos)

Synopsyswww.synopsys.comVirtex-II Pro multigigabit transceiver support for high-speed PCB design(HSPICE®); FPGA Compiler II™ RTLsynthesis for Virtex series FPGAs;VCS™(MX)/Scirocco™(MX) simulators;Formality® formal verification, LEDA®

RTL linter, and PrimeTime™ static timing analysis; high-level design usingCoCentric™ System C Compiler andCoCentric System Studio

Synplicitywww.synplicity.comRTL synthesis (Synplify®), debugger technology (Identify®), and physical synthesis (Amplify®) for all Xilinx FPGAs

Translogicwww.translogiccorp.comFPGA symbol generation for fast PCBdesign iterations (FPGA Connector™) for Virtex-II series FPGAs

Verplexwww.verplex.comFormal verification technology for Virtex-IIseries FPGAs (Conformal™ LEC)



Xilinx AllianceCORE Third-PartyIP Providers and Products

Alcatel Technology Licensing Groupwww.ind.alcatel.com/emac/Ethernet media access controller coresUnited States

Amphion Semiconductor Ltd.www.amphion.comDSP, wireless communications, and multimedia coresUnited States

Barco-Silexwww.barco-silex.comDSP cores, with a specialization in image-audio applicationsBelgium

CAST, Inc.www.cast-inc.comGeneral purpose IP for processors, perhipherals, multimedia, networking,encryption, serial communications, and bus interfacesUnited States

Crossbow Technologies, Inc.www.crossbowip.comSystem Interconnect IP for on-chip andchip-to-chip multiprocessingUnited States

Deltatec S.A.www.deltatec.be/IP and services for digital imaging, DSP,multimedia, PCI, and datacomBelgium

Derivation Systems, Inc.www.derivation.com

IP cores for high-assurance hardware/software applications and embedded systems products; 32-bit Java processor coreUnited States

Digital Communications Technologies, Ltd.www.dctl.comEmbedded JAVA solutionsUnited Kingdom

Digital Core Designwww.dcd.pl/Microprocessor, microcontroller, floating point, and serial communicationcontroller coresPoland

Dolphin Integrationwww.dolphin.fr/Bus interface, processor, peripheral, and DSP cores; EDA softwareFrance

Duma Video, Inc.www.dumavideo.comDigital video, AES/EBU audio, MPEGand DCT cores; real-time MPEG-2 HD and SD compressionUnited States

eInfochips Pvt. Ltd.www.einfochips.comPCI, USB, 80186, multimedia, and wireless coresUnited States

Eureka Technologywww.eurekatech.comCores for SoC designs based on PCI andsupporting PowerPC™, ARM, MIPS,ARC, and SH2/SH4 processorsUnited States

GV & Associates, Inc.www.gvassociates.comBoards and expertise in DSP, processor,software, analog, and RF designUnited States

iCoding Technology, Inc.www.icoding.comTurbo Code-related error correction products including system designUnited States

Intrinsyc, Inc.www.intrinsyc.comSingle board embedded computers (FPGA + external processor); peripheral IPUnited Kingdom

Loarant Corporationwww.loarant.comProprietary 16-bit RISC CPU; embeddedsystem designUnited States

MEET Ltd.www.meet-electronics.comIP cores dedicated to industrial servomotor controlSwitzerland

Memec Corewww.memeccore.comPeripheral, bus interfaces, encryption, and communications coresUnited States

ModelWare, Inc.www.modelware.comDatacom/telecom cores including ATM,HDLC, POS, IMA, UTOPIA, and bridgesUnited States

NewLogic GmbHwww.newlogic.at/Cores for wireless applications includingBluetooth and 802.11Austria

Paxonet Communicationswww.paxonet.comSolutions for interworking metro networking technologies to SONETUnited States

Perigee, LLCwww.perigeellc.comDSP and image processing cores; embeddedfirmware, GUI, and application softwaredevelopmentUnited States

RealFast Operating Systems ABwww.realfast.se/Real-time systems and RTOS; operatingsystem coresSweden

SOC Solutions, L.L.C.www.socsolutions.comEmbedded uP and software; networking,wireless, audio, GPS, and handheld; peripheral coresUnited States

X I L I N X P A R T N E R Y E L L O W P A G E S

SysOnChip, Inc.www.sysonchip.co.kr/IP and products for CDMACellular/PCS/WLL modem, FEC, andBluetoothRepublic of South Korea

Telecom Italia Lab S.p.A.www.idosoc.com/soc/viplibrary/main.jsp?screen=viplibraryCores for ATM, optical networking, and switched digital video broadcast equipmentItaly

Tensilica, Inc.www.tensilica.comConfigurable processors cores and development toolsUnited States

TurboConceptwww.turboconcept.comTurbo Code forward error correction solutionsFrance

Virtual IP Groupwww.virtualipgroup.comCores for microcontrollers, telecommunica-tion, datacom, PC peripherals, and businterface standardsUnited States

Wipro, Ltd.www.wipro.comIP building blocks for technologies like IEEE 1394, USB, Bluetooth, and IEEE 802.11United States

Xylon d.o.o.www.logicbricks.comHuman-machine interfaces and industrialcommunication controllersCroatia

Zuken, Inc.www.zuken.co.jp/soc/PCI2.2, 10/100 Ethernet, and gigabitEthernet coresJapan

Reference Design PartnersThe Xilinx Reference Design AllianceProgram builds partnerships with industry-leading semiconductor manufacturers todevelop reference designs for acceleratingour customer’s product and system time tomarket. The goal is to build a library ofhigh-quality, multicomponent system-levelreference designs in the areas of networking,communications, image and video processing, DSP, and emerging technolo-gies and markets.

Agere Systemswww.agere.com

AMCCwww.amcc.com

Analog Deviceswww.analog.com

Bay MicroSystemswww.baymicrosystems.com

BitBlitz Communicationswww.bitblitz.com

Broadcom Corp.www.broadcom.com

Centilliumwww.centillium.com

Congnigine Corporationwww.cognigine.com

Cypress Semiconductorwww.cypress.com

IBM Microelectronicswww.ibm.com/us/

IDTwww.idt.com

Ignis Opticswww.ignis-optics.com

Infineon Technologies AGwww.infineontechnologies.com

Intel Corporationdeveloper.intel.com/design/network/

Intrinsitywww.intrinsity.com/home.htm

Micron Technologywww.micron.com

Motorolawww.motorola.com

Octasic Semiconductorwww.octasic.com

PMC-Sierra Inc.www.pmc-sierra.com/index.html

SiberCore Technologieswww.sibercore.com

Teracrosswww.teracross.com/~web/

Texas Instrumentswww.ti.com

TransSwitch Coporationwww.transwitch.com/index_flash.jsp

Velio Communications, Inc.www.velio.com

Vitessewww.vitesse.com

West Bay Semiconductor Inc.www.westbaysemi.com

ZettaComwww.zettacom.com

Xanoptixwww.xanoptix.com




XPERTS Partners

3T BVwww.3T.nl/Design services; measurement instruments;fail-safe controlling; medical equipment,communication, and computer peripherals

Accent S.r.l.www.Accent.it/Complex FPGAs; SoCs; PowerPCs; IP-platforms; software, PCB, and ICfoundry services, from concept to silicon

ADI Engineeringwww.adiengineering.comReference designs; custom designs; designservices focused on Intel IXA and XScale

Advanced Electronic Designs, Inc.www.aedbozeman.comDesign services and manufacturing support;hardware and software design for embeddedsystems

Advanced Principles Group, Inc.www.advancedprinciples.comDesign services and consulting; softwarealgorithm acceleration and application-specific computing systems

Alpha Datawww.alpha-data.comPCI/PMC/CPCI FPGA boards; embeddedapplications using HDL or SystemGenerator methodologies

AMIRIX Systems Inc.www.amirix.comDesign services for electronic product realization; high-performance digital boards;programmable logic; embedded software

Andraka Consulting Group, Inc.www.andraka.comExclusively FPGAs for DSP since 1994;applications include radar, sonar, digitalcommunications, imaging, and video

Array Electronicswww.array-electronics.de/SoC/FPGA/PCB designs in telecom, industrial, and DSPs; concepts; verification;prototypes; cores

Avnet Design Serviceswww.ads.avnet.comEmbedded processing FPGA design services; Virtex-II Pro; high-speedSERDES; IP Core integration; timing closure; RLDRAM; RapidIO™

Baranti Group Inc.www.baranti.comAward-winning design/manufacturing firm;expertise in digital video, FPGAs

Barco Silexwww.barco-silex.comTotal solutions consisting of IP, FPGA, and board design

Benchmark Electronics Inc.www.bench.comEMS/JDM team; product design, support,introduction, and launch into volume production

Birger Engineering, Inc.www.birger.comDevelopment of algorithms, electronics,and systems for digital imaging

BitSim ABwww.bitsim.comDesign services; DSP, video, 3G, andWLAN designs; high-speed prototypingboards

Bottom Line Technologies Inc.www.bltinc.comFPGA, product, and system design services;networking; data communications;telecommunications; video; PCI; signalprocessing; military; aerospace

CES Design Services @ Siemens Program and System Engineeringwww.ces-designservices.comPlatform-oriented SoC/FPGA/PCB andfirmware design in telecom, industrial, andvideo processing; customized solutions;concept; verification; prototypes

CG-CoreEl Programmable Solutions P. Ltd.www.cg-coreel.comDesign services; telecom, networking, andProcessor IP and designs; turnkey FPGA;RTL design/validation

Chess iT/Embeddedwww.chess.nl/Embedded hardware and software design ofproducts and services at the chip, board,and system level

Colorado Electronic Product Design, Inc.www.cepdinc.comDesigning embedded systems with FPGAs for DSP; interfaces for medical,consumer, aerospace, and military

Comit Systems, Inc.www.comit.comHigh-end FPGA/SoC design services,including the integration of customer-developed and third-party IP

ControlNet India Pvt Ltd.www.controlnetindia.comASIC/SoC Analog/RF FPGA design services; IP development; domains:Ethernet, IEEE1394, USB, security, PCI,WLAN, Infiniband

Convergent Design LLCwww.convergent-design.comAudio/video design for professional/consumer products

DATA Respons ASAwww.datarespons.comProfessional design and development services for embedded hardware/softwaresolutions; FPGA/digital hardware applica-tion specialists

Deltatec International Inc.www.deltatec.be/Design services; digital imaging applica-tions; broadcast video, image processing and image synthesis

Digicom Answers Pty Ltd. www.fpga.com.au/Design services; experienced FPGAresources; design-on-demand; pre-designadvice; reviews and problem solving

Digital Design Corporation (DDC)www.digidescorp.comDesign services and products; image pro-cessing; video; communications; DSP;audio; automotive; controls; interfaces



Dillon Engineering, Inc.www.dilloneng.comDesign services; FPGA-based DSP algorithms; high-bandwidth, real-time digital signal and image processingapplications

DRS Tactical Systems West Inc.(formally Catalina Research)www.catalinaresearch.comDesign services; FPGAs for DSP, includingthe manufacturer of Virtex reconfigurablecomputing boards

Eden Networks, Inc.www.edennetworks.comTurnkey design services; telecom and net-working designs (Ethernet, SONET, ATM,VoIP)

Edgewood Technologies, LLCwww.edgewoodtechnologies.comDesign services; FPGAs for telecom, DSP,embedded processors

Enea Data ABwww.enea.se/Telecommunication, data communication,DSP, RTOS, automotive, defense, high-reliability, and consumer electronics design

Enterpoint Ltd.www.enterpoint.co.uk/Design services; development boards; video,telecommunications, military, and high-speed design

ESD Inc.www.esdnet.comDesign services; FPGAs for embedded systems, software/hardware design, PCBlayout

Evatronix S.A.www.evatronix.pl/Design services; FPGA design (Virtex,Virtex-E, Spartan-II); embedded systems;SoCs and SoPCs designs

Evermore Systems Inc.www.evermoresystems.comDesign services; FPGA designs for commu-nications, audio/video, wireless, and homenetworking

ExaLinx www.exalinx.comDesign services; ASIC emulation for high-speed communications and wireless appli-cations; reference designs

Fidus Systems Inc.www.fidus.ca/Design services; FPGAs; communications;video; DSP; interface conversions; ASICverification; hardware; PCB layout; soft-ware; SI/EMC

First Principles Technology, Inc.www.fptek.comDesign/assembly/test services; FPGA +PCB + DSP/processor + system; imaging;video; test; satellite telecom; control

Flexibilis Oywww.flexibilis.comIP development; FPGA design services;Linux device drivers

Flextronics Designwww.flextronics.com/design/Complete product design and developmentservices for high-speed communications;reconfigurable computing; imaging;audio/video; military

GDA Technologies, Inc.www.gdatech.comA leading services company focused ondesigning systems, SoC, ASIC, FPGA, and IP

HCL Technologieswww.hcltech.comHigh-speed board, ASIC, and FPGAdesign and verification services in avionics,medical, networking/telecom, consumerelectronics

Helion Technology Limitedwww.heliontech.comDesign services and IP for FPGA with afocus on data security, wireless, and DSP

IDERS Inc.www.iders.ca/Contract electronic engineering and EMSresource, providing complete product cyclesranging from specifications to production

Image Technology Laboratory Corporationwww.gazogiken.co.jp/Design services; FPGAs for image process-ing; design tools: EDK, System Generator,and Forge

INITEC AGwww.initec.ch/Design services for system design; FPGAapplications in telecommunication systemsand medical electronics

Innovative Computer Technologyictconn.comDigital, analog, Xilinx FPGA, and softwaredesign solutions for customers in a widevariety of industries throughout the UnitedStates

iWave Systems Technologies Private Ltd.www.iwavesystems.comEmbedded hardware and software design;board design; FPGA and ASIC develop-ment services

Liewenthal Electronics Ltd.www.liewenthal.ee/Embedded systems design services; develop-ment of software and hardware includingVirtex and Spartan FPGAs

Logic Product Developmentwww.logicpd.comFull-service product development, includingindustrial design, mechanical, electrical, andsoftware engineering

M&M [email protected] services; imaging; video, audiodesigns; high-density ASIC emulation

Memondo Graphicswww.memondo.comImplementation of digital signal processing,communications, and image processingsolutions and algorithms over Xilinx FPGAs

Mikrokrets ASwww.mikrokrets.no/FPGA development comprising telecom-munication, network communications, andembedded systems; PCB development



Millogic Ltd.www.millogic.comDesign services and synthesizable cores; expertise in PCI, video, imaging,DSP, compression, ASIC verification, communications

Milstar Inc.www.Milstar.co.il/Design services and manufacturers (industrial and military specs); DSP; communication; video; audio; high-speed boards

Misarc srl - Agratewww.misarc.comDesign services and manufacturers;telecommunications, SoC development, and test equipment boards using FPGAsolutions

Multi Video Designswww.mvd-fpga.comDesign services; DSP for video, telecom-muications; SoC with Virtex-II/Pro andSpartan (PowerPC/MicroBlaze™); Xilinxtraining

Multiple Access Communications Ltd.www.macltd.comDesign services; products and consultancy;DSP for wireless communications

Nallatechwww.nallatech.comEmbedded reconfigurable computers forhigh-performance applications in DSP,imaging, and defense; Xilinx DiamondXPERTS

NetQuest Corporationwww.netquestcorp.comTurnkey engineering design and produc-tion services in advanced high-speedembedded communications

North Pole Engineering Inc.www.northpoleengineering.comHardware and software design services forFPGA, ASIC, and embedded systems

Northwest Logicwww.nwlogic.comPCI, PCI-X, and SDRAM controller IP;high-end FPGA design services

NovTech Engineeringwww.novtech.comBoard-level and IP cores; turnkey designservices; imaging; communication; PCIcores; encryption

NUVATIONwww.nuvation.comDesign services; imaging and communica-tions for defense/security, medical, con-sumer, and datacom/telecom markets

Plextek Ltd.www.plextek.comDesign services; FPGA, DSP, radio,microwave, and microprocessor technolo-gies for defense and communications

POLAR-Designwww.polar-design.de/High-end FPGA design for telecom, networking, and DSP applications

Polybus Systems Corporationwww.polybus.comTest patterns; customizable in-systemFPGA test patterns; design services; net-working and communications

Presco, Inc.www.prescoinc.comTwenty-five years of experience in customelectronics design/manufacturing for high-performance image processing, data com-munications, inkjet

Productivity Engineering GmbH www.pe-gmbh.comDesign services; PCI design; microproces-sor cores; obsolete component replace-ments; ASIC prototyping

Programall Technologies Inc.www.ProgramallTechnologies.comDesign services; embedded systems target-ing Virtex, Spartan, Virtex-II, and Virtex-IIPro FPGAs

R&D Consulting972-9-7673074 FPGA development; video; imaging;graphics; DSP; communications

Rapid Prototypes, Inc.www.FPGA.comDesign services; high-performance reconfig-urable FPGA applications requiring maxi-mum speed or density using physical designprinciples

RDLABSwww.rdlabs.comFPGA/ASIC design; wireless communica-tions; 802.11b/a IP cores; Matlab, Sysgen,ModelSim; instruments HP1661A,HP8594E, HP54520A

RightHand Technologies, Inc.www.righthandtech.comDesign services; Virtex-II Pro FPGAs,boards, and software for video gaming, storage, medical, wireless

Rising Edge Technology Inc.www.risingedgetech.comComplete design solutions from the groundup; FPGA interface designs

Riverside Machines Ltd.www.riverside-machines.comDesign services and project management;DSP, wireless, network, and processor development; Verilog, VHDL, SystemC,Specman

Roke Manor Researchwww.roke.co.uk/Design services; IP, ATM, DSP, imaging,radar, and control solutions for FPGAs

Roman-Jones, Inc.www.roman-jones.comDesign services; FPGAs for embeddedmicroprocessors; PCI; DSP; low-cost 8051softcore

Sapphire Computers, [email protected] design consulting; high-speeddigital and FPGA design

Siemens AG, Electronic Design Housewww.eda-services.comDesign services; system-on-chip; ASICs;FPGAs; IPs; DSPs; boards; EMC; embedded software; prototypes



Silicon & Software Systems Ltd. (S3)www.s3group.comWorld-class electronics design companyuniquely combining IC, FPGA, software,and hardware design expertise

Silicon Interfaces America Inc.www.siliconinterfaces.comDesign services; develops IP in areas of networking, wireless, optical, datacom,interconnect, and microcontrollers

Silicon System Solutions P/Lwww.silicon-systems.comDesign services; FPGAs for very high-speedapplications including communications andDSP applications

Siscad S.p.A.www.siscad.it/Xilinx FPGA design services; IP development and integration

Smart Logic, Inc.www.smart-logic.comDesign services; FPGAs for rapid prototyping including imaging, compres-sion, and real-time control

SoleNet, Inc.www.solenet.netFPGA, board, and system designs for wire-less, telecommunications, consumer, andreference design applications

so-logic electronic consultingwww.so-logic.netEmbedded systems (PowerPC,MicroBlaze); system-level design (Forge, SystemGenerator, Handel-C);Xilinx training centers (Austria, Eastern Europe)

Styrex ABwww.styrex.se/Design services for embedded systems; programmable logic, hardware develop-ment, and microprocessor programming

Synopsys Professional Serviceswww.synopsys.comDesign services to solve your design challenges in system-level design, RTLdesign, and physical design

Syntera ABwww.syntera.se/Design services; FPGAs for radar, digitalcommunications, telecom automotive, aerospace, and DSP

Tachyon Semiconductorwww.tachyonsemi.comDesign services for portable computing,networking, and embedded systems

Tao of Digital, Inc.www.taoofdigital.comHigh-speed, large-gate-count SoC designsusing IP cores for maximum modularityand efficiency

Technolution B.V.www.technolution.nl/Innovative hardware and software solutions

Thales Airborne Systemswww.thalesgroup.com/airbornesystemsProvider and integrator with high expertisein FPGA design for radars, DSP, and com-munications

TietoEnator R&D Services ABwww.TietoEnator.comEuropean design services for telecom,industrial IT, and automotive; Xilinx exclu-sive training provider in Scandinavia

V-Integrationwww.V-Integration.comProviding first-pass success in complexFPGA designs; applications include imag-ing, communications, and interface design

Williams Consulting, [email protected] systems hardware and software;video; MPEG; control

Zaiq Technologies, Inc.www.zaiqtech.comDesign; partitioning and timing conver-gence; VIP; platform experts for embeddedcomputer, networking, wireless, andinstrumentation


Synplicity offers a wide range of software products for FPGA and ASIC designers. Synplicity products are fast, easy-to-use, and most importantly, provide the best Quality of Results. Synplicity's products support industry-standard languages (VHDL and Verilog) and run on most popular platforms.

Visit us at:www.synplicity.comor send an e-mail to:[email protected] learn more

Millogic IP isXilinx Proven!

• PCI-X, VME, 12C,Video, LZS, PS2

• Design Services• Prototyping• Xilinx Xperts

Millogic, Ltd.6 Clocktower PlaceMaynard, MA [email protected]

Will the RealDigital™

CPLD please stand up.

If you are not using the latest breakthrough in

CPLD technology, you are not getting the most out of your CPLD. Only the

new 1.8V CoolRunner-II RealDigital CPLD from Xilinx, offering a 100% digital

core, gives you the performance, low power, and features you are looking for

with no price premium.

The best system performance in the industry

CoolRunner–II RealDigital CPLDs feature

the most I/O per macrocell, as well as advanced

I/O interfacing that includes HSTL and SSTL.

Plus, they deliver system performance in

excess of 500 MHz with the industry’s lowest

dynamic and standby current as low as 12 µA

— lower than any other 1.8V device! The

unique Clock Divider also means no more

dividing the clock off-chip. Best of all, RealDigital CPLDs

deliver all this performance in the smallest, most secure

design package available.

Get the new CoolRunner-II Design Kit

Get started now with the new CoolRunner-II Design Kit,

including a populated board, programming cable, design guide, plus software and

resource CDs… all for under fifty dollars!

Just contact your local Xilinx distributor or

visit www.xilinx.com/coolrunner2

to order your kit today. And don’t forget

the new CoolRunner-II RealDigital CPLDs

are fully supported by the easy-to-use

ISE WebPACK™ tool, which you can

download FREE right now.

www.xilinx.com/realcpld

© 2003, Xilinx Inc. All rights reserved. The Xilinx name and the Xilinx logo are registered trademarks, CoolRunner, WebPACK are trademarks, and The Programmable Logic Company is a service mark of Xilinx Inc. All other trademarks and registered trademarks are the property of their respective owners.

1.8V CORE VOLTAGE CPLD COMPETITIVE CHARTManufacturer Xilinx Lattice Altera

Device Family CoolRunner-II ispMACH4000C ispMACH4000Z None

Standby Current 12 µA 1,800 µA 20 µA N/A

Internal Performance 500 MHz 400 MHz 265 MHz N/A

Clock Divider/Doubler YES/YES NO/NO NO/NO N/A

Max Density (Macrocells) 512 512 128 N/A

I/O Standards Support LVTTL, LVCMOS, LVTTL, LVCMOS LVTTL, LVCMOS N/AHSTL, SSTL

I/O Banks (max) 4 2 2 N/A

Spartan-3 1.2V FPGA Family:Introduction and OrderingInformationAdvance Product SpecificationDS099-1 (v1.0) April 14, 2003

IntroductionThe 1.2V Spartan™-3 family of Field Programmable GateArrays is specifically designed to meet the needs of highvolume, cost-sensitive consumer electronic applications.The eight-member family offers densities ranging from50,000 to five million system gates, as shown in Table 1.

The Spartan-3 family builds on the success of the earlierSpartan-IIE family by increasing the amount of logicresources, the capacity of internal RAM, the total number ofI/Os, and the overall level of performance as well as byimproving clock management functions. Numerousenhancements derive from state-of-the-art Virtex™-II tech-nology. These Spartan-3 enhancements, combined withadvanced process technology, deliver more functionalityand bandwidth per dollar than was previously possible, set-ting new standards in the programmable logic industry.

Because of their exceptionally low cost, Spartan-3 FPGAsare ideally suited to a wide range of consumer electronicsapplications, including broadband access, home network-ing, display/projection, and digital television equipment.

The Spartan-3 family is a superior alternative to mask pro-grammed ASICs. FPGAs avoid the high initial cost, thelengthy development cycles, and the inherent inflexibility ofconventional ASICs. Also, FPGA programmability permitsdesign upgrades in the field with no hardware replacementnecessary, an impossibility with ASICs.

Features• Very low cost, high-performance logic solution for

high-volume, consumer-oriented applications

- Densities as high as 74K logic cells- 325 MHz system clock rate- Three separate power supplies for the core (1.2V),

I/Os (1.2V to 3.3V), and special functions (2.5V)• SelectIO™ signaling

- Up to 784 I/O pins- 622 Mbps data transfer rate per I/O- Seventeen single-ended signal standards- Six differential signal standards including LVDS- Termination by Digitally Controlled Impedance- Signal swing ranging from 1.14V to 3.45V- Double Data Rate (DDR) support

• Logic resources- Abundant, flexible logic cells with registers- Wide multiplexers- Fast look-ahead carry logic- Dedicated 18 x 18 multipliers- JTAG logic compatible with IEEE 1149.1/1532

standards• SelectRAM™ hierarchical memory

- Up to 1,872 Kb of total block RAM- Up to 520 Kb of total distributed RAM

• Digital Clock Manager (up to four DCMs)- Clock skew elimination- Frequency synthesis- High-resolution phase shifting

• Eight global clock lines and abundant routing• Fully supported by Xilinx ISE development system

- Synthesis, mapping, placement and routing

R

©2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.


Table 1 – Summary of Spartan-3 FPGA Attributes

DeviceSystem Gates

Logic Cells

CLB Array (One CLB = Four Slices) Distributed

RAM (bits1)Block RAM

(bits1)Dedicated Multipliers DCMs

Maximum User I/O

Maximum Differential

I/O PairsRows Columns Total CLBs

XC3S50 50K 1,728 16 12 192 12K 0 0 0 124 56

XC3S200 200K 4,320 24 20 480 30K 216K 12 4 173 76

XC3S400 400K 8,064 32 28 896 56K 288K 16 4 264 116

XC3S1000 1M 17,280 48 40 1,920 120K 432K 24 4 391 175

XC3S1500 1.5M 29,952 64 52 3,328 208K 576K 32 4 487 221

XC3S2000 2M 46,080 80 64 5,120 320K 720K 40 4 565 270

XC3S4000 4M 62,208 96 72 6,912 432K 1,728K 96 4 712 312

XC3S5000 5M 74,880 104 80 8,320 520K 1,872K 104 4 784 344

Notes: 1By convention, one Kb is equivalent to 1,024 bits.


Spartan-3 1.2V FPGA Family: Introduction and Ordering InformationR

Architectural OverviewThe Spartan-3 family architecture consists of five funda-mental programmable functional elements:

• Configurable Logic Blocks (CLBs) contain RAM-basedLook-Up Tables (LUTs) to implement logic and storageelements that can be used as flip-flops or latches.CLBs can be programmed to perform a wide variety oflogical functions as well as to store data.

• Input/Output Blocks (IOBs) control the flow of databetween the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plusthree-state operation. Twenty-three different signal standards, including six high-performance differentialstandards, are available as shown in Table 2. DoubleData Rate (DDR) registers are included. The DigitallyControlled Impedance (DCI) feature provides automaticon-chip terminations, simplifying board designs.

• Block RAM provides data storage in the form of 18 Kbdual-port blocks.

• Multiplier blocks accept two 18-bit binary numbers asinputs and calculate the product.

• Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing,delaying, multiplying, dividing, and phase shifting clocksignals.

These elements are organized as shown in Figure 1. A ringof IOBs surrounds a regular array of CLBs. Those devicesranging from the XC3S200 to the XC3S2000 have two col-umns of block RAM embedded in the array. The XC3S4000and XC3S5000 devices have four RAM columns. Each col-umn is made up of several 18 Kb RAM blocks; each blockis associated with a dedicated multiplier. The DCMs arepositioned at the ends of the outer block RAM columns,making up a total of four. The XC3S50, the lowest costmember of the family, has neither block RAM, nor dedicatedmultipliers, nor DCMs.

The Spartan-3 family features a rich network of traces andswitches that interconnect all five functional elements,transmitting signals among them. Each functional elementhas an associated switch matrix that permits multiple con-nections to the routing.

Figure 1 – Spartan-3 Family Architecture

DS099-1_01_032703

Notes: 1. The two additional block RAM columns of the XC3S4000 and XC3S5000

devices are shown with dashed lines. The XC3S50 device does not have any block RAM, multipliers, or DCMs.



ConfigurationSpartan-3 FPGAs are programmed by loading configurationdata into robust static memory cells that collectively control allfunctional elements and routing resources. Before poweringon the FPGA, configuration data is stored externally in aPROM or some other nonvolatile medium either on or off theboard. After applying power, the configuration data is writtento the FPGA using any of five different modes: MasterParallel, Slave Parallel, Master Serial, Slave Serial andBoundary Scan (JTAG). The Master and Slave Parallelmodes use an 8-bit wide SelectMAP™ Port.

The recommended memory for storing the configurationdata is the low-cost Xilinx Platform Flash PROM family,which includes XCF00S PROMs for serial configurationand XCF00P PROMs for parallel configuration.

I/O CapabilitiesThe SelectIO feature of Spartan-3 devices supports 17single-ended standards and six differential standards aslisted in Table 2. Table 3 shows the number of user I/Osas well as the number of differential I/O pairs available foreach device/package combination.

Table 2 – Signal Standards Supported by the Spartan-3 Family

Standard Category Description VCCO (V) Class Symbol

Single-Ended

GTL Gunning Transceiver Logic N/A Terminated GTL

Plus GTLP

HSTL High-Speed Transceiver Logic 1.5 I HSTL_I

III HSTL_III

1.8 I HSTL_I_18

II HSTL_II_18

III HSTL_III_18

LVCMOS Low-Voltage CMOS 1.2 N/A LVCMOS12

1.5 N/A LVCMOS15

1.8 N/A LVCMOS18

2.5 N/A LVCMOS25

3.3 N/A LVCMOS33

LVTTL Low-Voltage Transistor/Transistor Logic 3.3 N/A LVTTL

PCI Peripheral Component Interconnect 3.0 33 MHz PCI33_3

SSTL Stub Series Terminated Logic 1.8 N/A SSTL18_I

2.5 I SSTL2_I

II SSTL2_II

Differential

LDT Lightning Data Transport (HyperTransport™)

2.5 N/A LDT_25

LVDS Low-Voltage Differential Signaling Standard LVDS_25

Bus BLVDS_25

Extended Mode LVDSEXT_25

Ultra ULVDS_25

RSDS Reduced-Swing Differential Signaling 2.5 N/A RSDS_25



Product Ordering and AvailabilityTable 4 shows all valid device ordering combinations ofdevice density, speed grade, package, and temperature

range parameters for the Spartan-3 family as well as theavailability status of those combinations.

Table 3 – Spartan-3 User I/O Chart

Device

Available User I/Os and Differential (Diff) I/O Pairs

VQ100 TQ144 PQ208 FT256 FG456 FG676 FG900 FG1156

User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff

XC3S50 63 TBD 97 46 124 56 - - - - - - - - - -

XC3S200 63 TBD 97 46 141 62 173 76 - - - - - - - -

XC3S400 - - - - 141 62 173 76 264 116 - - - - - -

XC3S1000 - - - - - - 173 76 333 149 391 175 - - - -

XC3S1500 - - - - - - - - 333 149 487 221 - - - -

XC3S2000 - - - - - - - - - - 489 221 565 270 - -

XC3S4000 - - - - - - - - - - - - 633 300 712 312

XC3S5000 - - - - - - - - - - - - 633 300 784 344

Notes: 1. All device options listed in a given package column are pin-compatible.

Table 4 – Spartan-3 Device Availability

Device

Package Type: VQFP TQFP PQFP FTBGA FBGA

No. of Pins: 100 144 208 256 456 676 900 1156

Code: VQ100 TQ144 PQ208 FT256 FG456 FG676 FG900 FG1156

Speed Grade

XC3S50 Commercial devices offered in the -4 and -5 speed grades; industrial devices offered in the -4 speed grade.

(C, I) (C, I) (C, I) - - - - -

XC3S200 (C, I) (C, I) (C, I) (C, I) - - - -

XC3S400 - - (C, I) (C, I) (C, I) - - -

XC3S1000 - - - (C, I) (C, I) (C, I) - -

XC3S1500 - - - - (C, I) (C, I) - -

XC3S2000 - - - - - (C, I) (C, I) -

XC3S4000 - - - - - - (C, I) (C, I)

XC3S5000 - - - - - - (C, I) (C, I)

Notes: 1. C = Commercial: TJ = 0° to +85° C; I = Industrial: TJ = –40° C to +100° C.2. Parentheses indicate that a given product is not yet released. Contact sales for availability information.


Xilinx Virtex FPGA Products

Plat

form

FPG

As

CLB Resources Memory Resources DSP Clock Resources I/O Features Speed

Syst

em G

ates

(see

not

e 1)

CLB

Arra

y (R

ow X

Col

)

Num

ber o

f Slic

es

Logi

c Ce

lls (s

ee n

ote

2)

CLB

Flip

-Flo

ps

Max

.Dist

ribut

ed R

AM B

its(kb

its)

# 18

kbi

ts B

lock

RAM

Tota

l Blo

ck R

AM (k

bits

)

# 18

x18

Dedi

cate

d M

ultip

liers

DCM

Fre

quen

cy (m

in/m

ax)

# DC

M B

lock

s(s

ee n

ote

3)

Digit

ally C

ontro

lled

Impe

danc

e

Max

imum

Diffe

rent

ial I/

O Pa

irs

Max

.I/O

I/O S

tand

ards

Com

mer

cial S

peed

Gra

des

(slo

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t to

fast

est)

Indu

stria

l Spe

ed G

rade

s(s

low

est t

o fa

stes

t)

Seria

l PRO

M F

amily

Syst

em A

CE

Conf

ig.M

emor

y (B

its)

Rock

etIO

™Tra

nsce

iver B

lock

s

Pow

erPC

Pro

cess

or B

lock

s

Virte

x-II

Serie

s Ea

syPa

thSo

lutio

n (s

ee n

ote

4)

Virtex-II Pro Family — 1.5 VoltXC2VP2 * 16 x 22 1,408 3,168 2,816 44 12 216 12 24/420 4 YES 100 204XC2VP4 * 40 x 22 3,008 6,768 6,016 94 28 504 28 24/420 4 YES 172 348XC2VP7 * 40 x 34 4,928 11,088 9,856 154 44 792 44 24/420 4 YES 196 396XC2VP20 * 56 x 46 9,280 20,880 18,560 290 88 1,584 88 24/420 8 YES 276 564XC2VP30 * 80 x 46 13,696 30,816 27,392 428 136 2,448 136 24/420 8 YES 372 644XC2VP40 * 88 x 58 19,392 43,632 38,784 606 192 3,456 192 24/420 8 YES 396 804XC2VP50 * 88 x 70 23,616 53,136 47,232 738 232 4,176 232 24/420 8 YES 420 852XC2VP70 * 104 x 82 33,088 74,448 66,176 1,034 328 5,904 328 24/420 8 YES 492 996XC2VP100 * 120 x 94 44,096 99,216 88,192 1,378 444 7,992 444 24/420 12 YES 572 1,164XC2VP125 * 136 x 106 55,616 125,136 111,232 1,738 556 10,008 556 24/420 12 YES 644 1,200Virtex-II Family — 1.5 VoltXC2V40 40K 8 x 8 256 576 512 8 4 72 4 24/420 4 YES 44 88XC2V80 80K 16 x8 512 1,152 1,024 16 8 144 8 24/420 4 YES 60 120XC2V250 250K 24 x16 1,536 3,456 3,072 48 24 432 24 24/420 8 YES 100 200XC2V500 500K 32 x 24 3,072 6,912 6,144 96 32 576 32 24/420 8 YES 132 264XC2V1000 1M 40 x 32 5,120 11,520 10,240 160 40 720 40 24/420 8 YES 216 432XC2V1500 1.5M 48 x 40 7,680 17,280 15,360 240 48 864 48 24/420 8 YES 264 528XC2V2000 2M 56 x 48 10,752 24,192 21,504 336 56 1,008 56 24/420 8 YES 312 624XC2V3000 3M 64 x 56 14,336 32,256 28,672 448 96 1,728 96 24/420 12 YES 360 720XC2V4000 4M 80 x 72 23,040 51,840 46,080 720 120 2,160 120 24/420 12 YES 456 912XC2V6000 6M 96 x 88 33,792 76,032 67,584 1,056 144 2,592 144 24/420 12 YES 552 1,104XC2V8000 8M 112 x 104 46,592 104,832 93,184 1,456 168 3,024 168 24/420 12 YES 554 1,108

LDT-25, LVPECL-33,LVDS-33, LVDS-25,

LVDSEXT-33, LVDSEXT-25,BLVDS-25, ULVDS-25,

LVTTL, LVCMOS33,LVCMOS25, LVCMOS18,

LVCMOS15, PCI33, PCI66,PCI-X, GTL, GTL+, HSTL I,HSTL II, HSTL III, HSTL IV,SSTL2I, SSTL2II, SSTL3 I,SSTL3 II, AGP, AGP-2X

LDT-25, LVDS-25, LVDSEXT-25,BLVDS-25, ULVDS-25, LVPECL-25,

LVCMOS25, LVCMOS18,LVCMOS15, PCI33, LVTTL,

LVCMOS33, PCI-X, PCI66, GTL,GTL+, HSTL I (1.5V,1.8V),

HSTL II (1.5V,1.8V),HSTL III (1.5V,1.8V),

HSTL IV (1.5V,1.8V), SSTL2I,SSTL2II, SSTL18 I, SSTL18 II

-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5-4 -5 -6 -4 -5

-4 -5

-5 -6 -7 -5 -6-5 -6 -7 -5 -6-5 -6 -7 -5 -6-5 -6 -7 -5 -6-5 -6 -7 -5 -6-5 -6 -7 -5 -6-5 -6 -7 -5 -6-5 -6 -7 -5 -6-5 -6 -7 -5 -6-5 -6 -7 -5 -6

ISP/O

TP

ISP

ISP/

OTP

ISP

.15um Eight Layer Metal Process

.13um Nine Layer Copper Process

0.4M0.6M1.7M2.8M4.1M5.7M7.5M10.5M ✔

15.7M ✔

21.9M ✔

29.1M ✔

Note: 1. System Gates include 20-30% of CLBs used as RAM 2. Logic cell = (1) 4 Input (LUT) Look Up Table + Flip Flop + Carry Logic.3. DCM – Digital Clock Management4. Virtex-II Series EasyPath solution available to provide a no risk, no effort cost reduction path for volume production.

* System gate count not meaningful for Virtex-II Pro devices with immersed special blocks such as PowerPC processors and multi-gigabit transceivers.** The FF1148 and FF1696 packages support higher numbers of user I/O and zero RocketIO multi-gigabit transceivers.Important: Verify all Data with Device Data Sheet (http://www.xilinx.com/partinfo/databook.htm)

1.31M 4 03.01M 4 14.49M 8 18.21M 8 211.36M 8 2 ✔

15.56M 0**or 12 2 ✔

19.02M 0**or 16 2 ✔

25.60M 16 or 20 2 ✔

33.65M 0**or 20 2 ✔

42.78M 0**,20, or 24 4 ✔

R E F E R E N C E

XC2V

40

XC2V

80

XC2V

250

XC2V

500

XC2V

1000

XC2V

1500

XC2V

2000

XC2V

3000

XC2V

4000

XC2V

6000

XC2V

8000

XC2V

P2

XC2V

P4

XC2V

P7

XC2V

P20

XC2V

P30

XC2V

P40

XC2V

P50

XC2V

P70

XC2V

P100

XC2V

P125

Pins Body Size 204 348 396 564 692 804 852 996 1164 1200 88 120 200 264 432 528 624 720 912 1104 1296

Chip Scale Packages — wire-bond chip-scale BGA (0.8 mm ball spacing)

144 12 x 12 mm 88 92 92

BGA Packages (BG) — wire-bond standard BGA (1.27 mm ball spacing)

575 31 x 31 mm 328 392 408

728 35 x 35 mm 516

FGA Packages (FG) — wire-bond fine-pitch BGA (1.0 mm ball spacing)

256 17 x 17 mm 140 140 88 120 172 172 172

456 23 x 23 mm 156 248 248 200 264 324

676 27 x 27 mm 404 416 416 392 456 484

FFA Packages (FF) — flip-chip fine-pitch BGA (1.0 mm ball spacing)

672 27 x 27 mm 204 348 396

896 31 x 31 mm 396 556 556 432 528 624

1152 35 x 35 mm 564 644 692 692 720 824 824 824

1148* 35 x 35 mm 804 812

1517 40 x 40 mm 852 964 912 1104 1108

1704 42.5 x 42.5 mm 996 1040 1040

1696* 42.5 x 42.5 mm 1164 1200

BFA Packages (BF) — flip-chip fine-pitch BGA (1.27 mm ball spacing)

957 40 x 40 mm 624 684 684 684

Virtex-II (1.5V)Virtex-II Pro (1.5V)

Note: Within the same family, all devices in a particular package are pin-out (footprint) compatible.Virtex-II packages FG456 and FG676 are also footprint compatible.Virtex-II packages FF896 and FF1152 are also footprint compatible.* The FF1148 and FF1696 packages support higher number of user I/O and zero RocketIO™ multi-gigabit transceivers.Important: Verify all Data with Device Data Sheet (http://www.xilinx.com/partinfo/databook.htm)

Numbers indicated in the matrix are the maximum number of user I/Os for that package and device combination; I/Os for RocketIO MGTsare not included in this table.

I/O’sPackage

FG256 4 4

FG456 4 4 8

FG676 8 8 8

FF672 4 4 8

FF896 8 8 8

FF1152 8 8 12 16

FF1148 0* 0*

FF1517 16 16

FF1704 20 20 24

FF1696 0* 0*

Note: * FF1148 and FF1696 packages support higher number of user I/O and zero RocketIO multi-gigabit transceivers

Virtex-II Pro Package Configurations with Available RocketIO Transceiver Blocks

XC2V

P2

XC2V

P4

XC2V

P7

XC2V

P20

XC2V

P30

XC2V

P40

XC2V

P50

XC2V

P70

XC2V

P100

XC2V

P125

Xilinx Spartan FPGA Products


CLB Resources BLK RAM CLK Resources I/O Features Speed

Syst

em G

ates

(see

not

e 1)

CLB

Arra

y (R

ow X

Col

)

Num

ber o

f Slic

es

Logi

c Ce

lls (s

ee n

ote

2)

CLB

Flip

-Flo

ps

Max

.Dist

ribut

ed R

AM B

its

# Bl

ock

RAM

Bloc

k RA

M (k

bits

)

# De

dica

ted

Mul

tiplie

rs

DLL

Freq

uenc

y (m

in/m

ax)

# DL

L's

Freq

uenc

y Sy

nthe

sis

Phas

e Sh

ift

Digit

ally C

ontro

lled

Impe

danc

e

Num

ber o

f Diffe

rent

ial I/

O Pa

irs

Max

.I/O

I/O S

tand

ards

Com

mer

cial S

peed

Gra

des

(slo

wes

t to

fast

est)

Indu

stria

l Spe

ed G

rade

s(s

low

est t

o fa

stes

t)

Seria

l PRO

M F

amily

Conf

ig.M

emor

y (B

its)

Spartan-IIE Family — 1.8 VoltXC2S50E 50K 16 x 24 768 1,728 1,536 24K 8 32K NA 25/320 4 YES YES NA 83 182XC2S100E 100K 20 x 30 1,200 2,700 2,400 37K 10 40K NA 25/320 4 YES YES NA 86 202XC2S150E 150K 24 x 36 1,728 3,888 3,456 54K 12 48K NA 25/320 4 YES YES NA 114 265XC2S200E 200K 28 x 42 2,352 5,292 4,704 73K 14 56K NA 25/320 4 YES YES NA 120 289XC2S300E 300K 32 x 48 3,072 6,912 6,144 96K 16 64K NA 25/320 4 YES YES NA 120 329XC2S400E 400K 40 x 60 4,800 10,800 9,600 150K 40 160K NA 25/320 4 YES YES NA 172 410XC2S600E 600K 48 x 72 6,912 15,552 13,824 216K 72 288K NA 25/320 4 YES YES NA 205 514Spartan-II Family — 2.5 VoltXC2S15 15K 8 x 12 192 432 384 6K 4 16K NA 25/200 4 YES YES NA NA 86XC2S30 30K 12 x 18 432 972 864 13.5K 6 24K NA 25/200 4 YES YES NA NA 132XC2S50 50K 16 x 24 768 1,728 1,536 24K 8 32K NA 25/200 4 YES YES NA NA 176XC2S100 100K 20 x 30 1,200 2,700 2,400 37.5K 10 40K NA 25/200 4 YES YES NA NA 196XC2S150 150K 24 x 36 1,728 3,888 3,456 54K 12 48K NA 25/200 4 YES YES NA NA 260XC2S200 200K 28 x 42 2,352 5,292 4,704 73.5K 14 56K NA 25/200 4 YES YES NA NA 284Spartan-XL Family — 3.3 VoltXCS05XL 5K 10 x 10 100 238 200 3.1K NA NA NA NA NA NA NA NA NA 77XCS10XL 10K 14 x 14 196 466 392 6.1K NA NA NA NA NA NA NA NA NA 112XCS20XL 20K 20 x 20 400 950 800 12.5K NA NA NA NA NA NA NA NA NA 160XCS30XL 30K 24 x 24 576 1,368 1,152 18.0K NA NA NA NA NA NA NA NA NA 192XCS40XL 40K 28 x 28 784 1,862 1,568 24.5K NA NA NA NA NA NA NA NA NA 224

LVTTL,LVCMOS2,LVCMOS18, PCI33, PCI66,GTL, GTL+, HSTL I, HSTL III,HSTL IV, SSTL3 I, SSTL3 II,SSTL2 I, SSTL2 II,AGP-2X,CTT, LVDS, BLVDS, LVPECL

LVTTL, LVCMOS2,PCI33 (3.3V & 5V),

PCI66 (3.3V), GTL, GTL+,HSTL I, HSTL III, HSTL IV,SSTL3 I, SSTL3 II, SSTL2 I,

SSTL2 II, AGP-2X, CTT

TTL, LVTTL, CMOS,LVMOS, PCI

-6 -7 -6 -6 -7 -6-6 -7 -6 -6 -7 -6 -6 -7 -6 -6 -7 -6 -6 -7 -6

-5 -6 -5-5 -6 -5-5 -6 -5-5 -6 -5-5 -6 -5-5 -6 -5

-4 -5 -4-4 -5 -4-4 -5 -4-4 -5 -4-4 -5 -4

ISP

ISP

ISP

OTP

OTP

OTP

.18/.15um Six Layer Metal Process

.22/.18um Six Layer Metal Process

0.6M0.9M1.1M1.4M1.9M2.7M4.0M

0.2M0.4M0.6M0.8M1.1M1.4M

0.05M0.09M0.18M0.25M0.33M

Note: 1. System Gates include 20-30% of CLBs used as RAM2. Logic Cell is defined as a 4 input LUT and a register

Automotive products are highlighted:-40C to +125C junction temperature for FPGAs

XC2S

50E

XC2S

100E

XC2S

150E

XC2S

200E

XC2S

300E

XC2S

400E

XC2S

600E

XC2S

15

XC2S

30

XC2S

50

XC2S

100

XC2S

150

XC2S

200

Spartan-IIE (1.8V)

XCS0

5XL

XCS1

0XL

XCS2

0XL

XCS3

0XL

XCS4

0XL

Spartan-XL (3.3V)Spartan-II (2.5V)

PACKAGE OPTIONS AND USER I/O

PRODUCT SELECTION MATRIX

Pins Body Size 182 202 265 289 329 410 514 86 132 176 196 260 284 77 112 160 192 224PLCC Packages84 30 x 30 mm 61 61PQFP Packages (PQ)208 28 x 28 mm 146 146 146 146 146 132 140 140 140 140 160 169 169240 32 x 32 mm 192 192VQFP Packages (VQ)100 14 x 14 mm 60 60 77 77 77 77TQFP Packages (TQ)144 20 x 20 mm 102 102 86 92 92 92 112 113 113Chip Scale Packages — wire-bond chip-scale BGA (0.8 mm ball spacing)144 12 x 12 mm 86 92 112 113280 16 x 16 mm 192 224FGA Packages (FT) — wire-bond fine-pitch thin BGA (1.0 mm ball spacing)256 17 x 17 mm 182 182 182 182 182 182FGA Packages (FG) — wire-bond fine-pitch BGA (1.0 mm ball spacing)256 17 x 17 mm 176 176 176 176456 23 x 23 mm 202 265 289 329 329 329 196 260 284676 27 x 27 mm 410 514BGA Packages256 27 x 27 mm 192 205

I/O’s

R E F E R E N C E

Spartan-3 — 1.2 VoltXC3S50 50K 16 x 12 768 1,728 1,536 12K - - - - - - - YES 56 124XC3S200 200K 24 x 20 1,920 4,320 3,840 30K 12 216K 12 25/325 4 YES YES YES 76 173XC3S400 400K 32 x 28 3,584 8,064 7,168 56K 16 288K 16 25/325 4 YES YES YES 116 264XC3S1000 1000K 48 x 40 7,680 17,280 15,360 120K 24 432K 24 25/325 4 YES YES YES 175 391XC3S1500 1500K 64 x 52 13,312 29,952 26,624 208K 32 576K 32 25/325 4 YES YES YES 221 487XC3S2000 2000K 80 x 64 20,480 46,080 40,960 320K 40 720K 40 25/325 4 YES YES YES 270 565XC3S4000 4000K 96 x 72 27,648 62,208 55,296 432K 96 1,728K 96 25/325 4 YES YES YES 312 712XC3S5000 5000K 104 x 80 33,280 74,480 66,560 520K 104 1,872K 104 25/325 4 YES YES YES 344 784

Single-endedLVTTL,LVCMOS3.3/2.5/1.8/1.5/1.2,PCI 3.3V – 32/64-bit 33MHz,SSTL2 Class I & II, SSTL18 Class I,

HSTL Class I, III,HSTL1.8 Class I, II & III,

GTL, GTL+

DifferentialLVDS2.5, Bus LVDS2.5,

Ultra LVDS2.5, LVDS_ext2.5,RSDS, LDT2.5

-4 -5 -4 -4 -5 -4-4 -5 -4 -4 -5 -4 -4 -5 -4 -4 -5 -4 -4 -5 -4 -4 -5 -4

0.3M1.0M1.7M3.2M5.2M7.7M11.3M13.3M

XCF01SXCF01SXCF02SXCF04SXCF08PXCF08PXCF16PXCF16P

90nm Eight Layer Metal Process

XC3S

50

XC3S

200

XC3S

400

XC3S

1000

XC3S

1500

XC3S

2000

XC3S

4000

XC3S

5000

Pins Body Size 124 173 264 391 487 565 712 784VQFP Packages (VQ) – very thin TQFP (0.5 mm lead spacing)100 16 x 16 mm 63 63TQFP Packages (TQ) – thin QFP (0.5 mm lead spacing)144 22 x 22 mm 97 97 97PQFP Packages (PQ) – wire-bond plastic QFP (0.5 mm lead spacing)208 30.6 x 30.6 mm 124 141 141FGA Packages (FT) – wire-bond thin BGA (1.0 mm ball spacing)256 17 x 17 mm 173 173 173FGA Packages (FG) – wire-bond fine-pitch BGA (1.0 mm ball spacing)456 23 x 23 mm 264 333 333676 27 x 27 mm 391 487 489900 31 x 31 mm 565 633 6331156 35 x 35 mm 712 784

I/O’s

Spartan-3

Important: Verify all Data with Device Data Sheet (http://www.xilinx.com/spartan)

Numbers indicated in the matrix are the maximum number of user I/Os for that package and device combination.


Xilinx CPLD Products

R E F E R E N C E

XC2C

32

XC2C

64

XC2C

128

XC2C

256

XC2C

384

XC2C

512

CoolRunner-II

XCR3

032X

L

XCR3

064X

L

XCR3

128X

L

XCR3

256X

L

XCR3

384X

L

XCR3

512X

L

XC95

36XV

XC95

72XV

XC95

144X

V

XC95

288X

V

XC9500XV

XC95

36XL

XC95

72XL

XC95

144X

L

XC95

288X

L

XC9500XL

*JTAG pins and port enable are not pin compatible in this package for this member of the family.

Important: Verify all Data with Device DataSheet and Product Availability with your localXilinx Rep

CoolRunner XPLA3

PACKAGE OPTIONS AND USER I/O

Body Size

PLCC Packages (PC)

44 16.5 x 16.5 mm 33 33 36 36 34 34 34 34

PQFP Packages (PQ)

208 28 x 28 mm 173 173 173 164 172 180 168 168

VQFP Packages (VQ)

44 12 x 12 mm 33 33 36 36 34 34 34 34

64 12 x 12 mm 36 52

100 16 x 16 mm 64 80 80 68 84

TQFP Packages (TQ)

100 14 x 14 mm 72 81 72 81

144 20 x 20 mm 100 118 118 108 120 118* 117 117 117 117

Chip Scale Packages (CP) — wire-bond chip-scale BGA (0.5 mm ball spacing)

56 6 X 6 mm 33 45 48

132 8 X 8 mm 100 106

Chip Scale Packages (CS) — wire-bond chip-scale BGA (0.8 mm ball spacing)

48 7 x 7mm 36 40 36 38 36 38

144 12 x 12 mm 108 117 117

280 16 x 16 mm 164 192 192

BGA Packages (BG) — wire-bond standard BGA (1.27 mm ball spacing)

256 27 x 27 mm 192

FGA Packages (FT) — wire-bond fine-pitch thin BGA (1.0 mm ball spacing)

256 17 x 17 mm 184 212 212 164 212 212

FBGA Packages (FG) — wire-bond Fineline BGA (1.0 mm ball spacing)

256 17 x 17 mm 192 192

324 23 x 23 mm 240 270 220 260

Automotive products are highlighted:-40C to +125C ambient temperature for CPLDs

PRODUCT SELECTION MATRIX I/O Features Speed Clocking

Syst

em G

ates

Mac

roce

lls

Prod

uct t

erm

s pe

r Fun

ctio

nBl

ock

Inpu

t Vol

tage

Com

patib

le

Outp

ut V

olta

ge C

ompa

tible

Max

.I/O

I/O B

anki

ng

Min.

Pin-to

-Pin

Logic

Dela

y (ns

)

Com

mer

cial S

peed

Gra

des

(fast

est t

o slo

wes

t)

Indu

stria

ll Sp

eed

Gra

des

(fast

est t

o slo

wes

t)

Glo

bal C

lock

s

Prod

uct T

erm

Clo

cks

per

Func

tion

Bloc

k

CoolRunner-II Family — 1.8 Volt

XC2C32 750 32 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 33 1 3.5 -3 -4 -6 -6 3 17

XC2C64 1500 64 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 64 1 4 -4 -5 -7 -7 3 17

XC2C128 3000 128 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 100 2 4.5 -4 -6 -7 -7 3 17

XC2C256 6000 256 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 184 2 5 -5 -6 -7 -7 3 17

XC2C384 9000 384 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 240 4 6 -6 -7 -10 -10 3 17

XC2C512 12000 512 40 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 270 4 6 -6 -7 -10 -10 3 17

CoolRunner XPLA3 Family — 3.3 Volt

XCR3032XL 750 32 48 3.3/5 3.3 36 5 -5 -7 -10 -7 -10 4 16

XCR3064XL 1500 64 48 3.3/5 3.3 68 6 -6 -7 -10 -7 -10 4 16

XCR3128XL 3000 128 48 3.3/5 3.3 108 6 -6 -7 -10 -7 -10 4 16

XCR3256XL 6000 256 48 3.3/5 3.3 164 7.5 -7 -10 -12 -10 -12 4 16

XCR3384XL 9000 384 48 3.3/5 3.3 220 7.5 -7 -10 -12 -10 -12 4 16

XCR3512XL 12000 512 48 3.3/5 3.3 260 7.5 -7 -10 -12 -10 -12 4 16

XC9500XV Family — 2.5 Volt

XC9536XV 800 36 90 2.5/3.3 1.8/2.5/3.3 36 1 5 -5 -7 -7 3 18

XC9572XV 1600 72 90 2.5/3.3 1.8/2.5/3.3 72 1 5 -5 -7 -7 3 18

XC95144XV 3200 144 90 2.5/3.3 1.8/2.5/3.3 117 2 5 -5 -7 -7 3 18

XC95288XV 6400 288 90 2.5/3.3 1.8/2.5/3.3 192 4 6 -6 -7 -10 -7 -10 3 18

XC9500XL Family — 3.3 Volt

XC9536XL 800 36 90 2.5/3.3/5 2.5/3.3 36 5 -5 -7 -10 -7 -10 3 18

XC9572XL 1600 72 90 2.5/3.3/5 2.5/3.3 72 5 -5 -7 -10 -7 -10 3 18

XC95144XL 3200 144 90 2.5/3.3/5 2.5/3.3 117 5 -5 -7 -10 -7 -10 3 18

XC95288XL 6400 288 90 2.5/3.3/5 2.5/3.3 192 6 -6 -7 -10 -7 -10 3 18


XC9500XL CPLD

XC9536XL 10 ns/100 MHz

Part Number Speed

VQ44, VQ64

Package

3.3V

Voltage

36 Macrocells (800 Gates), ISP, JTAG, Bus Hold& I/P Hysteresis

XC9572XL

CoolRunner XPLA3

CoolRunner-II

XCR3032XL

XCR3064XL

XCR3128XL

XCR3256XL 10 ns/100 MHz TQ144, PQ208 3.3V

XCR3384XL 10 ns/100 MHz PQ208 3.3V

XCR3512XL

XC2C32 6 ns/145 MHz VQ44 1.8V 32 Macrocells (800 Gates), 6 I/O Standards, Slew Rate Control, Clock Doubler, Bus Hold, I/P Hysteresis. Ultra low power.

XC2C64 7.5 ns/127 MHz VQ44, VQ100 1.8V 64 Macrocells (1,600 Gates), 6 I/O Standards, Slew Rate Control, Clock Doubler, Bus Hold, I/P Hysteresis. Ultra low power.

10 ns/100 MHz PQ208 3.3V 512 Macrocells (12,800 Gates), Low Power, Slew Rate Control, ISP & JTAG

384 Macrocells (9,600 Gates), Low Power, Slew Rate Control, ISP & JTAG


10 ns/100 MHz VQ44, VQ100

VQ100, TQ144

3.3V

10 ns/100 MHz 3.3V 128 Macrocells (3,200 Gates), Low Power, Slew Rate Control, ISP & JTAG


10 ns/100 MHz VQ44 3.3V 32 Macrocells (800 Gates), Low Power, Slew Rate Control, ISP & JTAG

10 ns/100 MHz VQ64, TQ100 3.3V 72 Macrocells (1,600 Gates), ISP, JTAG, Bus Hold & I/P Hysteresis

Description

XC2C128 7.5 ns/127 MHz VQ44, VQ100 1.8V 128 Macrocells (3,200 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok Divider, CoolClock, DataGate, Bus Hold, I/P Hysteresis. Ultra low power.

XC2C256 7.5 ns/127 MHz VQ100, TQ144 1.8V 256 Macrocells (6,400 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok Divider, CoolClock, DataGate, Bus Hold, I/P Hysteresis. Ultra low power.

XC2C384 10 ns/100 MHz TQ144, PQ208 1.8V 384 Macrocells (9,600 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok Divider, CoolClock, DataGate, Bus Hold, I/P Hysteresis. Ultra low power.

XC2C512 10 ns/100 MHz PQ208 1.8V 512 Macrocells (12,800 Gates), 9 I/O Standards, Slew Rate Control, Clock Doubler, Clcok Divider, CoolClock, DataGate, Bus Hold, I/P Hysteresis. Ultra low power.

Spartan-XL

XCS05XL -4

Part Number Speed Grade

VQ100

Package

3.3V

Voltage

Low cost FPGA with power down pin, 5V tol I/O, 5,000 Gate, 238 logic cells, 100 CLBs.

XCS10XL

XCS20XL -4 TQ144, PQ208 3.3V Low cost FPGA with power down pin, 5V tol I/O, 20,000 Gate, 950 logic cells, 400 CLBs.

XCS30XL -4 TQ144, PQ208 3.3V Low cost FPGA with power down pin, 5V tol I/O, 30,000 Gate, 1,368 logic cells, 576 CLBs.

XCS40XL -4 PQ208, BG256 3.3V Low cost FPGA with power down pin, 5V tol I/O, 40,000 Gate, 1,862 logic cells, 784 CLBs.

-4 VQ100 3.3V Low cost FPGA with power down pin, 5V tol I/O, 10,000 Gate, 466 logic cells, 196 CLBs.

Description

Spartan-II

Spartan-IIE

XC2S50E -6 TQ144, PQ208, FT256

1.8V High volume FPGA, on-chip RAM, 19 I/O standards, 50,000 Gate, 1,728 logic cells, 384 CLBs, 8 block RAM blocks, 4 DLLs.

XC2S15 -5 TQ144 2.5V High volume FPGA, on-chip RAM, 16 I/O standards, 15,000 Gate, 432 logic cells, 96 CLBs, 4 block RAM blocks, 4 DLLS.

XC2S30 -5 TQ144, PQ208 2.5V High volume FPGA, on-chip RAM, 16 I/O standards, 30,000 Gate, 972 logic cells, 216 CLBs, 6 block RAM blocks, 4 DLLS.

XC2S50 -5 TQ144, PQ208, FG256


XC2S100 -5 TQ144, PQ208, FG256


XC2S150 -5 PQ208, FG256 2.5V High volume FPGA, on-chip RAM, 16 I/O standards, 150,000 Gate, 3,888 logic cells, 864 CLBs, 12 block RAM blocks, 4 DLLs.

XC2S200 -5 PQ208, FG456 2.5V High volume FPGA, on-chip RAM, 16 I/O standards, 200,000 Gate, 5,292 logic cells, 1,176 CLBs, 14 block RAM blocks, 4 DLLs.

XC2S100E -6 TQ144, PQ208, FT256


XC2S150E -6 PQ208, FT256 1.8V High volume FPGA, on-chip RAM, 19 I/O standards, 150,000 Gate, 3,888 logic cells, 864 CLBs, 12 block RAM blocks , 4 DLLs.

XC2S200E -6 PQ208, FT256 1.8V High volume FPGA, on-chip RAM, 19 I/O standards, 200,000 Gate, 5,292 logic cells, 1,176 CLBs, 14 block RAM blocks, 4 DLLs.

XC2S300E -6 PQ208, FG456 1.8V High volume FPGA, on-chip RAM, 19 I/O standards, 300,000 Gate, 6,912 logic cells, 1,536 CLBs, 16 block RAM blocks, 4 DLLs.

XC2S400E -6 FT256, FG456, FG676

1.8V High volume FPGA, on-chip RAM,19 I/O standards, 400,000 Gate,10,800 logic cells, 2,400 CLBs, 40 block RAM blocks, 4DLLs.

XC2S600E -6 FG456, FG676 1.8V High volume FPGA, on-chip RAM,19 I/O standards, 600,000 Gate,10,800 logic cells, 3,456 CLBs, 72block RAM blocks, 4DLLs.

Xilinx IQ Solutions

R E F E R E N C E

Xilinx Defense and Aerospace Products


R E F E R E N C E

QPRO

Devi

ce

SMD

Volta

ge

Syst

em G

ates

Logi

c Ce

lls

RAM

bits

CFG

Bits

MUL

Ts

DLLs

Flip

-Flo

ps

Max

I/O

s

Pack

ages

XC3020* 5962-89948 5 1500 256 - 14779 - - 256 64 PG84, CB100

XC3030* None 5 2000 360 - 22176 - - 360 80 PG84

XC3042* 5962-89713 5 3000 480 - 30784 - - 480 96 PG84, PG132, CB100

XC3064* None 5 4500 688 - 46064 - - 688 120 PG132

XC3090* 5962-89823 5 6000 928 - 64160 - - 928 144 PG175, CB164

XC4005* 5962-92252 5 9K 466 6272 151960 - - 616 112 PG156, CB164

XC4010* 5962-92305 5 20K 950 12800 283424 - - 1120 160 PG191, CB196

XC4013* 5962-94730 5 30K 1368 18438 393632 - - 1536 192 PG223, CB228

XQ4005E 5962-97522 5 9K 466 6272 95008 - - 616 112 PG156, CB164

XQ4010E 5962-97523 5 20K 950 12800 178144 - - 1120 160 HQ208, PG191, CB196

XQ4013E 5962-97524 5 30K 1368 18438 247968 - - 1536 192 HQ240, PG223, CB228

XQ4025E 5962-97525 5 45K 2432 32768 422176 - - 2560 256 PG299, CB228

XQ4028EX 5962-98509 5 18K-50K 2432 32768 668184 - - 2560 256 HQ240, BG352, PG299, CB228

XQ4013XL 5962-98513 3.3 10-30K 1368 18K 393632 - - 1536 192 PQ240, BG256, PG223, CB228

XQ4036XL 5962-98510 3.3 22-65K 3078 42K 832528 - - 3168 288 HQ240, BG352, PG411, CB228

XQ4062XL 5962-98511 3.3 40-130K 5472 74K 1433864 - - 5376 384 HQ240, BG432, PG475, CB228

XQ4085XL None 3.3 55-180K 7448 100K 1924992 - - 7185 448 HQ240, BG432, CB228

XQV100 None 2.5 108904 2700 40K 781248 - 4 2400 180 PQ240, BG256, CB228

XQV300 5962-99572 2.5 322970 6912 64K 1751840 - 4 6144 316 PQ240, BG352, BG432, CB228

XQV600 5962-99573 2.5 661111 15552 96K 3608000 - 4 13824 512 HQ240, BG432, CB228

XQV1000 5962-99574 2.5 1124022 27648 128K 6127776 - 4 24576 512 BG560, CG560

XQV600E None 1.8 986K 15552 288K 3961632 - 8 13824 512 BG432, CB228

XQV1000E None 1.8 1569K 27648 384K 6587520 - 8 24576 660 BG560, CG560

XQV2000E None 1.8 2542K 43200 640K 10159648 - 8 38400 804 BG560, FG1156

XQ2V1000 TBD 1.5 1000K 11520 720 4082592 40 8 10240 432 FG456, BG575

XQ2V3000 TBD 1.5 3000K 32256 1728 10494368 96 12 28672 720 BG728

XQ2V6000 TBD 1.5 6000K 76032 2592 21849504 144 12 67584 1104 FF1152

* Not for new designs.

QPRO RT

Devi

ce

Volta

ge

Syst

em G

ates

Logi

c Ce

lls

RAM

bits

CFG

Bits

MUL

Ts

DLLs

Flip

-Flo

ps

Max

I/O

s

Pack

ages

Tota

l Ion

izing

Dose

(TID

) in

KRAD

s

XQR4013XL 3.3 10-30K 1368 18K 393632 - - 1536 192 CB228 60

XQR4036XL 3.3 22-65K 3078 42K 832528 - - 3168 288 CB228 60

XQR4062XL 3.3 40-130K 5472 74K 1433864 - - 5376 384 CB228 60

XQVR300 2.5 322970 6912 64K 1751840 - 4 6144 316 CB228 100

XQVR600 2.5 661111 15552 96K 3608000 - 4 13824 512 CB228 100

XQVR1000 2.5 1124022 27648 128K 6127776 - 4 24576 512 CG560 100

XQR2V1000 1.5 1000K 11520 720 4082592 40 8 10240 432 BG575 150

XQR2V3000 1.5 3000K 32256 1728 10494368 96 12 28672 720 CG717 150

XQR2V6000 1.5 6000K 76032 2592 21849504 144 12 67584 1104 FC1144 150

**Under development.

QPRO CONFIGURATION PROMS

DEVICE NOMENCLATURESXC = Qualified Prior to QML Certification

Devi

ce

SMD

Volta

ge

Syst

em G

ates

Logi

c Ce

lls

RAM

bits

CFG

Bits

MUL

Ts

DLLs

Flip

-Flo

ps

Max

I/O

s

Pack

ages

Tota

l Ion

izing

Dose

(TID

)KR

ADs

XC1736D None 5 - - - 32768 - - - - DD8 -

XC1765D 5962-94717 5 - - - 65536 - - - - DD8 -

XC17128D None 5 - - - 131072 - - - - DD8 -

XC17256D 5962-95617 5 - - - 262144 - - - - DD8 -

XQ1701L 5962-99514 5 - - - 1048576 - - - - SO20, CC44 -

XQ17V16 TBD 3.3 - - - 16777216 - - - - VQ44, CC44 -

XQR1701L - 5 - - 1048576 - - - - SO20, CC44 60

XQR18V04 - 3.3 - - 4194304 - - - - VQ44, CC44 40

XQR17V16** - 3.3 - - 16777216 - - - - VQ44, CC44 TBD

Qualified after QMLCertification

X Q V R

X Q R 2V

Radiation Tolerant

Virtex/Virtex-E

Virtex-II

Radiation Tolerant


VER

Y T

HIN

QU

AD

FLA

T PA

CK

CP5

6

VQ

44

12.0

x12.

0mm

(0.8

mm

)

VQ

64

12.0

x12.

0mm

(0.5

mm

)

VQ

100

16.0

x16.

0mm

(0.5

mm

)

PLA

STI

C Q

UA

D F

LAT

PAC

K

PC44

0.69

x0.6

9in

(0.0

5in

)

PC84

1.19

x1.1

9in

(0.0

5in

)

THIN

QU

AD

FLA

T PA

CK

TQ14

4

22.0

x22.

0mm

(0.5

mm

)

TQ10

0

16.0

x16.

0mm

(0.5

mm

)B

F957

40.0

x40.

0mm

(1.2

7mm

)

CH

IP-S

CA

LE B

GA

6.0x

6.0m

m(0

.5m

m)

CP1

32

8.0x

8.0m

m(0

.5m

m)

CS4

8

7.0x

7.0m

m(0

.8m

m)

CS1

44

12.0

x12.

0mm

(0.8

mm

)16

.0x1

6.0m

m(0

.8m

m)

CS2

80

PLA

STI

C Q

UA

D F

LAT

PAC

K

HQ

/PQ

208

30.6

x30.

6mm

(0.5

mm

)

HQ

/PQ

240

34.6

x34.

6mm

(0.5

mm

)FF

1517

40.0

x40.

0mm

(1.0

mm

)

FF11

52

35.0

x35.

0mm

(1.0

mm

)

FF89

6

31.0

x31.

0mm

(1.0

0mm

)

CA

VIT

Y-U

P B

GA

’SC

AV

ITY-D

OW

N B

GA

’S(w

ith

co

pp

er

Heats

lug

)

BG

560

42.5

x42.

5mm

(1.2

7mm

)

BG

728

35.0

x35.

0mm

(1.2

7mm

)

BG

256

27.0

x27.

0mm

(1.2

7mm

)

BG

575

31.0

x31.

0mm

(1.2

7mm

)

FG11

56

35.0

x35.

0mm

(1.0

mm

)

FG67

6

27.0

x27.

0mm

(1.0

mm

)

FG68

0

40.0

x40.

0mm

(1.0

mm

)

FG90

0

31.0

x31.

0mm

(1.0

mm

)

FG45

6

23.0

x23.

0mm

(1.0

mm

)

FG32

4

23.0

x23.

0mm

(1.0

mm

)17

.0x1

7.0m

m(1

.0m

m)

FT25

6

17.0

x17.

0mm

(1.0

mm

)

FG25

6

FF67

2

27.0

x27.

0mm

(1.0

mm

)

FLIP

-CH

IP B

GA

’S

R E F E R E N C E

Xilinx Configuration Storage Solutions


Xilinx Home Page

http://www.xilinx.com

Xilinx Online Support

http://www.xilinx.com/support/support.htm

Xilinx IP Center

http://www.xilinx.com/ipcenter/index.htm

Xilinx Education Center

http://www.xilinx.com/support/

education-home.htm

Xilinx Tutorial Center

http://www.xilinx.com/support/techsup/

tutorials/index.htm

Xilinx WebPACK

http://www.xilinx.com/sxpresso/webpack.htm

R E F E R E N C E

Dens

ity

PD8

VO8

SO20

PC20

PC44

VQ44

Core

Vol

tage

2.5V

3.3V

In-System Programming (ISP) Configuration PROMs

XC18V512 512Kb Y Y Y 3.3V Y Y

XC18V01 1Mb Y Y Y 3.3V Y Y

XC18V02 2Mb Y Y 3.3V Y Y


One-Time Programmable (OTP) Configuration PROMsXC17V01 1.6Mb Y Y Y 3.3V Y Y





I/OVoltage

PRO

M S

olut

ion

VO20

FS48

VCC

(V)

VCCJ

Platform Flash PROMs

XC3S50 XCF01S Y 3.3 1.8 - 3.3

XC3S200 XCF01S Y 3.3 1.8-3.3

XC3S400 XCF02S Y 3.3 1.8-3.3

XC3S1000 XCF04S Y 3.3 1.8-3.3

XC3S1500 XCF08P Y 1.8 1.5-3.3

XC3S2000 XCF08P Y 1.8 1.5-3.3

SC3S4000 XCF16P Y 1.8 1.5-3.3

XC3S5000 XCF16P Y 1.8 1.5-3.3

XC2S50E XCF01S Y 3.3 1.8-3.3

XC2S100E XCF01S Y 3.3 1.8-3.3

XC2S150E XCF02S Y 3.3 1.8-3.3

XC2S200E XCF02S Y 3.3 1.8-3.3

XC2S300E XCF02S Y 3.3 1.8-3.3

XC2S400E XCF04S Y 3.3 1.8-3.3

XC2S600E XCF04S Y 3.3 1.8-3.3

XC2VP2 XCF02S Y 3.3 1.8-3.3

XC2VP4 XCF04S Y 3.3 1.8-3.3

XC2VP7 XCF08P Y 1.8 1.5-3.3

XC2VP20 XCF16P Y 1.8 1.5-3.3

XC2VP30 XCF16P Y 1.8 1.5-3.3

XC2VP40 XCF16P Y 1.8 1.5-3.3

XC2VP50 XCF32P Y 1.8 1.5-3.3

XC2VP70 XCF32P Y 1.8 1.5-3.3

XC2VP100 XCF32P Y Y 1.8 1.5-3.3

+ XCF01S Y Y & 3.3 & 3.3

XC2VP125 XCF32P Y 1.8 1.5-3.3

+ XCF16P

XC2V40 XCF01S Y 3.3 1.8-3.3

XC2V80 XCF01S Y 3.3 1.8-3.3

XC2V250 XCF02S Y 3.3 1.8-3.3

XC2V500 XCF04S Y 3.3 1.8-3.3

XC2V1000 XCF04S Y 3.3 1.8-3.3

XC21500 XCF08P Y 1.8 1.5-3.3

XC2V2000 XCF08P Y 1.8 1.5-3.3

XC2V3000 XCF16P Y 1.8 1.5-3.3

XC2V4000 XCF16P Y 1.8 1.5-3.3

XC2V6000 XCF32P Y 1.8 1.5-3.3

XC2V8000 XCF32P Y 1.8 1.5-3.3

SystemACE CF up to 8 Gbit 2 25 cm2 No JTAG Unlimited Yes Yes Yes 30 Mbit/sec CompactFlash

SystemACE MPM 16 Mbit 1 12.25 cm2 Yes SelectMAP AMD

32Mbit 152 Mbit/sec Flash Memory

64 Mbit Slave-Serial (up to

8 FPGA chains)

SystemACE SC 16 Mbit 3 Custom Yes SelectMAP Up to 8 No No Yes 152 Mbit/sec AMD

32 Mbit (up to 4 FPGA) Flash memory

64 Mbit Slave-Serial (up to

8 FPGA chains)

Mem

ory

Den

sity

Num

ber

of C

ompo

nent

s

Min

Boa

rd S

pace

Com

pres

sion

FPG

A C

onfig

.Mod

e

Mul

tipl

e D

esig

ns

Soft

war

e St

orag

e

Rem

ovab

le

IRL

Hoo

ds

Max

Con

fig.S

peed

Non

-Vol

atile

Med

ia

FPG

A

PRO

MSo

lutio

n

PD8

VO8

SO20

PC20

PC44

VQ44

Core

Vol

tage

2.5V

3.3V

OTP Configuration PROMs for Spartan-II/IIE

XC2S50E XC17S50A Y Y Y 3.3V Y Y




XC2S300E XC17S300A Y 3.3V Y Y

XC2S15 XC17S15A Y Y Y 3.3V Y Y






I/OVoltage

FPG

A

PRO

MSo

lutio

n

PD8

VO8

SO20

PC20

PC44

VQ44

Core

Vol

tage

3.3V

5.0V

OTP Configuration PROMs for Spartan-XL

XCS05XL XC17S05XL Y Y 3.3V Y Y





I/OVoltage

VCCO

(V)

1.8-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.5-3.3

1.5-3.3

1.5-3.3

1.5-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.5-3.3

1.5-3.3

1.5-3.3

1.5-3.3

1.5-3.3

1.5-3.3

& 1.8-3.3

1.5-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.8-3.3

1.5-3.3

1.5-3.3

1.5-3.3

1.5-3.3

1.5-3.3

1.5-3.3

1.5-3.3

Xilinx Software


R E F E R E N C E

Feature ISE WebPACK ISE BaseX ISE Foundation ISE Alliance

Devices Virtex™Series Virtex-E: V50E – V300E Virtex: V50 – V300 ALL ALLVirtex-II: 2V40 – 2V250 Virtex-E: V50E – V300E

Virtex-II Pro: 2VP2 Virtex-II: 2V40 – 2V250Virtex-II Pro: 2VP2

Spartan™ Series Spartan-II/IIE: Spartan-II/IIE: ALL Spartan-II/IIE: ALL Spartan-II/IIE: ALL ALL (except XC2S400E and XC2S600E)

Spartan-3: 3S50 Spartan-3: 3S50 and 3S200 Spartan-3: ALL Spartan-3: ALLCoolRunner™ XPLA3 / CoolRunner-II ALL ALL ALL ALLXC9500™ Series ALL ALL ALL ALL

Services Educational Services Yes Yes Yes YesDesign Services Sold as an Option Sold as an Option Sold as an Option Sold as an OptionSupport Services Web Only Yes Yes Yes

Design Entry Schematic Editor Yes Yes PC Only NoHDL Editor Yes Yes Yes YesState Diagram Editor Yes Yes PC Only NoCORE Generator System No Yes Yes YesPACE (Pinout and Area Constraint Editor) Yes Yes Yes YesArchitecture Wizards Yes Yes Yes Yes

DCM – Digital Clock ManagementMGT – Multi-Gigabit Transcievers

3rd Party RTL Checker Support Yes Yes Yes YesXilinx System Generator for DSP No Sold as an Option Sold as an Option Sold as an Option

Embedded GNU Embedded Tools No Yes (Available with optional EDK) Yes (Available with optional EDK) Yes (Available with optional EDK)System Design GCC – GNU Compiler

GDB – GNU Software DebuggerWindRiver Xilinx Edition Development Tools No Sold as an Option Sold as an Option Sold as an Option

Diab C/C++ CompilerSingleStep DebuggervisionPROBE II target connection

Synthesis Xilinx Synthesis Technology (XST) Yes Yes Yes NoSynplicity Synplify/Pro Integrated Interface Integrated Interface Integrated Interface (PC Only) Integrated Interface (PC Only)Synplicity Amplify Physical Synthesis Support Yes Yes Yes YesLeonardo Spectrum Integrated Interface Integrated Interface Integrated Interface Integrated InterfaceSynopsys FPGA Compiler II EDIF Interface EDIF Interface EDIF Interface EDIF InterfaceABEL CPLD CPLD CPLD (PC Only) No

Implementation FloorPlanner Yes Yes Yes YesConstraints Editor Yes Yes Yes YesTiming Driven Place & Route Yes Yes Yes YesModular Design Yes Yes Yes YesTiming Improvement Wizard Yes Yes Yes Yes

Programming iMPACT Yes Yes Yes YesSystem ACE Configuration Manager Yes Yes Yes Yes

Board Level IBIS Models Yes Yes Yes YesIntegration STAMP Models Yes Yes Yes Yes

LMG SmartModels Yes Yes Yes YesHSPICE Models* Yes Yes Yes Yes

Verification HDL Bencher™ Yes Yes PC Only NoModelSim® Xilinx Edition (MXE II) ModelSim XE II Starter** ModelSim XE II Starter** ModelSim XE II Starter** ModelSim XE II Starter**Static Timing Analyzer Yes Yes Yes YesChipScope Pro No Sold as an Option Sold as an Option Sold as an OptionFPGA Editor with Probe No Yes Yes YesChipViewer Yes Yes Yes YesXPower (Power Analysis) Yes Yes Yes Yes3rd Party Equivalency Checking Support Yes Yes Yes YesSMARTModels for PPC and Rocket I/O No Yes Yes Yes3rd Party Simulator Support Yes Yes Yes Yes

Platforms PC (MS Windows 2000/MS Windows XP) PC Only (MS Windows 2000/MS Windows XP) PC (MS Windows 2000/MS Windows XP)Sun Solaris, Linux PC (MS Windows 2000/MS Windows XP)Sun Solaris, LinuxIP/CORE For more information on the complete list of Xilinx IP products, visit the Xilinx IP Center at http://www.xilinx.com/ipcenter

* HSPICE Models available at the Xilinx Design Tools Center at www.xilinx.com/ise. ** MXE II supports the simulation of designs up to 1 million system gates and is sold as an option.

For more information, visit the Xilinx Design Tools Center at www.xilinx.com/ise


Xilinx Global Services

support.xilinx.com

• Sign up for personalized email alerts at mysupport.xilinx.com

• Search our knowledge database

• Troubleshoot with Problem Solvers

• Consult with engineers in Forums

Xilinx Productivity Advantage (XPA)Program

The XPA provides customers with everything they need toimprove their designs — Software, Education and SupportServices, IP cores and demo boards — in one package. Asingle purchase order allows their designers to get what theyneed, when they need it, without the worry of orderingeach piece of the solution separately.

Two types of XPAs are available: custom XPA andPrepacked “XPA Seat.” “XPA Seat” is primarily for individuals or small design teams.

http://support.xilinx.com/support/gsd/xpa_program.htm

Xilinx Design Services (XDS)

• XDS provides extensive FPGA hardware andembedded software design experience backed byindustry recognized experts and resources to solveeven the most complex design challenge.

• System Architecture Consulting — Provideengineering services to define system architec-ture and partitioning for design specification.

• Custom Design Solutions — Project designed,verified, and delivered to mutually agreed upondesign specifications.

• IP Core Development, Optimization,Integration, Modification, and Verification —Modify, integrate, and optimize customer intellectual property or third party cores to work with Xilinx technology. Develop customer-required special features to Xilinx IPcores or third party cores. Perform integration,optimization, and verification of IP cores in Xilinx technology.

• Embedded Software — Develop complexembedded software with real-time constraints,using hardware/software co-design techniques.

• Conversions — Convert ASIC designs and otherFPGAs to Xilinx technology and devices.

Titanium Technical Service

• Dedicated application engineer

• Design flow methodology coaching

• Contract based service

• Factory escalation process

• Timing closure expertise

• Service at customer site or Xilinx site

Platinum Technical Service

• Access to Senior Applications Engineers

• Dedicated Toll Free Number*

• Priority Case Resolution

• Ten Education Credits

• Electronic Newsletter

• Formal Escalation Process

• Service Packs and Software Updates

• Application Engineer to Customer Ratio, 2x Gold Level

*Toll free number available in US only, dedicated local numbers available across Europe

R E F E R E N C E

Part Number Product Description Duration Availability

Education Services hours

FPGA13000-5-ILT Fundamentals of FPGA Design 8 Now

FPGA23000-5-ILT Designing for Performance 16 Now

FPGA33000-5-ILT Advanced FPGA Implementation 16 Now

LANG11000-5-ILT Introduction to VHDL 24 Now

LANG21000-5-ILT Advanced VHDL 16 Now

LANG12000-5-ILT Introduction to Verilog 24 Now

PCI8000-4-ILT PCI CORE Basics 8 Now

PCI28000-4-ILT Designing a PCI System 16 Now

ASIC25000-5-ILT Designing for Performance for the ASIC User 24 Now

DSP2000-3-ILT DSP Implementation Techniques for Xilinx FPGAs 24 Now

DSP-10000-5-ILT DSP Design Flow 24 Now

RIO22000-5-ILT Designing with RocketIO MGT 16 Now

PROMO-5003-5-LEL Designing for Performance, Live Online 9 Now

EMBD-21000-5-ILT Embedded Systems Development 16 Now

Platinum Technical Service

SC-PLAT-SVC-10 1 Seat Platinum Technical Service w/10 education credits N/A Now

SC-PLAT-SITE-50 Platinum Technical Service site license up to 50 customers N/A Now

SC-PLAT-SITE-100 Platinum Technical Service site license for 51-100 customers N/A Now

SC-PLAT-SITE-150 Platinum Technical Service site license for 101-150 customers N/A Now

Titanium Technical Service

PS-TEC-SERV Titanium Technical Service (minimum 40 hours) N/A Now

PS-TEC-SERV-JP Titanium Technical Service (minimum 8 hours) Japan N/A Now

Design Services

DC-DES-SERV Design Services Contract N/A Now

Xilinx Productivity Advantage

DS-XPA Custom XPA Packaged Solution N/A Now

DS-XPA-10K Custom XPA for $0 – $10,000 N/A Now

DS-XPA25K Custom XPA for $10,0001 – $25,000 N/A Now

DS-XPA Custom XPA for $25,001 – $100,000 N/A Now

DS-XPA-10K-INT Custom XPA (International) for $0 – $10,000 N/A Now

DS-XPA-25K-INT Custom XPA (International) for $10,0001 – $25,000 N/A Now

DS-XPA-INT Custom XPA (International) for $25,001 – $100,000 N/A Now

DS-ISE-ALI-XPA XPA Seat, ISE Alliance N/A Now

DS-ISE-FND-XPA XPA Seat, ISE Foundation N/A Now

Promotion Packages

PROMO-5004-5-ILT FPGA Essentials 24 Now

DS-SYSGEN-4SL-T DSP Bundle-SYSGen + DSP Flow class 24 Now

DO-EDK-T EDK kit + Embedded Systems Development class 16 Now

Education Services Contacts

North America: 877-XLX-CLAS (877-959-2527)http://support.xilinx.com/support/training/training.htm

Europe: [email protected]

Japan: +81-3-5321-7750 http://support.xilinx.co.jp/support/education-home.htm

Asia Pacific: +852 2424 5200 [email protected] http://support.xilinx.com/support/education-home.htm

Design Services Contacts

North America & Asia:Richard Fodor: 408-626-4256Mike Barone: 512-238-1473

Europe:Alex Hillier: +44-870-7350-516Martina Finnerty: +353-1-4032469

Asia Pacific:David Keefe: +852 2401 5171

[email protected]

XPA Contacts

North America: 800-888-FPGA (3742)fpga.xilinx.com

Europe:Stuart Elston: +44-870-7350-532


Titanium Technical Service Contacts

North America:Telesales: 1-800-888-3742

Europe:Stuart Elston: +44-870-7350-632

Japan:81-3-5321-7730 or [email protected]


Introducing the

SPARTAN™-3Platform FPGAs.

The New Generation of Low Cost Solutions.

The world’s lowest-cost FPGAs

The first devices ever manufactured in 90nm process technology, our new Spartan-3 FPGAs

deliver unbeatable price and performance. Packing a ton of I/Os, with densities ranging from

50K to 5 Million gates, you’ve got the lowest cost per pin and lowest cost per gate in the industry—

and it’s all in the most cost-efficient die size available.

All the density and I/O you need . . . at the price you want

The new Spartan-3 FPGAs allow you to take your design idea from the white

board to the circuit board in a huge range of applications. With cost savings in

manufacturing, easy integration of soft core processors, superior DSP perform-

ance and full I/O support with total connectivity solutions, you get all you

need at the price you want.

The Spartan-3 Platform FPGAs are ready for a new generation of designs. . . are you?

MAKE IT YOUR ASIC


For more information visitwww.xilinx.com/spartan3

® 2003 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx and Spartan are registered trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc.

PN 0010726