1

1XESS Boards

ECE 4514

XESS FPGA Boards

2XESS Boards

ECE 4514

XESS boards

• Two boards:– XSTEND: Dip switches, Bar LEDs, other support

devices– XSA-100: Contains FPGA, SDRAM, parallel port

interface

– XSA board is attached to the XSTEND board

2

3XESS Boards

ECE 4514

XstendBoard

4XESS Boards

ECE 4514

Jumpers

• J17 – Connects CODEC interface to XSA– ON when using CODEC– OFF for all other applications

• J11 – Holds CODEC in RESET state– ON when NOT using CODEC– OFF when using CODEC

• J8 – ON enables the BAR LEDs• J7 – ON enables the LEFT seven-segment (U1)• J4 – ON enables the RIGHT seven-segment (U2)

3

5XESS Boards

ECE 4514

DIP Switches

• Switch Operation– ON – Pulls line directly to GND– OFF – Line is pulled HI through 10K resistor

• Must be in OFF position when not in use– Switches share lines with CODEC control signals– Switches share lines with FLASH memory on

XSA board

6XESS Boards

ECE 4514

XSA Board Layout

DIP Switches

4

7XESS Boards

ECE 4514

8XESS Boards

ECE 4514

5

9XESS Boards

ECE 4514

10XESS Boards

ECE 4514

6

11XESS Boards

ECE 4514

XSA Programmer’s Model

12XESS Boards

ECE 4514

100 MHz Programmable Oscillator

7

13XESS Boards

ECE 4514

Programmable Oscillator

• Programmed for 100 MHz, 50 MHz, 33.3 MHz, 25 MHz, …, downto 48.7 KHz

• Can be configured to pass an external clock through Pin 64 of Prototype Header

• Oscillator output goes directly to CPLD• The CPLD passes the clock to FPGA(P88)• The FPGA may be clocked via P1 or P31 of

the Prototype Header (FPGA pins 18 and 15)

14XESS Boards

ECE 4514

SDRAM Interface

8

15XESS Boards

ECE 4514

SDRAM Interface

• External 8Mx16 SDRAM• Applications in the FPGA can directly

interface with the external SDRAM.• External SDRAM clock (CLK) is directly

controlled by the FPGA through P129• This external clock is re-routed back into

the FPGA through P91

16XESS Boards

ECE 4514

XSA Board SDRAM Cntrl

9

17XESS Boards

ECE 4514FLASH_RAM-CPLD-FPGA Interface

18XESS Boards

ECE 4514

CPLD Configurations• Load data into the FLASH RAM through parallel

PC port• Load a Bitstream into FPGA

– Through parallel PC port using the FPGA prog. pins– From FLASH on power up– Through parallel PC port using JTAG pins of FPGA

• Load data into SDRAM from PC parallel port (must change the configuration of the FPGA)

• Read data from FLASH RAM into PC through parallel port

• Read data from SDRAM into PC through parallel port (must change the configuration of the FPGA)

10

19XESS Boards

ECE 4514

Possible Scenario• Load data into the SDRAM from PC• Program the FPGA to implement your

device by loading a Bitstream from PC into the FPGA– Your model can use the SDRAM data in its

calculation– Your model can store results back into the

SDRAM• Read the results from SDRAM into the PC

to verify the design

20XESS Boards

ECE 4514

FPGA Options

• Enable the FLASH RAM by driving P41 low– Can read data from FLASH– Can write data into the FLASH

• Disable the FLASH RAM by driving P41 high– Can read the DIP switches– Can display results in the seven-segment LED

11

21XESS Boards

ECE 4514

Seven Segment LED

• Active-high inputs – Segments glow when logic-high is applied

• Used by either CPLD or FPGA• LED shares the same 8 pins with the

FLASH RAM data bus.

22XESS Boards

ECE 4514

Four DIP Switches• Accessible by either the CPLD or the FPGA• When closed (ON), each switch pulls the connected pin

to GND• When open (OFF), each pin is pulled high through a pull-

up resistor• When not in use, all switches must be kept in the OFF

position– For CPLD to program the FPGA or FLASH– For FPGA to read or write the FLASH

• Share pins with uppermost 4 bits of FLASH address bus– Allows selection of multiple Bitstreams on power up

12

23XESS Boards

ECE 4514

PS/2 Port and Push-button

24XESS Boards

ECE 4514

Push-Button

• Drives line to GND when pressed• Line is pulled high through pull-up resistor

when button is not pressed.• Shares same line with the PS2 data port

13

25XESS Boards

ECE 4514

VGA Monitor Interface

26XESS Boards

ECE 4514

Parallel Port Interface

14

27XESS Boards

ECE 4514

Summary

• Nickel tour of the XESS boards

• Next time: More synthesis examples– Reading: Ch. 10.7, 10.8 of text– Ch. 4 of Xilinx Synthesis and Simulation

Design Guide:http://toolbox.xilinx.com/docsan/xilinx5/data/docs/sim/sim0002_2.html

– You may find it useful to skim Ch. 3 too.