xilinx embedded processing solutions

Xilinx Embedded Processing SolutionsEmbedded Systems and Applications Symposium Istanbul November 2008

Embedded Systems and Applications Symposium Istanbul Nov. 2008

Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsXilinx Serves a Wide Range of MarketsInfrastructureWirelessCommunicationsInfotainmentInstrumentationAutomotiveCryptoSpaceAerospace and DefenseDisplaysHandheldsConsumerSurveillanceTest and MeasurementIndustrial Scientific and Medical


Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsDigital Convergence Drives DemandIn-The-Hand (CoolRunner II)Cost and size are premiumPower is keyShortest time-in-marketThe Core Infrastructure (Virtex)Performance & capability are premiumPower & cost constrainedLonger time-in-marketVoiceDataVideoThe Expanding Edge (Spartan)Cost and flexibility are keyModerate PerformanceShorter time-in-market


Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsWhat Do Embedded Customers Need ?

Customer are saying that theySolution Requirement Want to minimize inventory of off-the-shelf (OTS) parts or inventory of different OTS parts for each projectInventory one type of silicon part (e.g. FPGA) that can be used across many projects Want processor/sub-system thats a fit to the target applicationA processor with a custom mix of standard peripherals or mix of custom peripheralsWant a solution that will not become obsoleteMaintain same processor code for software re-use Want to spend less time creating and debugging custom IP blocksA wide range of pre-verified intellectual property with complete support infrastructure Want to use sw resources across different projectsCommon software development tools


Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsXilinx Offers a Range of FPGA Embedded Processor Solutions

From space efficient to high performance processorsFlexible IntegrationVariable resources requiredScalable Cost Points

PerformanceFeatures32-bit General Purpose Architecture Soft Core with AccelerationHighest Performance 32-bit General Purpose Architecture With AccelerationExtensive offering of common peripherals and IPOnly Dual PowerPC core architecturePowerPCMicroBlaze


Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsFlexible Embedded Use ModelsHighest Integration, Extensive Peripherals, RTOS & Bus StructuresNetworking & WirelessHigh PerformanceMedium Cost, Some Peripherals, Possible RTOS & Bus StructuresControl & InstrumentationModerate PerformanceLowest Cost, No Peripherals, No RTOS & No Bus StructuresVast range of applications (Programmable State Machine)Low/High Performance123State MachineMicrocontrollerCustom EmbeddedRange of Use ModelsPowerPCMicroBlazeMicroBlazePowerPCMicroBlaze


PowerPC-based Embedded Design Full system customization to meet performance, functionality, and cost goalsArbiterProcessor Local BusPLBI CacheD Cache

MicroBlaze-based Embedded DesignFlexible Soft IPOff-ChipMemoryFLASH/SRAMBRAMLocal Memory BusD-CacheBRAMI-CacheBRAMConfigurableSizes

Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsAcceleration Beyond the CoreWhen clock frequency limits performance, Fabric Acceleration to the rescueApplication-specific hardware accelerationEnables dramatic improvements in performanceSubstantially reduces cost and powerPowerPCAPU InterfaceMicroBlazeFSL (Fast Simplex Links) InterfacePowerPC


Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsA Higher Performance Bus Infrastructure

One interface for PPC and MicroBlazeOne interface with common IPsFast and efficient


Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsWhy MicroBlaze v7.00 with MMU?Strong Customer Demand for Embedded Linux solution for FPGA-based Processors~ 30 % of Xilinx Embedded Opportunities use Linux or uClinux

MicroBlaze v7 with MMU enables Full Embedded Linux 2.6 solutionMore Secure, Robust Software Development because of Memory ProtectionEasier Software development because of Virtual Memory and Runtime Loadable applicationsEasy to port large number of Linux applications, drivers and libraries

LynuxWorks BlueCat Linux (MicroBlaze Edition) to support MMUSupport from other partners and GPL patch to follow soon after


Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsProject tabSystem Assembly ViewBus interfaceMessages WindowXilinx Platform StudioEmbedded IDE and Tool SuiteProject Information Area


XPS FunctionsXPSHW/SWSimulationHW/SWDebugHardware DesignSoftwareDesignProject managementMHS or MSS fileXMP fileSoftware application managementPlatform managementTool flow settingsSoftware platform settingsTool invocationDebug and simulation

Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsPlatform StudioIntelligent Tools Streamline Design Embedded System Development Intuitive design environment for Xilinx Platform FPGAs One environment for both MicroBlaze and PowerPC HW and SW platform definition and generation Extensive IP library Comprehensive design verification and debug Integrated verification and debug Platform Debug SW simulation models Automated paths to development kits


Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsUser friendly core configuration dialogsPlatform Studio Customize Processor, IP & Peripherals


Project Creation Using BSB

Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsRTOS, Board Support PackageEmbedded Development KitIntegrated HW/SW/FPGA FlowsInstantiate the System Netlist and Implement the FPGAInclude the BSPand Compile theSoftware Image123Xilinx Platform Studio SDKXilinx Platform Studio


Embedded Systems and Applications Symposium Istanbul Nov. 2008 Xilinx Embedded Processing SolutionsCross Trigger HW and SW Debuggers to Find and Fix Bugs Faster!Platform Debug in XPS SDKFind and Fix Bugs Faster


*****Time on the foil: 2 min..Total elapsed at the end of foil: 10 min*Time on the foil: 2 min..Total elapsed at the end of foil: 12 minSlide StartFirst ClickBuild DSOCM and ISOCMThe PowerPC 405 core is provided with non-bused, non-cacheable, low-latency data and instruction memory interfaces, known as the 32-bit data-side On-Chip Memory and the 64-bit instruction-side On-Chip Memory. Typical uses of data-side OCM include scratch-pad memory and using the dual-port feature of block RAM to enable a bidirectional data transfer between the processor and the FPGA. The typical use for instruction-side OCM is storage of interrupt service routines. One of the primary advantages of OCM is that it guarantees a fixed latency of execution because there is no bus arbitration required for the OCM interface. Also, it reduces cache pollution and thrashing, because the cache remains available for caching code from other memory resources.Build PLBThe processor local bus (PLB) interface provides a 32-bit address and three 64-bit data buses attached to the instruction-cache and data-cache units. Two of the 64-bit buses are attached to the data-cache unit, one supporting read operations and the other supporting write operations. The third 64-bit bus is attached to the instruction-cache unit to support instruction fetching. The prime goal of the PLB is to provide a high-bandwidth, low-latency connection between bus agents that are the main producers and consumers of the bus transaction traffic. This is the bus to which you connect your higher speed peripherals (e.g., G-Ethernet Mac) and memory.Build OPBThe On-chip Peripheral Bus (OPB) provides a fully synchronous 32-bit address and 32-bit data bus. The prime goal of the OPB is to provide a flexible connection path to peripherals and memory, while providing minimal performance impact to the PLB bus. Put your slower peripherals on this bus, such as UARTs, GPIO, 10/100 E-Net MAC, etc.Build DCRThe DCR (Device Control Register) bus is a 32-bit bus for removing device configuration slave loads, memory address resource use, and configuration transaction traffic from the main system buses. Most traffic on the DCR bus occurs during the system initialization period; however, some elements, such as the DMA controller and the interrupt controller cores, use the DCR bus to access normal functional registers used during operation.Build MB Because MicroBlaze is a soft-logic processor, it runs on all current FPGA families. Build Caches With MicroBlaze, you can select whether to use an instruction cache and a data cache and their sizes. FPGA BRAM is used for these caches.Build LMB MicroBlaze has a 32-bit Local Memory Bus (LMB) that is used for low-latency access to on-chip BRAM. The LMB provides single-cycle access to on-chip dual-port block RAM and is split into instruction-side LMB and data-side LMB. Build off-chip memory EDK includes memory controllers for off-chip flash, SDRAM, or DDR SDRAMBuild LocalLink MicroBlaze contains zero to eight input LocalLink interfaces and zero to eight output LocalLink interfaces. The LocalLink channels are dedicated uni-directional point-to-point data-streaming interfaces. The LocalLink interfaces on MicroBlaze are 32 bits wide. Further, the same LocalLink channels can be used to transmit or receive either control or data words. A separate bit indicates whether the transmitted (received) word is control or data information. There are two two cycle-assembly instructions: get and put. Wrapping this into custom C functions with appropriate custom hardware also provides an optimal method by which you can implement custom instructions for the processor.Build OPB MicroBlaze also shares the On-chip Peripheral Bus (OPB) with the PowerPC. The same peripherals that work on the OPB with the PowerPC can also be used with MicroBlaze.Build PPC Finally, because the OPB is shared, one can hang a MicroBlaze as an OPB peripheral connected to a PowerPC system on Virtex-II Pro.*Time on the foil: 1 min..Total elapsed at the end of foil: 20 min***XPS supports the creation of the MHS and MSS files required for embedded tools flow. XPS also aids you in creating an MHS through a dialog-based editor and bus connection matrix, or through a graphical block diagram editor (referred to as the Platform Block Diagram editor). XPS supports customization of software libraries, drivers, interrupt handlers, and compilation of user programs. Source management of C source files and header files for your applications is also provided by XPS. You can also choose the simulation mode for the complete system. You can begin a project by importing an existing MHS file or by starting with an empty MHS file and then adding cores to it. XPS performs process management and dependency checking between the hardware, software, and simulation tool flows by calling the tools in the correct order, using the makefile mechanism.**When invoked, the BSB presents a Create New Project Using Base System Builder Wizard GUI. You will identify the location and project file name. By default, the project file name is system.xmp

Next, you select a board vendor, a name, and a revision of the board. Currently, there are several boards supported. You can add other boards specifications, so they can be displayed as an option.

If the board you want to use is unavailable as an option, you can use BSB to select a board from the database. The database may have a board that resembles the board that you want to use. Once the board is configured to the closest functionality, the designer can then go to the MHS file and either add more IPs or remove devices that are not useful to the current design.

Alternatively, you can choose to load a previously generated BSB settings file from an existing XPS project. A BSB settings file is a file that is created by the Base System Builder upon exit and records all GUI selections made by you during that BSB session. You may load this setting file in any subsequent BSB sessions and the previously recorded selections will be automatically loaded into the GUI, including the board selection. Once this file is loaded, you can still make changes in the current GUI. A new BSB settings file is always created by default upon exit of the BSB wizard, reflecting the final selections of the current session. This feature may be useful to users who want to create several projects with similar designs.

Currently, the Base System Builder supports two processors: Microblaze, a configurable soft processor implemented in FPGA logic, and the PowerPC 405 processor, a hardware device available only in some Xilinx FPGA architectures. If the PowerPC is unavailable in the FPGA device on your development board, this selection will be disabled in the GUI. A brief description of the currently selected processor is displayed on this page, along with an illustration of what a typical system using this processor might look like.

Based on the processor selected, you can configure certain system and processor-specific settings. System settings include processor and bus clock frequencies. Permitted values may be restricted by the clock resources available on the target development board or the on-chip resources available in the FPGA device. Processor-specific settings include debug interfaces, cache options, and configuration of any on-chip memory that communicates over a processor-specific bus.The Base System Builder will determine what external memory and peripheral devices are available on your development board. For each device found, you can indicate whether you want to use that device by clicking the checkbox next to the device name. If a device interface is enabled, you must select from a list of IP cores that can be used to control that device. BSB will instantiate the selected core in the system, connect it to the appropriate bus, and automatically set any parameters that are dictated by the on-board device that that core is controlling. For ease of use, most core parameter values cannot be explicitly set in the BSB GUI. The BSB Wizard is designed to select default parameter values, which will create a functional base system on a specific development board. If required, you can manually change the parameter values in the generated MHS file.

For each device interface enabled, BSB will create the necessary top-level system ports and assign to them the correct FPGA pin locations in a generated UCF file. Depending on the number of devices on the board, the IO Devices Selection panel may span across several wizard pages. The Back button can be used to view or edit previous selections at any time while the wizard is active.

If you are unsure about which IP core to use, you can click the Data Sheet button on the right to view the data sheet of the currently selected core.

Internal peripherals are IP cores that do not communicate directly with any devices outside of the FPGA. Examples of such peripherals are on-chip memory (BRAM) controllers and timers. You can add internal peripherals by clicking the Add Peripheral button at the top of this page and selecting from a list of internal peripherals. Any selections added by default, or by you, can be removed by clicking the Remove button next to that device. Depending on the number of internal peripheral devices you added, additional wizard pages may be created to display the current list. The Back button can be used to remove or edit previous selections. The Base System Builder will instantiate all internal peripherals that are added to the system and connect them to the appropriate bus. It will NOT generate any top-level system ports for internal peripherals.In summary, the novice EDK user can use this tool to quickly generate a hardware system that is correct by construction for the targeted board. However, the advanced EDK user can use this tool to quickly generate a starter system, and then use other XPS features to further enhance the generated system.Here are some of the limitations of BSB: BSB does not support multi-processor systems BSB does not allow users to specify or modify the address map BSB does not check for specific hardware resources on the target FPGA device. The user must consult the data sheet for the FPGA they are using to ensure that it contains enough logic elements and other resources required by the system they are creating. Systems generated by BSB are not guaranteed to meet timing.

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xilinx embedded processing solutions

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