yield, v a riability & reliability in the nanoera:
DESCRIPTION
Yield, V a riability & Reliability in the Nanoera:. Will existing approaches survive?. Debbora Ahlgren VP Sales & Marketing OptimalTest 26-May-2009. MPU to Multi-Core SoC Trend. Homogeneous Array of Cores Fixed Function Units Global Coherency Hardware. - PowerPoint PPT PresentationTRANSCRIPT
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P# 1OptimalTest at ETS 2009
Yield, Variability & Reliabilityin the Nanoera:Will existing approaches survive?
Debbora AhlgrenVP Sales & MarketingOptimalTest26-May-2009
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P# 2OptimalTest at ETS 2009
Cache
Big Core
CacheCache
Big CoreBig Core
1
2
3
4
Power
11
22
33
44
Power
2
1
Performance
22
11
PerformanceCache
SmallCore 1 1
Power = ¼Performance = 1/2
Cache
SmallCore
CacheCache
SmallCoreSmallCore 11 11
Power = ¼Performance = 1/2
Homogeneous Array of CoresFixed Function UnitsGlobal Coherency Hardware
1
2
3
4
Power
11
22
33
44
Power
Cache
C1 C2
C3 C4
Cache
C1 C2
C3 C4
Performance
1
2
3
4
11
22
33
44
Multi-Core is more power-efficientPower ~ AreaSingle-Thread Performance ~ Area *.5
Source: Intel, www.intel.com
MPU to Multi-Core SoC Trend
Scalable Fabric
R econfigurable C ache
High Bandw idth M em ory
Pow er D elivery & M anagem ent
C ore
C ore
C ore
C ore
Core
Core
Core
Core C ore C ore
Core
Core
C ore
C ore
Core
Core
Core
C ore
C ore
C ore
C ore
Core
Core
Core
Core
C ore
C ore
C ore
C ore
Core
Core
Core
Core C ore C oreC ore C oreC ore C ore
Core
Core
C ore
C ore
Core
Core
C ore
C ore
Core
Core
C ore
C ore
Core
Core
Core
Core
Core
Core
Fixed Function U nits
Scalable Fabric
R econfigurable C ache
High Bandw idth M em ory
Pow er D elivery & M anagem ent
Scalable FabricReconfigurable Cache
High Bandwidth Memory
Power Delivery & Management
C ore
C ore
C ore
C ore
Core
Core
Core
Core C ore C ore
Core
Core
C ore
C ore
Core
Core
Core
C ore
C ore
C ore
C ore
Core
Core
Core
Core C ore C oreC ore C ore
Core
Core
C ore
C ore
Core
Core
C ore
C ore
Core
Core
Core
Core
Core
Core
CoreCore
Core
CoreCore
Core
Core
CoreCore
CoreCore
Core
Core
Core
Fixed Function Units
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P# 3OptimalTest at ETS 2009
“More than Moore … and More for Less”
More than Moore: Application-Driven Process Diversification
Analog/RF Passives HV Power BiochipsSensorsActuators
Moo
re’s
Law
: Sc
alin
g
CPU
Mem
ory
Logi
c
90nm
65nm
45nm
32nm
22nm
130nm
.
.
.
Digital DataProcessing & Storage
Interfacing &Interacting withEnvironment
Source: ITRS, Intel
Combination Higher Value Systems
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P# 4OptimalTest at ETS 2009
Qualcomm vs. Intel
Source: Core Logic 2008
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P# 5OptimalTest at ETS 2009
3 Imperatives For Mobile Internet
Source: XOHM
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P# 6OptimalTest at ETS 2009
Business Model Transitions
90nm (2003) 65nm (2006) 45nm (2008) 32nm (2010) 22nm (2012)
Process Node (Year)
TI
WindowOf
Opportunity
With the move to 300mm-diameter wafers, the price tag for anadvanced production fab has becomeout of reach for all but the largest IDMs…*
Source: Gartner, 2008
Source: Gartner, 2008
Window ofOpportunity
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P# 7OptimalTest at ETS 2009
Integrating the DistributedManufacturing Model
Foundry Services
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P# 8OptimalTest at ETS 2009
Thank You!
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P# 9OptimalTest at ETS 2009
Integrating the DistributedManufacturing Model
End-UseCustomer
Channel
ServiceProviders
S/W & Content
Providers
SystemOEMs
Sub-SystemOEMs
ODMs
PackagingServices
Test Houses