- create simulink edge detector (1)

5/21/2018 - Create Simulink Edge Detector (1)

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Developing Video Applications on Spartan-

3A DSP FPGAs

Video Starter Kit Tutorial Lab 3

Create a Simulink Edge Detector

Video Starter Kit Lab www.xilinx.com 1April 15, 2008
http://www.xilinx.com/http://www.xilinx.com/


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Build Video Application

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VSK Tutorial Lab D Overview

In this part of the tutorial you will learn how a high-level Simulink executable specification can be used withmodel-based design techniques to create an FPG hardware design! series of design will be created that

demonstrate how a frame based Simulink design is seriali"ed and turned into a streaming design suitable forimplementation in an FPG!

#he ob$ective of this lab is to provide an introduction to the %ilinx Simulink to FPG design methodology! For

more detailed training on System and the %ilinx &SP 'lockset please visit the %ilinx e-learning web site and

check out the free System Generator e-learning training class at(

http())www!xilinx!com)support)training)free-courses!htm

Objectives Introduce users to the model based design flow for video applications targeting %ilinx FPGs

Show how frame based executable specifications can be used for serial streaming hardware designs Introduce users to %ilinx System Generator for &SP

Developoing Video Application on !ilinx "#$A #age & o% 1& April 2&rd, 2008
http://www.xilinx.com/support/training/free-courses.htmhttp://www.xilinx.com/support/training/free-courses.htm


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Part 1: Create a Simulink Simplified Executable Specification

Procedure

*! +opy the file ,edge_detection_of_gamma_image.mdl from the .ab/ folder into the .ab0 folder and

rename this file ,edge_detect_hw_arch_def.mdl!

/! .aunch Simulink and set the working directory to the .ab0 folder and open the ,edge_detect_hw_arch.mdlfile! 1e-simulate the design to make sure it still functions correctly!

Note:In this part of the lab e need to con!ert the image frame of data into a serial pi"el stream that enters

the hardare and then take the serial stream output from the hardare and build back up a frame of data that

can be used b# the abstract Simulink Imaging and Video $lockset

0! dd the following blocks to the Simulink diagram

- Signal Processing 'lockset)2ath Functions)2atrices and .inear lgebra)2atrix 3perations)#ranspose

- Signal Processing 'lockset)Signal 2anagement)Signal ttributes)+onvert /& to *&

- Signal Processing 'lockset)Signal 2anagement)Signal ttributes)Frame +onversion

- Signal Processing 'lockset)Signal 2anagement)'uffers)4nbuffer

5! 3nce added connect after the ,+olor Space +onverter subsystem as shown below(

6ext we will convert the serial data stream back to a frame! #hen we can verify the logic is workingcorrectly!

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7! dd the following blocks to the Simulink diagram

- Signal Processing 'lockset)2ath Functions)2atrices and .inear lgebra)2atrix 3perations)#ranspose

- Signal Processing 'lockset)Signal 2anagement)Signal ttributes)+onvert *& to /&

- Signal Processing 'lockset)2ath Functions)2atrices and .inear lgebra)2atrix 3perations)Sub 2atrix

- Signal Processing 'lockset)Signal 2anagement)'uffers)'uffer

-

Simulink)Signal ttributes)1ate #ransition- Simulink)+ommonly 4sed 'locks)&ata #ype +onversion

- Simulink)8ideo and Image 'lockset)8ideo 8iewer 9 :rong directory and block

nd connect the blocks as shown below!

;! Push the fourra!es to serial bloc"sinto a subsystem and rename the subsystem ,Frame to Serial! #hen

push the four serial to ra!eblocks into a subsystem called ,Serial to Frame! gain this will help keep the

diagram manageable!

:e now need to setup some parameters on the second subsystem to specify the image si"e! It makes sense toset these parameters as variables in the model properties ,call backs because they will be used in several

places!



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=! >xecute the pulldown menu ,File -? 2odel Properties and set the following 0 variables in the ,InitFcn field

of the model callbacks! #hese variables will be set to the workspace and we can reference them in the

properties fields of the Simulink blocks! 3ur frame si"e is /5@ rows by 0;@ columns executes at *7 frames

per second! 3nce done 3A the form!

B! Push down into the second subsystem that re-creates the image and double click on the ,1ate #ransition

block and set the ,3utput Port Sample #ime to *)CrowDcolDfpsE!

Note:Inclusion of the %&ate Transition' block is technicall# not necessar# for this e"ercise as the output

sample times ill be correctl# calculated b# the ( remaining blocks) *oe!er this block is needed later for a

lab that in!ol!es hardare co+simulation) It doesn,t hurt to put this in no and then e ha!e a serial+to+frame con!ersion subs#stem that ill support all our future de!elopment efforts)

*@! &ouble click on the ,buffer block and set the following parameter! #he buffer block needs to know how big

a frame is! 3nce done 3A for form!

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**! &ouble-click on the +onvert from *& to /& block and set the following parameters! Simulink needs to know

the si"e of the matrix you wish to create! 3nce done ,3A the form!

*/! 3nce done simulate the design 9 you should see a black and white version of image because we only have the

red video stream connected! :e have demonstrated that we have successfully converted the image into a

streaming format then converted the streaming image back into the original frame!

:e are now ready to begin architecting a Sobel >dge &etector on streaming data

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Part 3: Define a hardare !rchitecture usin" Simulink

In this part of the exercise we are going to create a streaming model of our color space converter and edge

detector that represents the hardware architecture we wish to use!

#he , output of an 1G' to H+r+b color space converter can be implemented using the following equation(

@!/BB1 J @!7=


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/! &ouble click on the >mbedded 2#.' function and modify the 2#.' function as shown below( #he

embedded 2#.' function block provides a simple way to implement the color space converter that we

need for this design!

0! +onnect the blocks as shown below(

5! &ouble-click on the Integer &elay block and set the delay ,col! 1emember we set this as a 2odel

Properties +allback InitFcn variable! :e will use this simple delay to model a line buffer7! &ouble-click on each of the 0 &igital Filters and set the coefficients to the corresponding values shown in the

block diagram at the beginning of Part 0!

;! Set the constant values to ,/77 and ,@

=! Set the ,+onvert block to output ,double datatypes! #his Simulink digital filter requires a double as input!

B! 3nce done push all the logic for this edge detector into a subsystem 9 this will help keep the top-leveldiagram manageable

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#he >dge &etector subsystem should be connected at the top level as shown below!

*@! Set the simulation period to ,*)fps or ,*)*7! #he video source executes at *7 ,frames per second and for

each Simulink simulation cycle will process *7 frames of data! For hardware development purposes we canlimit this to one frame for now! Since we set the ,fps variable in the callbacks we can reference it here!

**! 3nce complete Simulate the design 9 ou will notice some slight differences between the 8ideo and Imaging'lockset Sobel >dge &etector and the hardware accurate model we created from Simulink 9 this is primarily

due the specification of a lower threshold value! It is set for the lighting in the building rather then the

outdoor lighting of the video! #he basic results should look acceptable! If you wish you can ad$ust the

threshold value specified in the switch block on the Simulink edge detector to get a more exact image!



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Part ': Define a hardare !rchitecture usin" S%stem (enerator

In this part of the exercise we are going to design the exact same >dge &etector using System Generator and the

%ilinx &SP 'lockset! #his should be a straightforward process as System Generator has blocks that correspond to

the ones used in the Simulink model

Procedure*! dd the following blocks to the &iagram

#lock $ibrar% &t%

System Generator %ilinx 'lockset)Index *

Gateway In %ilinx 'lockset)Index *

Gateway 3ut %ilinx 'lockset)Index *

FI1 +ompiler 5!@ %ilinx 'lockset)Index 0

ddSub %ilinx 'lockset)Index 7

+onstant %ilinx 'lockset)Index 0

1elational %ilinx 'lockset)Index *

2ux %ilinx 'lockset)Index *

&elay %ilinx 'lockset)Index 0

+mult %ilinx 'lockset)Index 0

+onvert %ilinx'lockset)Index *

/! 3pen the library called ,lab3_lib.mdl and add two of the 'S blocks! #he 'S block doesnHt exist in the

%ilinx 'lockset! n 'S block has been saved to a library to save time! #his 'S block is actually providedin one of the other 8SA reference designs 9 it is in the ,&8IKPassK#hroughK&emo! If you wish you can get

it from there as well!

0! First we will create the color space converter :ire up the design as shown in the diagram below!

5! &ouble-click on the ,+onvert block and set the output datatype to 4nsigned L= @M

7! Set the constant values of the +mult blocks to !/BB for the 1 inputN !7=< for the ,G input and !**5 for the ,'

input! lso set the latency equal to *! ou donHt need to modify the fixed point values but you may if you

wish 9 the default setting is provides more bits than are necessary! #he Spartan-0 &SP supports arithmeticoperations up to *= bits with a hard &SP5= slice!



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;! 3nce done with the +S+ 9 push the logic into a subsystem Ccntrl Og?E and connect the edge detector as

shown below

into the block to improve performance!

=! &ouble-click on the ,Gateway In blocks and set the following parameters(

Note:S#stem -enerator re.uires that the actual sample rate be specified on the -atea# In and S#stem

-enerator blocks) In this model a frame of data is being input to the s#stem ith a sample rate of /0fps)

$ecause this %1rame' is decomposed into a !ector of data that gets passed into S#stem -enerator than thes#stem generator design must run at a much higher rate it is %ro2col' faster to be e"act) This is

accomplished b# setting the %Sample eriod' field 4 /05ro2col2fps6) This is an important concept to

understand hen using S#stem -enerator ith the Video and Imaging $lockset



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B! Set the +oefficients on each of the FI1 +ompiler 5!@ blocks to the same values as the Simulink &igital Filter

blocks! #here 0 different coefficients! 'elow is an example of one of them!!

*@! 3n the FI1 +ompiler Implementation #ab select the ,#ransposeK2ultiplyKcculate architecture!

**! Set the constant blocks to the values of ,@N ,/77 and ,B@

*/! Set the System Generator 'lock Simulink system period to *)CrowDcolDfpsE as shown below(

*0! 3nce the design is wired together and the block parameters are set push the System Generator blocks into a

subsystem as you did in the previous lab! our diagram should look something like this(

*5! 3nce done Simulate the design! If you get an error about ,continues states double check all the sample ratesettings! #his means that two sample rates have come together somewhere in the Simulink diagram where

they are not supposed to! ou should see results that are similar as before!

End of $ab 3

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- create simulink edge detector (1)

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