全新架構的全數位式無類比鎖相倍頻電路全新架構的全數位式無類比鎖相倍頻電路Create DLL circuit and Multiple frequency Create DLL circuit and Multiple frequency with VHDL or VERILOG in CPLD,FPGA or with VHDL or VERILOG in CPLD,FPGA or

ASICASIC

授課教授 授課教授 : : 陳永耀 博士 陳永耀 博士 學生 學生 : : 藍浩濤 藍浩濤 P90921001P90921001

電機所控制組 電機所控制組

OUTLINEOUTLINE

AbstractAbstract Purposes of DLLPurposes of DLL DLL Definition and PrincipleDLL Definition and Principle Circuit Design with VHDL in CPLD and Circuit Design with VHDL in CPLD and

FPGA FlowchartFPGA Flowchart Simulation Wave for Lattice CPLDSimulation Wave for Lattice CPLD Experimental Results on OscilloscopeExperimental Results on Oscilloscope ConclusionsConclusions

AbstractAbstract

DLL usually implements with logic and DLL usually implements with logic and analog circuit in ASIC design.analog circuit in ASIC design.

CPLD and FPGA are logic devices,and CPLD and FPGA are logic devices,and must design DLL or PLL to implement in must design DLL or PLL to implement in devices design first.devices design first.

Could we create a simple DLL circuit Could we create a simple DLL circuit with VHDL or Verilog implementing in with VHDL or Verilog implementing in CPLD, FPGA or ASIC ?CPLD, FPGA or ASIC ?

Purposes of DLLPurposes of DLL

ADC and DACADC and DAC CPU designCPU design Single chip designSingle chip design SOC designSOC design DDR designDDR design Wireless circuitWireless circuit DSPDSP

DLL definition and principleDLL definition and principle DLL ( Delay Lock Loop )DLL ( Delay Lock Loop )

Circuit design with VHDL in Circuit design with VHDL in CPLD and FPGA FlowchartCPLD and FPGA Flowchart

LanguageDescription

RTL ( Register Transfer Level)

Transfer to RTL format

Cell Mapping

Optimal circuit

Netlist of circuit Auto Compiler Flow in CPLD and FPGA

Simulation Waves for Simulation Waves for Lattice CPLDLattice CPLD

Lattice 2032VE-110Lattice 2032VE-110 Lattice 2064VE-100Lattice 2064VE-100 LaLattice M4A3-256/100ttice M4A3-256/100 Altera Altera EPM7032LC44-6EPM7032LC44-6

Lattice 2032VE-110Lattice 2032VE-110

Lattice 2032VE-110Lattice 2032VE-110

Lattice 2064VE-100Lattice 2064VE-100

Lattice M4A3-256/100Lattice M4A3-256/100

Altera EPM7032LC44-6Altera EPM7032LC44-6

Experimental Results on OscilloscopeExperimental Results on Oscilloscope

Lattice M4A3-256/160-10YC 及電路板實際外觀

Lattice 2064VE-100LT100 及電路板實際外觀

Lattice M4A3-256/160-10YC 延遲的輸出波形

Lattice M4A3-256/160-10YC 倍頻的輸出波形

Lattice 2064VE-100LT100 鎖相的輸出波形

Lattice 2064VE-100LT100 鎖相的輸出波形

Lattice 2064VE-100LT100 延遲的輸出波形

Lattice 2064VE-100LT100 鎖相的輸出波形

Lattice 2064VE-100LT100 鎖相的輸出波形

Lattice 2064VE-100LT100 倍頻的輸出波形

Lattice 2064VE-100LT100 延遲的輸出波形

儀器誤差 + 電路板誤差 + 測試棒誤差 + 測試棒接點電阻延遲誤差 + 電路板 RC 延遲誤差

= 900ps

ConclusionsConclusions

鎖相只需一個 延遲時間鎖相只需一個 延遲時間 (only one loc(only one locking time)king time)

只有靜態耗電，沒有動態耗電 只有靜態耗電，沒有動態耗電 可輕易的實現於可輕易的實現於 CPLDCPLD ，， FPGAFPGA ，， ASIC ASIC Fully IP Fully IP 無無 JitterJitter 完全沒有類比電路，也不需要完全沒有類比電路，也不需要 ICIC 外部的電阻外部的電阻

電容或者是電感 電容或者是電感 無無 VCO VCO 內部震盪器內部震盪器

pdT pdT