1. elementary amplifiers - utcluj.ro · figure 1. operating principle of an elementary voltage...

Analog Integrated Circuits – Fundamental Building Blocks Elementary Amplifiers

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1. Elementary amplifiers

Elementary amplifier stages are fundamental building blocks in analog integrated circuits. They can be found in almost any analog signal processing circuitry, starting with the most simple operational amplifier to the most complicated systems, such as PLL-s and analog to digital converters. Three basic amplifier configu-rations are known, depending on the topology of the input transistors. Common emitter or common source stages are typically voltage amplifiers if they see capacitive or high impedance loads at their output. Com-mon collector or common drain configurations are used as voltage followers, power amplifiers or impedance matching circuits. Common base or common gate stages are less often encountered and are mostly used as current buffers. This material only deals with voltage amplifiers and their specific parameters.

Simple voltage amplifiers are always built around an input transistor, bipolar or MOSFET, in common emitter/source configuration. This transistor, acting as a voltage controlled current source, performs a voltage to current conversion. The conversion factor is the transconductance Gm of the amplifier. The resulting cur-rent is then injected into a load circuit that reconverts the current into the output voltage. This time, the con-version factor is the equivalent output resistance Rout of the amplifier. The output node must feature high im-pedance in order to achieve a large voltage gain. The operating principle of an elementary voltage amplifier is illustrated in Figure 1. The general small signal model is identical for all the studied variations, even when the input transistor is PNP or PMOS. The differences between topologies result from the identification of the Gm and Rout parameters.

Figure 1. Operating principle of an elementary voltage amplifier

The low frequency voltage gain of the amplifier will always take the form

0out

m outin

VA G RV

(1)

Depending on the type of the voltage controlled current source at the input and on the structure of the load, there are several possible amplifier topologies. Their performances can be defined by considering func-tional parameters such as the voltage gain, output signal range, bandwidth, unity gain bandwidth, poles and zeros of the frequency dependent transfer function.

1.1. The common source one transistor amplifier with resistive load

In this configuration the input voltage to current converter is a single transistor, while the load is a pas-sive resistor. The schematic of the circuit is given in Figure 2.

The operating point of the circuit is found by matching the operating points of the transistor and of the load line specific to the resistor. If a purely capacitive load is assumed, the circuit does not loose DC current at its output. Therefore, the same current I flows through both the transistor and the resistor and sets the bias conditions for both components. The DC current sunk by the transistor depends on the DC component of the input voltage. It results that every VGS of the transistor leads to a different operating point. It is the task of the designer to choose the correct biasing conditions for which the design specifications are fulfilled.


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Figure 2. A one transistor common source amplifier with resistive load

the output voltage range

As the input voltage increases from 0V to larger values, the current I through the amplifier increases according to the second order transfer characteristic of the transistor. The lowest input voltage for which there is a non-zero current through the circuit is equal to the threshold voltage of the transistor. If the transistor is biased in the cut-off region, the current is canceled. Consequently, there is no voltage drop on R and Vout is equal to VDD. Once Vin=VGS becomes larger than VTh, the current increases and the Vout voltage will move away from VDD. For a large input voltage the increased current will cause a significant voltage drop on the resistor and the output voltage will be shifted close to the ground. The decreasing tendency of Vout stops when the saturation condition (VDS>VGS-VTh) of the transistor is no longer fulfilled. When the circuit reaches this operating point the output voltage will saturate at approximately VDSat. The behavior of the amplifier for an increasing input voltage can be followed on the DC transfer function given in Figure 3.

Figure 3. The DC transfer function of the single transistor amplifier with resistive load

As a conclusion, the correct operation of the circuit assumes that the transistor is always biased in the saturation region and the current is never canceled. The instantaneous Vout can swing between VDSat and the supply voltage VDD.

DSat out DDV V V (2)

the small signal low frequency model

The low frequency small signal model is obtained by replacing the transistor with its small signal equi-valent and passivating all constant sources. The result is given in Figure 4.

Figure 4. The low frequency small signal model of the single transistor amplifier with resistive load


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The low frequency model does not take into account parasitic and load capacitances and it is used only to determine the DC voltage gain of the amplifier. The supply voltage has become a ground connection and the substrate transconductance gmb of the transistor has been neglected. Kirchhoff's current law, written for the output node, gives

0out outm in

DS

V Vg Vr R

(3)

The voltage gain A0 of the circuit results

0 ||1 1m out

out mm DS m out

in G RDS

V gA g r R G RV

r R

(4)

An important aspect concerning all the elementary amplifiers described in this section is that they are all inverting. The inversion is caused by the fundamental behavior and current-voltage dependence of transis-tors.

the small signal high frequency model

The small signal high frequency model also takes into account the parasitic and the load capacitances in the amplifier. The parasitic capacitances are introduced by the physical transistor structure, while the load capacitance is typically formed by the next stage that the amplifier is driving with its output. The schematic in Figure 5 explicitly shows the parasitic capacitances in the circuit.

Figure 5. Parasitic capacitances in the simple amplifier with resistive load and non-ideal input voltage source

The capacitances Cin, C1 and C2 can be identified as

1

2

in GS

GD

DB L L

C CC CC C C C

(5)

The corresponding small signal high frequency model can be drawn as illustrated in Figure 6. The mo-del also includes the equivalent resistance RS of the signal source Vin for the generality of the derivation.

Figure 6. Small signal high frequency model of the amplifier with resistive load

Kirchhoff's current law written for the gate of the transistor gives


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1in GS

in GS GS outS

V V sC V sC V VR

(6)

The gate potential of the transistor is found by solving the above equation for VGS.

1

11in S out

GSS in

V sR C VVsR C C

(7)

Writing again Kirchhoff’s current law, this time for the output node, leads to

21

1out outGS out m GS

out

V sR CsC V V g V

R

(8)

By solving this equation for VGS it results

1 2

1

1out outGS

out m

V sR C CV

R sC g

(9)

The two expressions from equations (7) and (9) can be matched and the frequency dependent voltage gain of the amplifier is found to be

1

21 2 1 1 1 2 1 2

1( )

1

m outm

out S in S m out out S in in

Cg R sg

A ss R C C R C C R g R C s R R C C C C C C

(10)

If RS is relatively small and the C2 capacitance is dominated by CL, then A(s) may be approximated

1

21 1 1

1( )

1

m outm

out L S m out out S L in

Cg R sg

A ss R C C R g R C s R R C C C

(11)

Applying the dominant pole approximation (see Appendix 1) to the above expression leads to

0 0

2

21 1 21 2

1 12 2

( )11 1 2 42 2

zp zp

p p pp p

s sA Af f

A ss ss sf f ff f

, (12)

where A0 is the low frequency gain, fp1, fp1 and fzp are the frequencies of two poles and one right half plane zero. The expressions of A0, fp1, fp1 and fzp can be identified as given in equation (13). The corresponding fre-quency response is illustrated in Figure 7.

0 11

21 1

1

1;2 1

1 ;22

m out pout S m L

mp zp

L m SS

L in

A g R fR R g C C

gf fC g R C CRC C C

(13)


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Figure 7. The frequency response of the amplifier corresponding to (10)

A frequency with a special meaning on the magnitude response is the so called unity-gain bandwidth or gain-bandwidth product GBW. The GBW is equal to the frequency where the magnitude response crosses the Ox axis and becomes equal to unity (0dB). Its value is determined by multiplying the low frequency gain A0 with the dominant pole fp1.

0 11

2 2m

p m outout L L

gGBW A f g RR C C

(14)

The pole-zero configuration of an amplifier can often be inferred intuitively by a simple inspection of the schematic. The rules used for this procedure are as follows:

every node in the signal path introduces a pole in the circuit gain or transfer function. The fre-quency of this pole is defined by the equivalent small signal resistance and the total capacitance of the considered node.

1

2pii i

fR C

(15)

if a node can be identified as the output of an inverting amplifier and there is a capacitive shunt between the input and the output, then the node will also introduce a right half plane zero into the transfer function as a consequence of the Miller effect (see Appendix 2). The frequency of the zero will depend on the shunt capacitance and on the inverting amplifier transconductance.

2

mpi

shunt

gfC

(16)

if the output resistance of the voltage source driving the input of the inverting amplifier is not zero, then the input-output shunt capacitance is reflected back to the input, multiplied by the DC gain of the amplifier. This capacitance, together with the source resistance will introduce an additional pole into the transfer function. The rigorous derivation of the pole frequencies be-comes rather complicated and further simplifications of the form in (11) are not possible (see the word of caution with the Miller effect!). The exception to this is encountered when the C1 is enlarged on purpose and RS is also large, in which case the additional pole at the amplifier in-put becomes dominant.


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If the input voltage source is ideal and its resistance is RS=0, the second pole moves to infinitely large frequencies and the gain will only exhibit the dominant pole fp1 and the right half plane zero fzp. The amplifier gain is then

1 10

1

1

11 1( )

1 1 1

m out m outzpm m

out L out L

p

sC C Ag R s g R sg g

A s ssR C C sR C

(17)

While the low frequency gain remains the same, the pole and zero frequencies can be written

0 11

1; ;2 2

mm out p zp

out L

gA g R f fR C C

(18)

The corresponding simplified magnitude and phase responses are illustrated in Figure 8.

Figure 8. The frequency response of the amplifier – RS has been neglected

1.2. The common source one transistor amplifier with diode load

The topology of this amplifier is very similar to the topology of the common source amplifier with re-sistive load, but the passive load resistance is replaced by a transistor in diode connection. The schematic of the circuit is illustrated in Figure 9.

Figure 9. Schematic of the common source amplifier with diode load


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The operating point of the circuit is found by matching the drain currents ID1 and ID2 of the two tran-sistors. These currents are

211

1

222

2

12

2

n oxD in Th out

p oxD DD out Th

C WI V V VL

C WI V V V

L

(19)

The operating point is defined by the voltage Vout for which ID1=ID2. The dependence of ID1 on Vout is the output characteristic of M1 while the dependence of ID2 on Vout gives the transfer characteristic of M2. The operating point is found at the intersection of these two characteristics as shown in Figure 9.

The load transistor is biased either in saturation (VSD=VSG and the saturation condition is always satis-fied) or in the cut off region when Vout increases above VDD-|VThp|. M1 should be biased in saturation for the correct operation of the amplifier. It results that the useful output voltage range is from VDsat of the input tran-sistor to VDD-|VThp|. The DC transfer function of the circuit is given in Figure 10.

Figure 10. The DC transfer function of the common source amplifier with diode load

The DC transfer function suggests the behavior of the circuit at the limits of the output voltage range. For small input voltages the transistor M1 will deliver very little current, the voltage drop across M2 will be small and the output voltage will be shifted toward VDD. Theoretically, if Vin < VThn, then Vout should settle to VDD. In reality, subthreshold leakage prevents Vout to sit at VDD. As Vin increases, the weak inversion current will push Vout away from the supply voltage, causing a nearly linear transfer characteristic.

At larger input voltages Vout decreases according to a practically linear function. The slope of the curve in the linear region defines the gain of the amplifier. For a large input voltage M1 absorbs a very large current from the output node. Due to the low gain, the output voltage cannot reach the theoretical lower limit of the voltage range (VDSat) before the current becomes slowly limited by velocity saturation.


The small signal low frequency model of the circuit is constructed by replacing both transistors with their linear equivalent as shown in Figure 11.

Figure 11. The small signal low frequency model of the common source amplifier with diode load


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The low frequency gain is calculated by writing Kirchhoff’s current law at the output node.

1 1 2 21 2

0||out

m GS m GSDS DS

Vg V g Vr r

(20)

The gate-source voltage of M1, is equal to the input voltage while VGS2=Vout. Replacing these voltages into (20) leads to

1 0 12

1 22

11 || || m

out

out outm in m

in mGDS DSRm

V Vg V A gV gr r

g

(21)

The above equation shows that, if the transistor operating points are approximately matched, then the low frequency gain is close to unity. Therefore, this configuration is typically used as voltage buffer or limi-ting amplifier.


The schematic of the amplifier, with its associated capacitances, and the small signal high frequency model are illustrated in Figure 12. The input source resistance RS and the capacitance Cin have been omitted since their impact on the high frequency behavior of the amplifier is the same as for the implementation with a resistive load.

Figure 12. The common source amplifier with diode load – emphasized capacitances and the small signal high frequency model

The capacitances C1 and C2 can be identified from the schematic as

1 1

2 1 2 2

GD

DB DB GS L

C CC C C C C

(22)

The equation describing the operation of the amplifier is

2

1 1

1

in

out outin out m GS

outV

V sR CsC V V g V

R

(23)

By rearranging the terms and calculating the ratio Vout/Vin, the frequency dependent gain results

10

1

1 2

11( )

1 1

m outzpmout

in out

p

sC Ag R sgVA s sV sR C C

(24)

It can be seen that the gain exhibits one pole and on right half plane zero. The parameters A0, fp and fzp


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can be written by identifying the coefficients of s in (24) and the output resistance Rout in (21).

1 2 10

2 1

; ;2 2

m m mp zp

m L

g g gA f fg C C

(25)

The corresponding frequency response is given in Figure 13. The unity-gain bandwidth GBW looses its significance here since the low frequency gain already approaches unity.

Figure 13. The magnitude and phase responses of the common source amplifier with diode load

1.3. The common source amplifier with current source load

The amplifiers discussed so far were not able to provide high gain since the output resistance was limi-ted by the resistive or diode load. High gain elementary amplifiers are invariably built by connecting two current sources in series. One source is controlled by the input voltage, providing the necessary voltage to current conversion, while the second reconverts the current into voltage through its very large output resis-tance. The most simple form of current source used in amplifiers is a single transistor. The resulting schema-tic is illustrated in Figure 14. The circuit works identically if the PMOS transistor is used as input.

Figure 14. Schematic and operating point of the common source amplifier with current source load


Assuming that the current I flows through both the transistors, the operating point is found by intersec-ting the output characteristics of the two transistors. For a high gain operation it is critical to keep both tran-sistors in the saturation region. Consequently, the instantaneous output voltage should not push any VDS vol-


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tage below VDsat. If this happens, the amplifier looses its gain and Vout will be clipped (distorted). These limi-tations can also be seen on the DC transfer characteristic given in Figure 15. The abrupt drop of the output voltage around the 1.5V operating point suggests a high gain.

Figure 15. DC transfer function of the common source amplifier with current source load


Replacing both transistors with their small signal model leads to the equivalent schematic in Figure 16.

Figure 16. DC transfer function of the common source amplifier with current source load

The equation that describes the balance of currents at the output node is identical to (20), written again for convenience.

1 1 2 21 2

0||out

m GS m GSDS DS

Vg V g Vr r

(26)

By replacing VGS1 with Vin and finding VGS2=0, the low frequency gain of the amplifier is

0 1 1 2||m out

outm DS DS

in G R

VA g r rV

(27)


The behavior of the common source amplifier with current source load is similar with the behavior of the implementation with resistive load. The schematic of the circuit, emphasizing the capacitances, and the high frequency model are given in Figure 17.

The capacitances C1 and C2 can be identified from the schematic as

1 1

2 1 2 2

GD

DB DB GD L

C CC C C C C

(28)

Since the high frequency model of the amplifier is identical with the one in Figure 12, the high fre-quency gain will also be identical.


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Figure 17. The common source amplifier with current source load – emphasized capacitance and high frequency model

10

1

1 2

11( )

1 1

m outzpmout

in out

p

sC Ag R sgVA s sV sR C C

, (29)

where A0, fp and fzp depend on the transconductance gm1, the output resistance from (27) and the capacitances.

0 1 1 2

1 2

1

1

||1

2 ||

2

m DS DS

pDS DS L

mzp

A g r r

fr r C

gfC

(30)

Additionally, the unity-gain bandwidth is written as

1

0 1 1 21 2

1||2 2

mp m DS DS

DS DS L L

gGBW A f g r rr r C C

(31)

The corresponding frequency response is given in Figure 18.

Figure 18. The magnitude and phase responses of the common source amplifier with current source load


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1.4. The common source amplifier with cascoded input

In this amplifier configuration the input current source is cascoded for a larger output resistance. The schematic of the circuit is given in Figure 19. Both, the NMOS and PMOS versions of the amplifier may be used in practical designs, depending on the DC component of the input signal.

Figure 19. Schematic and operating point of the common source amplifier with cascoded current source input


The operating point of the circuit is found by intersecting the output characteristics of the cascode cur-rent source M1-M2 and of the load transistor M3. For a high gain operation all transistors must be maintained in the saturation region, even for the peak values of the output voltage. The higher limit of the useful output voltage range is determined by the saturation condition of M3. Thus, the instantaneous value of Vout should not swing higher than VDD-VDSat3.

In theory, the lower limit of the output voltage range is determined by the minimal 2VDsat voltage, im-posed by the biasing conditions of M1 and M2 in saturation. However, in practice the variations of Vout are ab-sorbed by the cascode transistor which also defines de drain-source voltage drop of M1. The current through the NMOS section of the amplifier is set by this transistor M1 and must be maintained constant as Vout moves around the operating point. Therefore, M1 must remain in saturation even for a large negative output voltage swing and its VDS voltage is regularly chosen to be (1,5…2)VDSat1. In this case, the instantaneous value of Vout should not drop below (2,5…3)VDSat1.

The DC transfer function of the amplifier, illustrated in Figure 20, shows the theoretical output voltage range. The abrupt variation of the curve around the operating point suggests a large DC gain. The operating point is typically chosen somewhere in the middle of the voltage range in order to obtain the largest possible swing without clipping Vout.

Figure 20. DC transfer function of the common source amplifier with cascoded current source input


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The small signal low frequency model is obtained by replacing all transistors with their small signal equivalent. The resulting schematic is given in Figure 21. Since both the gate and the source of the load tran-sistor M3 are connected to a constant voltage, VSG3 becomes equal to zero in the small signal model and the voltage controlled current source gm3VSG3 can be completely eliminated. It results that M3 contributes only with its rDS3 to the amplifier model.

Figure 21. Small signal low frequency model of the common source amplifier with cascoded current source input

Kirchhoff's current law written for the output node leads to

22 2

2 3

0out S outm GS

DS DS

V V Vg Vr r

(32)

This equation can be solved for the source potential VS2 of M2.

2 32

3 2 21DS DS

S outDS m DS

r rV Vr g r

(33)

The balance of currents in the source of M2 results

2 22 2 1 1

2 1

out S Sm GS m GS

DS DS

V V Vg V g Vr r

(34)

After identifying VGS1=Vin and VGS2= -VS2 from the amplifier schematic, inserting the expression (33) into the equation (34) gives the low frequency gain A0 of the circuit.

3 1 2 2 1 3 2 2 10 1 1

3 2 1 2 2 1 3 2 2 1m

out

DS DS m DS DS DS m DS DSm m

DS DS DS m DS DS DS m DS DSGR

r r g r r r g r rA g gr r r g r r r g r r

(35)

This expression can also be found intuitively by knowing that the input transistor is M1 (Gm=gm1) and evaluating the output resistance that is

3 2 2 13 3 2 2 1

3 2 2 1

|| || DS m DS DSout DS N DS m DS DS

DS m DS DS

r g r rR r R r g r rr g r r

, (36)

where RN is the equivalent output resistance of the NMOS cascode current source. When RN is much larger than rDS3, which is typically the case, the gain can be approximated as

0 1 3m DSA g r (37)


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The schematic of the amplifier with the emphasized capacitances and the corresponding small signal high frequency model are illustrated in Figure 22. It can be seen that cascoding the input source introduces an additional node with its own equivalent resistance and parasitic capacitance C2 that will influence the am-plifier frequency response.

Figure 22. Small signal high frequency model of the common source amplifier with cascoded current source input

The frequency dependent gain A(s) of the amplifier can be derived by writing Kirchhoff's current law twice, first at the output node and next at the source of M2. The first equation is

3 32

2 22 3

10out DSout S

m GSDS DS

V sr CV Vg Vr r

, (38)

which can be solved for VS2 yielding

3 2 2 3 32

3 2 21DS DS DS DS

S outDS m DS

r r sr r CV Vr g r

(39)

The second equation is

2 1 221 2 2 2 1 1

2 1

1S DSout Sin S m GS m GS

DS DS

V sr CV VsC V V g V g Vr r

(40)

This can be again solved for VS2 that results

1 2 1 1 1

21 2 2 1 2 1 2 1 2

DS DS m in DS outS

DS DS m DS DS DS DS

r r sC g V r VV

r r g r r sr r C C

(41)

By replacing VGS1=Vin and matching the two expressions of VS2 from (39) and (41), some rather tedious calculations lead to the frequency dependent voltage gain

1 3 2 2 11

1 3 2 2 2 1 1

21 2 3 1 2 1 2 3 3 1 23 3

1 3 2 2 2 1 1 3 2 2 2 1

11

( )1

DS DS m DSm

DS DS DS m DS DS m

DS DS DS DS DS DSDS

DS DS DS m DS DS DS DS DS m DS DS

r r g r Cg sr r r g r r g

A sr r r C C r r r C C C

s r C sr r r g r r r r r g r r

(42)

If the drain-source resistances are considered to be very large, and the capacitor C3 (including CL) is much larger than C1 and C2, then A(s) can be approximated with


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101 3

1

2 3 3 1 23 3

2 1 2

11( )

1 1 1

m DSzpm

DSDS

m p p

sC Ag r sg

A sr C C C s ss r C s

g

(43)

The dominant pole approximation helps in identifying the parameters of this function. The parameters are consistent with the ones found by the intuitive approach discussed for the common source amplifier with resistive load (two nodes give two poles and one inverting stage with shunt C1 gives one positive zero).

0 1 3

13

22

1 2 2 1 2

1

1

1

1 12 2

12 2

2

2

m DS

pds L out L

mp

S

mzp

m

L

A g r

fr C R C

gfC C R C C

gfCgGBW

C

(44)

The corresponding frequency response of the circuit is illustrated in Figure 23. The unity-gain band-width inherits its expression and significance from the common source amplifier with current source load.

Figure 23. Frequency response of the common source amplifier with cascoded current source input

1.5. The symmetrical cascode common source amplifier

The symmetrical cascode common source amplifier is derived from the configuration with a cascode input stage and a simple transistor connected as current source load. The single transistor current source is simply replaced by a cascode current source in order to increase the output resistance and implicitly the vol-tage gain of the amplifier. The input transistor can be either a NMOS or a PMOS. The schematic of the cir-cuit is illustrated in Figure 24.


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Figure 24. Schematic and operating point of the symmetrical cascode common source amplifier


The operating point of the circuit is found at the intersection of the output characteristics correspon-ding to the NMOS and the PMOS current sources as shown in Figure 24. The large voltage gain can only be maintained if all the transistors are biased in the saturation region. It results that neither of the minimum out-put voltages of the two current sources should be violated by the changing output signal, otherwise clipping and distortion occurs. Since the cascode current sources are symmetrical and both need at least 2VDSat to ope-rate correctly, the output voltage range varies between 2VDSat and VDD-2VDSat. In practice the voltage range suffers further restrictions when the drops across M1 and M4 are set to (1.5...2)VDSat, a rule inherited from the design of the cascode current sources.

The DC transfer characteristic of the amplifier is illustrated in Figure 25. The non-linearity caused by the voltage limitations can be clearly seen at approximately 2VDSat and VDD-2VDSat. The nearly vertical linear section of the curve suggests a very large voltage gain, typically larger than 60dB. The DC component of the output voltage should be chosen to be around VDD/2 in order to maximize the signal swing.

Figure 25. DC transfer function of the symmetrical cascode common source amplifier


The small signal low frequency model is obtained by replacing all the transistors with their small sig-nal equivalent and by passivating all the constant sources. The resulting schematic is presented in Figure 26. The transistor M4 has its gate and source connected to small signal ground. Consequently, the current source gm4VGS4 has been removed from the schematic. Moreover, since the M3-M4 current source does not actively provide signal current, it can be simply replaced by its equivalent resistance Rp, where

3 4 3 3 4 3 3 4p DS DS m DS DS m DS DSR r r g r r g r r (45)


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Figure 26. Small signal low frequency model of the symmetrical cascode common source amplifier

The low frequency voltage gain is determined in a similar manner as for the simple cascode input con-figuration, but the resistance rDS3 of the load is replaced by Rp. A0 is then

3 3 4 2 2 10 1 1 2 2 1 3 3 4

3 3 4 2 2 1

||m out

m DS DS m DS DSm m m DS DS m DS DS

m DS DS m DS DS G R

g r r g r rA g g g r r g r rg r r g r r

(46)


The schematic of the amplifier with all the parasitic capacitances is given in Figure 27.

Figure 27. Small signal high frequency model of the symmetrical cascode common source amplifier

The equations (38)-(43) are still valid but rDS3 is replaced by the appropriate output resistance Rout. It results that the pole-zero configuration of the frequency dependent voltage gain does not change compared to the asymmetrical version and A(s) is

101

1

2 3 1 23

2 1 2

11( )

1 1 1

m outzpm

outout

m p p

sC Ag R sg

A sR C C C s ss R C s

g

(47)

The dominant pole approximation used for factoring the denominator leads to the high frequency para-meters given in (48). It can be seen that the intuitive evaluation of the singularities gives the same results. The output and the S2 nodes introduce a pole each. The pole p1, defined by Rout and CL will dominate the fre-quency response and determines the bandwidth, while the second pole, p2, is positioned at high frequencies. Additionally, the Miller effect across M1 introduces a right half plane zero into the expression of the gain.


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0 1 1 2 2 1 3 3 4

1

22

1 2 2 1 2

1

1

1

||1

21

2 2

2

2

m out m m DS DS m DS DS

pout L

mp

S

mzp

m

L

A g R g g r r g r r

fR C

gfC C R C C

gfCgGBW

C

(48)

The corresponding magnitude and phase responses of the amplifier are illustrated in Figure 28.

Figure 28. Frequency response of the symmetrical cascode common source amplifier

1.6. The folded cascode common source amplifier

This amplifier configuration is similar to the asymmetrical cascode but the input cascode stage is fol-ded, allowing a better use of the voltage budget. The folding means that the cascode transistor is of the com-plementary type as illustrated in Figure 29. Although its advantages as a single stage are not be obvious, the folded cascode amplifier is typically used for designs in low voltage technologies for extending signal swing.

Figure 29. Schematic and operating point of the folded cascode amplifier


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The operating point of the amplifier is found by intersecting the output characteristic of the cascode current source M1-M2 with the output characteristic of the transistor M3. The output voltage range is defined by the biasing requirements of all the transistors in the saturation region. The cascode transistor M2 together with M1 and M4 need at least 2VDSat voltages, setting the theoretical upper limit of the voltage range to VDD-2VDSat. The lower limit is defined by the VDSat requirement of M3.

The DC transfer characteristic of the amplifier is illustrated in Figure 30. It can be seen that the shape of the curve and the slope of the linear section (the low frequency gain) are very similar to the corresponding characteristic of the simple cascode input amplifier. The DC component of the output voltage can be set to VDD/2 in order to maximize the signal swing and avoid clipping.

Figure 30. DC transfer function of the folded cascode common source amplifier


The small signal low frequency model can be obtained by replacing the transistors with their small sig-nal equivalents. The transistors M3 and M4 have the gates connected to a constant voltage. Therefore, the vol-tage sources gm3VGS3 and gm4VGS4 are eliminated from the schematic, these transistors contributing only with their drain-source resistances rDS3 and rDS4. The resulting circuit is illustrated in Figure 31.

Figure 31. Small signal low frequency model of the folded cascode amplifier

The low frequency gain is calculated by writing Kirchhoff’s current law twice, once for the output and next for the node at the source of M2. The first equation for the balance of the currents at the output node is

22 2

2 3

0out S outm GS

DS DS

V V Vg Vr r

(49)

By identifying the VGS2 voltage as VGS2= -VS2 from the schematic, the source potential of M2 can now be expressed as a function of the output voltage Vout.


20

22

2 3 2 2|| 1DS

S outDS DS m DS

rV Vr r g r

(50)

The balance of the currents at the source terminal of M2 leads to

2 22 2 1 1

2 1 4||out S S

m GS m GSDS DS DS

V V Vg V g Vr r r

, (51)

where VGS2= -VS2 and VGS1=Vin. The low frequency voltage gain of the amplifier is then

3 2 2 1 40 1 1 3

3 2 2 1 4

||||

m m out

out

DS m DS DS DSm m DS m out

DS m DS DS DSG G RR

r g r r rA g g r G R

r g r r r

(52)


The small signal high frequency model is built by adding the capacitive effects to the circuit. Figure 32 shows the schematic of the folded cascode amplifier with emphasized parasitic capacitances and the corres-ponding small signal model.

Figure 32. Small signal high frequency model of the folded cascode common source amplifier

The capacitances C1, C2 and C3 can be identified as

1 1

2 4 2 1 4

3 2 3 2

GD

GD SB DB DB

L DB DB GD

C CC C C C CC C C C C

(53)

The equations (49) and (51) can be adjusted to include the capacitances. The equations describing the operation of the amplifier are then

3 322 2

2 3

2 1 4 221 2 2 2 1 1

2 1 4

10

1 ||||

out DSout Sm GS

DS DS

S DS DSout Sin S m GS m GS

DS DS DS

V sr CV Vg Vr r

V s r r CV VsC V V g V g Vr r r

(54)

By considering VGS2= -VS2 and VGS1=Vin, this system can be solved for A(s). The frequency dependent voltage gain results


21

101 3

1

2 3 3 1 23 3

2 1 2

11( )

1 1 1

m DSzpm

DSDS

m p p

sC Ag r sg

A sr C C C s ss r C s

g

(55)

From the expression of A(s) it can be seen that is has two poles and one right half plane zero. By assu-ming that C3 is dominated by CL and is the largest capacitance in the circuit, applying the dominant pole ap-proximation gives the following high frequency parameters:

0 1 3 1

13 3

22

1 2

1

1

1

1 12 2

2

2

2

m DS m out

pout DS L

mp

mzp

m

L

A g r g R

fR C r C

gfC C

gfCgGBW

C

(56)

The unity-gain bandwidth has the same significance as for the other common source configurations. The corresponding magnitude and phase responses are presented in Figure 33

Figure 33. Frequency response of the folded cascode common source amplifier

Appendix 1: the dominant pole approximation

The dominant pole approximation helps in building the magnitude and phase responses of a second or-der system where the denominator of the frequency dependent gain or transfer function is a second order po-lynomial in which the roots (poles) cannot be directly separated. The form of such a transfer function, depen-ding on the frequencies of the two poles, can be written as


22

22

1 2 1 2 1 2

1 1 1( )11 11 1 1

p p p p p p

A ssa s bs s ss

(A.57)

If one of the poles, for example p1, is situated at much lower frequencies then the other, then the coef-ficient of s in the denominator can be approximated with 1/ωp1. The lowest frequency pole, p1 in the particu-lar given example, is often called the dominant pole because it determines the behavior of the circuit at low and average frequencies. The transfer function becomes

2 2

1 1 2

1 1( )11

p p p

A ss s sa s b

, (A.58)

where the a and b variables depend on the circuit parameters. The frequencies corresponding to the two poles can be identified as

1

2

121

2

p

p

fa

afb

(A.59)

Appendix 2: the Miller effect

The Miller effect can be observed when the input and the output of an inverting amplifier are shunted with a capacitance. This is illustrated in Figure 34.a.

Figure 34. The Miller effect seen around an inverting amplifier

The current flowing through the shunt capacitance CM is

M in outI sC V V (A.60)

By considering the effect of the amplifier, Vout= -aVin, the current becomes

11M in M outaI sC a V sC V

a

(A.61)

The corresponding impedances can be written

1 1 1;

11 1

in out

M MM

V VI sC a I sCsC

a

(A.62)

The shunt capacitance can be divided into two equivalent capacitances, one connected to the input and


23

one connected to the output node as illustrated in Figure 34.b. Splitting the capacitance must not influence the operation of the amplifier. Therefore, the currents at the input and the output must be conserved and the impedances are

1 2

1 1;in outV VI sC I sC (A.63)

The equivalent capacitances reflected to the input and to the output can be identified by matching the impedances in equations (A.62) and (A.63). The capacitances are then

1 211 ;M M M M

aC C a aC C C Ca

(A.64)

The equation above shows that the shunt capacitance is reflected back to the input, multiplied by the gain of the amplifier and to the output with the same absolute value but a negative sign. While the input ca-pacitance C1 is positive and augments the total capacitance of the input node, the negative capacitance C2 cannot be subtracted from the total output capacitance and will typically introduce a right half plane zero into the total frequency dependent gain of the amplifier.

As a word of caution, when using the Miller effect to predict pole and zero locations, one should also account for the input source resistance. The shunt to input capacitance transformation given in (A.64) is only valid in this form only if the input source resistance and the input capacitance are neglected. If this is not the case, the additional pole introduced by the Miller effect cannot be simply isolated and the amplifier transfer function should be treated as a whole. Unfortunately, this happens more often than not in practical circuits. A typical example in this sense has been given when discussing the frequency response of the common source amplifier with resistive load.

1. elementary amplifiers - utcluj.ro · figure 1. operating principle of an elementary voltage...

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