1 h.hübner et al. mam 2006 grenoble infineon micro contacts with sub-30µm pitch for 3d...

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H.Hübneret al.MAM 2006Grenoble In

fin

eon

Micro Contacts with Sub-30µm Pitch for 3D Micro Contacts with Sub-30µm Pitch for 3D Chip-on-Chip IntegrationChip-on-Chip Integration

MAM 2006, Grenoble, March 2006

Holger HHolger Hübnübner, er, Sabine PenkaSabine Penka Markus Eigner, Wolfgang Gruber, Markus Nobis, Markus Eigner, Wolfgang Gruber, Markus Nobis,

Günter Kristen, Manfred SchneegansGünter Kristen, Manfred Schneegans (Munich)(Munich)

Bernd Barchmann, Stephan JankaBernd Barchmann, Stephan Janka ((Regensburg)Regensburg)

Infineon Technologies AG Infineon Technologies AG

GermanyGermany

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H.Hübneret al.MAM 2006Grenoble

Historical BackgroundHistorical Background

Theory and BasicsTheory and Basics

Comparison of BGA vs SOLIDComparison of BGA vs SOLID

Process FlowProcess Flow

Cost Comparison with FBGACost Comparison with FBGA

Experimental ResultsExperimental Results

OutlineOutline

Reliability ResultsReliability Results

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Due to the steady increase of information density and shrink of

design rules in the silicon

1. the traditional DIL package had been replaced by surface mount

technologies using solder bumps (Ball Grid Arrays – BGA).

2. and also the first level wire bonds inside the package will be replaced

by solder bumps (FBGA Fine Pitch Micro Bumps)

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Steadily Shrinking Dimensions of BGAsSteadily Shrinking Dimensions of BGAs

Micro bumps

Chip-to-Chip

Lead free

BGA

Chip-to Board

PbSn

Chip–to–substr.interconnect

future?

Chip–to–chipinterconnect

60/120 30/60 15/30120 / 240

Package–to–board interconnects

200µm / pitch 500 µm

today

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Problems with Shrinking DimensionsProblems with Shrinking Dimensions

Decreasing compliance of the solder bump

Increasing growth velocity and influence of intermetallic phases during

solder reflow - especially for lead free solders

Complicated architecture of the metallization

(e.g. Cu – Ni/Au – SnAg – Ni – Cu)

A mix of multiple phases in the solder bump (electro migration driven)

Consumption of diffusion barrier during (high temperature) operation

Risc of erosion of the under-bump metallization

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Argumentation for a New TechnologyArgumentation for a New Technology

(1) Compliance is only given (and needed) for chip-to-board interconnects

(2) We focus on chip-to-chip interconnects

(3) For chip-to-chip connections bumps must be low-scale and high density

(4) If the influence of the intermetallics grows,

why not build bumps completely out of intermetallics ?

(5) Our new interconnect technology replaces the soft soldering by a

soldering process called Solid-Liquid-InterDiffusion (SOLID)

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OutlineOutline


8


T

M L

liquid

solid

high melting phase

solid

soldering

T

T

2

1

MxLy

Sn melts at the soldering temperature (231°C)

Sn and Cu react to Inter Metallic Compounds (IMCs)

The melting point raises by several 100°C to T2 and

The joint solidifies isothermally at the processing temperature

Cu - Sn (3µm) - Cu

Sn Cu

Cu3Sn ()Cu6Sn5 ()

Metallurgical Basics of the SOLID TechnologyMetallurgical Basics of the SOLID Technology

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BA

Sn

Cu

Cu

Kinetic of Phase GrowthKinetic of Phase Growth

Diffusion paths

A - via grain boundaries into the liquid solder

B - through the - phases

C - via the - phases(less important)

Kinetics

Initially very rapid Cu-diffusion and growth of -phases via A (convection enhanced material transport within the liquid Sn)

At the same time the -phases grow laminar impeding more and more the phase growth (solid state diffusion via C)

After Sn is consumed completely, the -phase will be transformed to -phase (solid state diffusion)

C

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Kinetic of Phase Growth *Kinetic of Phase Growth *

A 3 µm gap solidifies within a few ten seconds

The ε-phase needs 15 - 20 min for the transformation of a 3 µm layer

S. BaderMPI für MetallforschungStuttgart, 1990

Dynamics of Phase Growth

0

0.5

1

1.5

2

2.5

3

0 1 2 3 4 5

Time / min

Th

ick

ne

ss

/ µ

m

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OutlineOutline


12


Comparison of Solder ProcessesComparison of Solder Processes

BGA - Solder bump SOLID interface

diffusion barrier

SnCu

CuCu3Sn

Large solder volumen

Phase growth is controlled by

- diffusion barrier (Ni/Au) and

- low temperature budget

Solidification by cooling

Very thin solder layer

- No barrier

- Simple metallurgy

Sn is completely consumed

Solidification isothermally

Sn

Cu

Cu

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Comparison of Solder ProcessesComparison of Solder Processes

FBGA

Metallization and solder apply

SOLID

Metallization and solder apply

Pick & place (no flux)

Soldering

1st step

2nd step

3rd step

4th step

Reflow

Pick & place (flux)

Soldering

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Comparison of ProcessesComparison of Processes

reflow defines shape of the balls before pick & place

All pads must be the same size

All pads must be the same shape

Larger spacing between balls, because balls expand

Complicated metallurgy (barrier, multiple IMCs)

Phase growth not finished

High homologous temperature

BGA SOLID

reflow and soldering in a single stepafter pick & place

Different sizes possible

Different shapes possible

Smaller spacing (only limited by the bonder alignment)

Only two metals involved (barrier free, one IMC)

Thermodynamical stable

Low homologuos temperature

Same processing for solder apply, but

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Geometrical Comparison of BGA vs SGeometrical Comparison of BGA vs SOLIDOLID

Soft solder bumps

SOLID contacts

15µm / pitch 30 µm(limited by the bonder alignment accuracy)

7,5/15

Micro bumpsBGA

Transition from soft solderto Inter Metallic Compounds (IMC)

60/120 30/60 15/30120 / 240200µm / pitch 500 µm

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SOLID-Face-to-Face StackSOLID-Face-to-Face Stack

Top chipCu and Sn coating

Bottom chipCu coating, bond pads

No underfill

Inter chip vias15 x 15 µm² 5 µm vias to LM

Redistribution

Insulation trenches15 µm

Passive areaheat spreader

External IOsstandard wire bonds

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Benefits of the Planar Metal InterfaceBenefits of the Planar Metal Interface

One single step for electrical and mechanical contact

Additional wiring layer

Very flat design

Electrical shield / base plane

Excellent heat conduction

Mechanical reinforcement of the point contacts

The top chip does not need an Al layer

No space consumption by testpads

(Testpads can be designed within the passive area)

Top chip thinning after soldering

Modular process for multi-tier stacking (Si thru holes)

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OutlineOutline


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MetallizationMetallization

(Testing)Top wafer thinningSingulationPick, flip and placeSoldering

Bond process Chip to Wafer

Wafer processesInitial stateOpened passivationVias Ø 5 µm, Al or Cu

SputteringTiW barrier 50nmCu seedlayer 100nm

Litho Insulation trenches

Plating moduleCu 5µmTop wafer only: Sn 3µmResist stripWet etch seedlayer and barrier

CuSn

Resist

Oxide

c-Si

AlSiCu

Cu

Sn

TiW

Cu seed

IMOX

c-Si

LM

M1

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Pick & PlacePick & Place

1st Step – Sticking the chips on wafer

Application of a liquid sticking agent by a jet dispenser

The hard contact with the cold wafer

• freezes the sticking agent w/o time delay

• parallizes the chips (tilt adjustment)

T = 70°C

T = 25°C T = 25°C

Solidification by cool down

Demands on the sticking agent (bibenzyl):• Melting point 50 - 60°C• High vapour pressure (evaporation in vacuum)• Inert, non corrosive, non hygroscopic• No residues

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2nd Step – Soldering of the populated wafer

Demands on the soldering process

Evaporation of the sticking agent

Reduction of the Cu- und Sn-surfaces

Complete transformation of Sn to η-phase

No lateral shift of the chips during heating (horizontal placement)

No contamination of the surface (residue-free flux)

SolderingSoldering

Process parameters: 1 min @ 260°C; vacuum or inert gas

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3rd Step (optional) – Final transformation η- into ε-phase

Batch oven

Inert gas

AlloyingAlloying

Process parameter: 20 min @ 300°C

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OutlineOutline


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Cost reduction potential comes from

Thinner metal layers

Additional redistribution layer given „for free“

No Al-layer in the top chip

No flux cleaning after soldering

No underfill required

Wafer metallization is similar to electro plated FBGA

Standard equipment for test, pick & place, soldering and inspection

Only one minor add-on: jet dispenser

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OutlineOutline


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30 µm

Standard contact with

15 µm

Pitch 30 µm

Via to last metal 5 µm

Demonstrator for20 µm pitch

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Standars contacts (defined by bonder alignment): 15 x 15 µm², 5 x 5 µm² vias to last metal

10 µm pads with 20 µm pitch demonstrated

5 µm crossed lines have successfully been bonded

No influence of particles seen (class 10000 CR)

Thickness of the top chips: 80 µm, typically 125 µm

Shear strength of the bond: >120 N @ 25 mm² chip size

Measured contact resistance: 5 m for a standard contact

Worst case simulation of stray capacities: 34 – 40 fF (w/o and w/ underfill)

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Modellumped circuit

Contact dimensions

15 x 15 µm²40 fF (simulation)5 m (measured value)

Conductor

width 200 nm

thickness 350 nm

resistance 90 m/

capacitance 250 aF/µm

(standard Cu-wire in C9)

Transit Frequency of a Single ContactTransit Frequency of a Single Contact

R

ContactC

R

C

R

Circuit line

Transit Frequency

10

100

1000

10000

10 100 1000

Length (µm)

GH

z

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Problem: Solder Squeeze OutProblem: Solder Squeeze Out

Wrong design rule (w/o stiching)

New design rule(stiched tin lines)

Redistribution lines are prone to solder sqeeze out

Theoretical background (surface tension) allows for exact calculation of design rules

Stiched tin volume prohibits solder squeeze-out

X-ray image of a chip stack

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OutlineOutline


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Corrosion Behaviour of an Uprotected Solder JointCorrosion Behaviour of an Uprotected Solder Joint

Reference probe

FIB preparation of the chip edge no underfill

After 96h @ 121°C, 100%

corrosion of the -phase

-phase is inert

minor Cu-corrosion

Cu

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FIB preparation after 1000 h HTS (85°C, 85%)

Top chip thinned by wet etch

Corrosion Free CavitiesCorrosion Free Cavities

No corrosion inside the stack cavity.

Metallical seal ring

Organical sealring (FF2200) protects -phase

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Temperature Cycles (TC)Temperature Cycles (TC)

73 chains of 500 standard contacts (15 x 15 µm², via 5 x 5 µm²) from LM to LM

1000 cycles -65…150°C, 1 h each

F2F_SM1 Chain_B-500 Chain12

t [h]1.0008006004002000

dR

/R [

%]

@ 1

00

00

µA

2,01,51,00,5

-0,5-1,0-1,5-2,0-2,5-3,0-3,5-4,0-4,5-5,0

cycles

dR

/R [

%]

Drift of 500 daisy chain

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Contact After 500 T-Cycles -65 …150°CContact After 500 T-Cycles -65 …150°C

Void-free joint

Alloying completed by a batch process

Only two phases (Cu and Cu3Sn), no barrier

No degradation, no re-cristallization

Morphology remains unchanged in comparison to the reference probe, beside a growing cross linking during the first cycles

Pitch 30µm

5 µm

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High Temperature Storage (HTS)High Temperature Storage (HTS)

140 chains of 500 standard contacts (15 x 15 µm², via 5 x 5 µm²) from LM to LM

Two storage temperatures175°C and 200°C

Temperature storage of daisy chain

t [h]1.0008006004002000

dR

/R [

%]

@ 1

00

00

µA

3,0

2,0

1,0

0,0

-1,0

-2,0

-3,0

-4,0

-5,0

175200

dR

/R [

%]

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Humidity Stress ResultsHumidity Stress Results

15 µm space between solder line and base plane, length 2.5 mm, height 12 µm, with underfiller

Resistance of daisy chain

group #543210

R [

Oh

m]

@ 1

00

00

µA

190

180

170

160

150

140

130

120

Leakage current

group #543210

I [A

] @

2V

1E-12

1E-11

1E-10

1E-09

1E-08

prestressprestress

UHAST

AC

Leakage current raises due to moisture uptake of the underfiller

Resistance remains unchainged

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Humidity Stress ResultsHumidity Stress Results

It will be a real concern for

small contact distances

for high pin counts

low power devices

Possible counter measures:

Use of underfiller with less moisture uptake

Interface w/o underfiller

Seal ring

The increase of the leakage current is a geometrical problem, when the insulation gap becomes more and more narrow.

This is a technology-independant phenomenon and can also be seen at micro-bumped probes.

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Despite a not yet optimized design, we succeeded in a

self-aligning process with an alignment accuracy of 1 µm (Initial placement 10 µm)

Self AlignmentSelf Alignment

Diagonal cut through a contact chain (steps 1 µm each)

Pitch 30µm

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Thank you for your attention !Thank you for your attention !

Many thanks to R. Tilgner / IFX for many valuable discussions !

1 h.hübner et al. mam 2006 grenoble infineon micro contacts with sub-30µm pitch for 3d...

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