1 richard b. brown cande workshop september 11-13, 2003 taos, new mexico richard b. brown michael s....

1 Richard B. BrownRichard B. Brown

CANDE Workshop

September 11-13, 2003Taos, New Mexico

Richard B. BrownMichael S. McCorquodale

brown, [email protected]

Analog Mixed Signal Low-Power Microcontrollers


Fundamental Changes in Microprocessor Market

• 1975 to 2000– Performance drove demand

• Desktop Processors – US market is saturating

– Performance is now adequate Less motivation to upgrade

– Performance is limited by power dissipation

– Cost is comparatively more important

• Servers and Video Processors– Performance is limited by power dissipation

• Portable Computers– Battery operation calls for lower power

• Where are the new markets?– Communications, Networking, and Microsystems


Generalized Microsystem

MEMS Analog Mixed-Signal Digital/VLSI

Antenna

MicroprocessorWirelessInterface

Clock

Sensor/Actuator Interface

Sensor

Actuator

BasebandModem

RFIC/RFMEMS

FE Tools

AHDLCustom IC Tools

VHDL Synthesis

Tools

AHDL Custom

RFIC Tools

DAC

ADC

MS-HDL Custom IC Tools

Technologies

Components

Design Tools

Electrical, Magnetic, Mechanical, Chemical, Optical, Biological


MS-8 Mixed-Signal Microcontroller

TWM Timers

MFT Timers

USART

Parallel I/O

Parallel I/O

Prog. Mem.

Data Mem.

CLK Manager

MACPro

cess

or

Co

re

Control

An

alo

g In

terf

ace

PGA

LPF

BandgapReference

12-bit

ADC

16-bitSlopeADC

Temp.Sensor

Ampero-metric

Interface

CapacitiveInterface

Voltage

K. Kraver, et al., Hilton Head Sensors and Actuators Conf., June 2000.


Programmable Gain Amplifier (PGA)

• Large input impedance, small output impedance

• Differential to single-ended conversion

• DC Level shifting

• Gain controlled by R1: 1, 11, 21, 31, 41, 51, 61 V/ V

R2

R3

R3

R3

R3

R1

R2

Vinp

Vinm

Vout

Vref

refinminpout VR

RVVV )

21)((

1

2


Ramp Generator

Potentiostat

Reference

Co

un

ter

Working

AmperometricCell

Rf

R2

R1

Vref

Vref

Vref

to mux

1

2

3

4


Capacitive Sensor Readout

• Programmable internal reference capacitor

• Four input sensor mux

Vref

V(Cs)

reset

CrefCs

Cf

reset

VA reff

refsAs V

C

CCVCV


Bottom-Up Design Methodology

Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)

Digital Specification Analog Specification Mechanical Specification

Custom Analog Design(SPICE)

Custom Mechanical Design(FE)

Synthesis/APR/Timing(Synthesizer)

Analog Physical Design(IC Tool)

DigitalLibrary

Tapeout

ProcessLibrary

Digital Design(HDL)

Dig

ita

l D

om

ain

An

alo

g D

om

ain

Me

ch

an

ica

l D

om

ain

Analog Macro Mechanical MacroDigital Macro

System Specification and Design Partition

Macro Automatic Place and Route(APR and IC Tool)

Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)

Digital Specification Analog Specification Mechanical Specification


Custom Mechanical Design(FE)

Synthesis/APR/Timing(Synthesizer)

Analog Physical Design(IC Tool)

DigitalLibrary

Tapeout

ProcessLibrary

Digital Design(HDL)

Dig

ita

l D

om

ain

An

alo

g D

om

ain

Me

ch

an

ica

l D

om

ain

Analog Macro Mechanical MacroDigital Macro

System Specification and Design Partition

Macro Automatic Place and Route(APR and IC Tool)


Bottom-Up Design Methodology Problems

• Time-consuming design iteration

• Cross-domain verification at top level only

• Time-consuming system level simulation, if it

is possible at all

• No opportunity for architectural studies


Mixed-Signal Microcontrollers

• Die size:– 3.8 x 4.1 mm2 (total)

– 3.0 x 2.6 mm2 (core)

• 0.35 m CMOS

• 303K transistors

• 103 I/O, 12 power

MS-8


Solid-State Sensor Advantages

3.5 x 4.8 mm

Sensicore• Sensor Arrays

• Convenience

• Accuracy

• Speed

• Shelf Life

• Cost

• Size

Potentiometric

ConductometricTemperatureAmperometric

ORP


Salinity

Water Parameters Test Selective Ligand / Exchanger Range – (Molar units)

Potassium K+ PU- Valinomycin 10-5 --10-1

Sodium Na+ PU- Calixarene 10-4 –10-1

Hydronium pH Tri-n-dodecylamine 5-9

Calcium Ca++ PU- ETH 1001 10-5–10-2

Chloride Cl - Quaternary Ammonium Poly 10-4 –10-1

Alkalinity HCO3- Differential Membrane pH 3x10-3 –10-1

Oxygen pO2 Silicone/Nafion® 0-300 mmHg

Ammonia NH3 Silicone- diff. pH or Ammonium ion 10-5 --10-1

Chlorine Cl2 Cellulose- HOCl reduction 1-10 ppm

Oxidation - Reduction

ORP Potential 0-1000 mV

Temperature RTD 5--50 oC

Conductivity Ti/Pt 0--2000 S/cm

Potable Water Testing


Sensors

• Amperometric– Three terminal sensors

– Voltage applied across reference and working electrodes

– Current measured at the auxiliary node

– Measured using cyclic voltammetry

Analyte peaks at varying voltages

Current depends on concentration

Dopamine Serontonin

Cyclic Voltamagrams


Neurological Sensor Array


Lead Detection by Pulse Voltammetry

E, V

-2.00E-07

-1.80E-07

-1.60E-07

-1.40E-07

-1.20E-07

-1.00E-07

-8.00E-08

-6.00E-08

-4.00E-08

-2.00E-08

0.00E+00

-0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

E, V

i, A

0 ppb

25 ppb

98 ppb

195 ppb

390 ppb


Arsenic Detection by Pulse Voltammetry

-1.10E-06

-9.00E-07

-7.00E-07

-5.00E-07

-3.00E-07

-1.00E-07

-1.00E-0700.10.20.30.40.50.60.7

Voltage, V

Cu

rre

nt,

A

0 ppb

5 ppb

10 ppb

15 ppb

20 ppb


Test Setup

GND3 V+12 V-12 V2.80 V0.20 V3 V

CLK

LabViewLabView

MS-8 Test BoardMS-8 Test Board

program

data

RS-232 bufferRS-232 buffer

resetreset


Potentiometric Sensor Demo


1.5

1.6

1.7

1.8

1.9

0 200 400 600 800 1000

Time (s)

Out

put V

olta

ge (V

)

1.5

1.6

1.7

1.8

1.9

-7 -6 -5 -4 -3 -2 -1 0

Concentration 10x (M)

Ou

tpu

t V

olt

ag

e (

V)

Potentiometric Sensor Results

CalibrationCurve forPotassium

Time Response:each step representsa decade jump inpotassium concentration

V = 0.0525Log(C) + 1.8211R2 = 0.9998

V = 0.0525Log(C) + 1.8211R2 = 0.9998

PGA gain = 1PGA gain = 110-6 10-5 10-410-3

10-210-1

1Molarity

Po

tass

ium

Po

tass

ium


Wireless Integrated MicroSystems (WIMS) ERC

Environmental Sensors Biomedical Implants

Cochlear Implant

preconcentrator

stackeddeep-RIE m-coiled column

distributed vacuum pump

column via

electroplatedchannel

bistable polymervalve gas

detector

pump via

1-2 cm

polar / nonpolar columns

5 mm

Medtronics

Deep Brain

Implants


Micropower Circuit Goals

• Acceptable Performance– ADC Speed and Accuracy

– Digital Processing Speed

• Very Low Power– Implantable

– Single Battery Cell

• Compatibility– Sensor Interfaces

– Wireless/Network Interfaces

– Software - C

• Flexibility – Efficiency Trade-off– Circuit Reusability

C

ADC

I/O

SensorInterface

TempSensor

Me

mo

ry

Power ManagementPower Management

RFBase-band


WIMS Architecture

• 16-bit Instruction Encoding– Most Instructions are two bytes

– Power-Efficient ISA

• 16-bit Datapath– 12-bit sensor data

• Loop Cache

• Static Logic

• Clocks– Gated

– Frequency Control

– Idle/Wake-Up

• Minimize Dynamic Power– Switching Activity

– Memory Accesses

• Advanced Process– Low Voltage

– Low Capacitance

• C Code Power Efficiency


Design Framework Requirements

• System level simulation support (HDL)

• Cross-domain verification – Analog and digital electronics, and MEMS

• Finite element simulation

• Active device and HDL simulation

• Parasitic extraction

• Co-simulation of primitives and HDL

• Timing verification

• HDL synthesis

• Automatic place and route


Design Tools Employed

• Cadence AMSSystem modeling, primitive/HDL co-simulation, and MEMS modeling

• Cadence SpectreAnalog device level simulation

• CoventorwareFinite element analysis

• Artisan Logic and Memory Libraries

• SynopsysDigital synthesis

• Cadence Silicon EnsembleAutomatic place and route

• Mentor Graphics CalibreDRC, ERC, and LVS


Tapeout

Top-Down Design Methodology

Cross- Domain Verification(Verilog with updated Verilog-A from achieved performance and/or Verilog and Verilog-A with Primitives)

Analog Model(Verilog-A)

Mechanical Model(Verilog-A)

Abstract System Model(Verilog-AMS: Verilog and Verilog-A)

DigitalLibrary

ProcessLibrary

Dig

ital

Do

mai

n

An

alo

g D

om

ain

Mec

han

ical

Do

mai

n

Cross - Domain Verification(Verilog with updated Verilog - A from parasitics and/or Verilog and Verilog-A with Primitives)

Cross-Domain Verification(Verilog with updated Verilog- A with interconnect parasitics )

Analog Macro

Parasitic Extraction(IC Tool)

Extraction, Timing(Timing Tool)

Digital Macro Mechanical Macro

Parasitic Extraction(IC Tool)


Mechanical Design(Finite Element)

Macro Place and Route, Layout Verification: DRC, LVS(APR and IC Tool)

Layout Parasitic Extraction (LPE) and Backannotation(IC Tool)

Synthesis/APR/Timing(Synthesis Tool)

Physical Design/Verif.(IC Tool)

Physical Design/Verif.(IC Tool)

Digital Model(Verilog)

Behavioral Verification(Verilog)

M. McCorquodale, DATE, March 2003.


• 0.18 m TSMC CMOS• 0.9 – 1.8V Power Supply• Components

– Input Buffers– Programmable Gain Amplifier– Second-Order Converter– Third-Order Comb Filter

• Features– Subthreshold Operation– Switched-Capacitor Circuits– Clock Doubling– Switched OpAmps– Body Biasing

Low-Voltage Analog to Digital Converter


WIMS Microcontroller Fabricated in TSMC 0.18m CMOS

8KB

RAM

8KB

RAM

8KB

RAM

8KB

RAM

C

O

R

E

I

OCLKAFE

WIMS Microcontroller

• TSMC 0.18 micron mixed-mode

• 16-bit 3-stage pipeline core

• Analog front end (AFE)

• MEMS-based clock generator

• 32 KB on-chip SRAM

• Timer and serial interfaces

• 1.5 million transistors

• 10.24mm2

• Estimated Power 24 mW @ 100 MHz

R. Senger, et al., DAC, June 2003.


Gaps and Solutions

Gaps in the Tool Suite

MEMS and analog simulation results not automatically extracted to behavioral model

Lack of physical verification for MEMS components

No synthesis capabilities for MEMS from topological or behavioral models

Inability to port designs between process technologies

Solutions & Future Direction

Custom and manual extraction: Requires design automation

Custom mod. of DRC/LVS decks: Requires support

No current solution: Requires design automation

No current solution: Requires design automation


Synthesis of MEMS Blocks• Specific Devices Supported

– Free-Free Beam Resonators– Clamped-Clamped Beam Resonators– Varactors, several configurations

• User Interface– Enter Process Characteristics– Enter Operational Specifications

• Proprietary Algorithms Generate Dimensions– Calls to MatLab and/or Mathematica

• Output– Plots– Electrical Model– Physical Design Parameters

• User Input for further Customization

• Generation of Physical Layout

• Output of Physical and Electrical Models


IP Repository

M. McCorquodale, et al., IFIP VLSI SoC 2003, Darmstadt, Dec. 2003.


Low-Power Microprocessor Status

• Top-Down Design Flow

• Low Dynamic and Static Power Dissipation– Reduced Switching– Scaled Processes, SOI– Subthreshold and Gate Leakage

• Processor Architecture– Efficient Instruction Set– Minimized Memory Accesses– Matched to Tasks– Dynamic Clock Scaling

• Power-Efficient Physical Design– Transistor Sizing– Datapaths

• Low-Power Analog– Subthreshold Operation– Bag of Tricks

• Power-Aware Software– C Compiler– Loop Cache


Conclusions

• Microsystem design methodologies are in their infancy

• Current methodologies reflect disparate nature of the technologies

• Top-down methodology leverages advances in mixed-signal design automation– Far superior verification

• Gaps in tool suites must be addressed for microsystems design– MEMS synthesis

– Better analog synthesis

– Automatic model extraction to AMS


Acknowledgements

• Ph.D. Students– Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger,

Matthew Guthaus

• CAD Vendors– Cadence, Synopsys, Coventor, Mentor, Artisan

• National Semiconductor

• MOSIS

• IBM

1 richard b. brown cande workshop september 11-13, 2003 taos, new mexico richard b. brown michael s....

Documents