12586603 siemens simatic s 7 300 400 function block diagram for s7300 and s7400

Preface, Contents

Product Overview 1

Configuration and Elements ofFunction Block Diagram 2

Addressing 3

Bit Logic Instructions 4

Timer Instructions 5

Counter Instructions 6

Integer Math Instructions 7

Floating-Point Math Instructions 8

Comparison Instructions 9

Move and ConversionInstructions 10

Word Logic Instructions 11

Shift and Rotate Instructions 12

Data Block Instructions 13

Jump Instructions 14

Status Bit Instructions 15

Program Control Instructions 16

Appendix

Glossary, Index

10/98

C79000-G7076-C566

Release 01

Function Block Diagram (FBD)for S7-300 and S7-400Programming

Reference Manual

SIMATIC S7

This reference manual is part of the documentationpackage with the order number:

6ES7810-4CA04-8BR0

iiFunction Block Diagram (FBD) for S7-300 and S7-400

C 9000 G 0 6 C 66 01

This manual contains notices which you should observe to ensure your own personal safety, as well as toprotect the product and connected equipment. These notices are highlighted in the manual by a warningtriangle and are marked as follows according to the level of danger:

!Danger

indicates that death, severe personal injury or substantial property damage will result if proper precautionsare not taken.

!Warning

indicates that death, severe personal injury or substantial property damage can result if proper precautionsare not taken.

!Caution

indicates that minor personal injury or property damage can result if proper precautions are not taken.

Note

draws your attention to particularly important information on the product, handling the product, or to aparticular part of the documentation.

Note the following:

!Warning

This device and its components may only be used for the applications described in the catalog or thetechnical description, and only in connection with devices or components from other manufacturers whichhave been approved or recommended by Siemens.

SIMATIC�, SIMATIC HMI� and SIMATIC NET� are registered trademarks of SIEMENSAG.

Third parties using for their own purposes any other names in this document which refer to trademarks mightinfringe upon the rights of the trademark owners.

We have checked the contents of this manual for agreement with thehardware and software described. Since deviations cannot be precludedentirely, we cannot guarantee full agreement. However, the data in thismanual are reviewed regularly and any necessary corrections included insubsequent editions. Suggestions for improvement are welcomed.

� Siemens AG 1998Technical data subject to change.

�� Copyright � Siemen s AG 1998 All rights reserved

The reproduction, transmission or use of this document or its contents isnot permitted without express written authority. Offenders will be liable fordamages. All rights, including rights created by patent grant or registrationof a utility model or design, are reserved.

Siemens AGBereich Automatisierungs- und AntriebstechnikGeschaeftsgebiet Industrie-AutomatisierungssystemePostfach 4848, D-90327 Nuernberg

Siemens Aktiengesellschaft C79000-G7076-C566

Safety Guidelines

Correct Usage

Trademarks

iiiFunction Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

Preface

This manual is your guide to creating user programs in the Function BlockDiagram (FBD) programming language.

This manual also includes a reference section that describes the syntax andfunctions of the language elements of Function Block Diagram.

The manual is intended for S7 programmers, operators, andmaintenance/service personnel. A working knowledge of automationprocedures is essential.

This manual is valid for release 5.0 of the STEP 7 programming softwarepackage.

FBD corresponds to the “Function Block Diagram” language defined in theInternational Electrotechnical Commission’s standard IEC 1131-3. Forfurther details, refer to the table of standards in the STEP 7 fileNORM_TBL.WRI.

Purpose of theManual

Audience

Where is thisManual Valid?

Which StandardsDoes the SoftwareComply With?

ivFunction Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01

To use this Function Block Diagram manual effectively, you should alreadybe familiar with the theory behind S7 programs which is documented in theonline help for STEP 7. The language packages also use the STEP 7 standardsoftware, so you should be familiar with handling this software and have readthe accompanying documentation.

Documentation Purpose Order Number

STEP 7 Basic Information with

� Working with STEP 7 V5.0, Getting StartedManual

� Programming with STEP 7 V5.0

� Configuring Hardware and CommunicationConnections, STEP 7 V5.0

� From S5 to S7, Converter Manual

Basic information for technicalpersonnel describing the methods ofimplementing control tasks withSTEP 7 and the S7-300/400programmable controllers.

6ES7810-4CA04-8BA0

STEP 7 Reference with

� Ladder Logic (LAD)/Function BlockDiagram (FBD)/Statement List (STL) forS7-300/400 manuals

� Standard and System Functions forS7-300/400

Provides reference information anddescribes the programminglanguages LAD, FBD and STL andstandard and system functionsextending the scope of the STEP 7basic information.

6ES7810-4CA04-8BA0

Online Helps Purpose Order Number

Help on STEP 7 Basic information on programmingand configuring hardware withSTEP 7 in the form of an onlinehelp.

Part of the STEP 7Standard software.

Reference helps on STL/LAD/FBD

Reference help on SFBs/SFCs

Reference help on Organization Blocks

Context-sensitive referenceinformation.

Part of the STEP 7Standard software.

You can display the online help in the following ways:

� Context-sensitive help about the selected object with the menu commandHelp > Context-Sensitive Help, with the F1 function key, or by clickingthe question mark symbol in the toolbar.

� Help on STEP 7 via the menu command Help > Contents.

References to other documentation are indicated by reference numbers inslashes /.../. Using these numbers, you can check the exact title in theReferences section at the end of the manual.

Requirements

Accessing theOnline Help

References

Preface

vFunction Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

The SIMATIC Customer Support team offers you substantial additionalinformation about SIMATIC products via its online services:

� General current information can be obtained:

– on the Internet underhttp://www.ad.siemens.de/simatic/html_00/simatic

– via the Fax-Polling number 08765-93 02 77 95 00

� Current product information leaflets and downloads which you may finduseful are available:

– on the Internet under http://www.ad.siemens.de/support/html_00/

– via the Bulletin Board System (BBS) in Nuremberg (SIMATICCustomer Support Mailbox) under the number +49 (911) 895-7100.

To dial the mailbox, use a modem with up to V.34 (28.8 Kbps) withthe following parameter settings: 8, N, 1, ANSI; or dial via ISDN(x.75, 64 Kbps).

If you have other questions, please contact the Siemens representative in yourarea. The addresses are listed, for example, in catalogs and in Compuserve(go autforum ).

Our SIMATIC Basic Hotline is also ready to help:

� in Nuremberg, Germany

– Monday to Friday 07:00 to 17:00 (local time): telephone:+49 (911) 895–7000

– or E-mail: [email protected]

� in Johnson City (TN), USA

– Monday to Friday 08:00 to 17:00 (local time): telephone:+1 423 461–2522


� in Singapore

– Monday to Friday 08:30 to 17:30 (local time): telephone:+65 740–7000


The SIMATIC Premium Hotline is available round the clock worldwidewith the SIMATIC card (telephone: +49 (911) 895-7777).

Siemens offers a number of training courses to introduce you to the SIMATICS7 automation system. Please contact your regional training center or thecentral training center in Nuremberg, Germany for details:Telephone: +49 (911) 895-3154.

SIMATIC CustomerSupport OnlineServices

AdditionalAssistance

Courses forSIMATIC Products

Preface

viFunction Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01

To help us to provide the best possible documentation for you and futureSTEP 7 users, we need your support. If you have any comments orsuggestions relating to this manual or the online help, please complete thequestionnaire at the end of the manual and send it to the address shown.Please include your own personal rating of the documentation.

Questionnaires onthe Manual andOnline Help

Preface

viiFunction Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

Contents

Preface iii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Product Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Configuration and Elements of Function Block Diagram 2-1. . . . . . . . . . . . . . . . . . .

2.1 Elements and Box Structure 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Boolean Logic and Truth Tables 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Significance of the CPU Registers in Statements 2-9. . . . . . . . . . . . . . . . . . . .

3 Addressing 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Types of Addresses 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Bit Logic Instructions 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Overview 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 AND Logic Operation 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 OR Logic Operation 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 AND-before-OR Logic Operation and OR-before-AND Logic Operation 4-5.

4.5 Exclusive OR Logic Operation 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Insert Binary Input 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Negate Binary Input 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 Assign 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9 Midline Output 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 Save RLO to BR Memory 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11 Set Output 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12 Reset Output 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.13 Set Counter Value 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14 Up Counter Instruction 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15 Down Counter Instruction 4-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16 Pulse Timer Instruction 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.17 Extended Pulse Timer Instruction 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viiiFunction Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01

4.18 On-Delay Timer Instruction 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.19 Retentive On-Delay Timer Instruction 4-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.20 Off-Delay Timer Instruction 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.21 Positive RLO Edge Detection 4-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.22 Negative RLO Edge Detection 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23 Address Positive Edge Detection 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.24 Address Negative Edge Detection 4-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.25 Set_Reset Flip Flop 4-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.26 Reset_Set Flip Flop 4-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Timer Instructions 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Memory Areas and Components of a Timer 5-2. . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Choosing the Right Timer 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Pulse S5 Timer 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Extended Pulse S5 Timer 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 On-Delay S5 Timer 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Retentive On-Delay S5 Timer 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Off-Delay S5 Timer 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Counter Instructions 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Memory Address and Components of a Counter 6-2. . . . . . . . . . . . . . . . . . . . .

6.2 Up-Down Counter 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Up Counter 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Down Counter 6-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Integer Math Instructions 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Add Integer 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 Add Double Integer 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Subtract Integer 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Subtract Double Integer 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Multiply Integer 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 Multiply Double Integer 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 Divide Integer 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8 Divide Double Integer 7-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.9 Return Fraction Double Integer 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.10 Evaluating the Bits of the Status Word with Integer Math Instructions 7-11. . .

Contents

ixFunction Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

8 Floating-Point Math Instructions 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Overview 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 Add Real 8-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Subtract Real 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 Multiply Real 8-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5 Divide Real 8-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6 Evaluating the Bits of the Status Word with Floating-Point Instructions 8-7. .

8.7 Forming the Absolute Value of a Floating-Point Number 8-8. . . . . . . . . . . . . .

8.8 Forming the Square (SQR) of a Floating-Point Number 8-9. . . . . . . . . . . . . . .

8.9 Forming the Square Root (SQRT) of a Floating-Point Number 8-10. . . . . . . . .

8.10 Forming the Natural Logarithm of a Floating-Point Number 8-11. . . . . . . . . . . .

8.11 Forming the Exponential Value of a Floating-Point Number 8-12. . . . . . . . . . . .

8.12 Forming Trigonometric Functions of Angles as Floating-Point Numbers 8-13.

9 Comparison Instructions 9-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 Compare Integer 9-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2 Compare Double Integer 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3 Compare Real 9-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Move and Conversion Instructions 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1 Assign Value 10-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2 BCD to Integer 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3 Integer to BCD 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4 Integer to Double Integer 10-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.5 BCD to Double Integer 10-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.6 Double Integer to BCD 10-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.7 Double Integer to Real 10-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.8 Ones Complement Integer 10-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.9 Ones Complement Double Integer 10-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.10 Twos Complement Integer 10-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.11 Twos Complement Double Integer 10-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.12 Negate Real Number 10-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.13 Round to Double Integer 10-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.14 Truncate Double Integer Part 10-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.15 Ceiling 10-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.16 Floor 10-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xFunction Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01

11 Word Logic Instructions 11-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1 Overview 11-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 (Word) AND Word 11-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3 (Word) AND Double Word 11-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.4 (Word) OR Word 11-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.5 (Word) OR Double Word 11-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6 (Word) Exclusive OR Word 11-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.7 (Word) Exclusive OR Double Word 11-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 Shift and Rotate Instructions 12-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1 Shift Instructions 12-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2 Rotate Instructions 12-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 Data Block Instructions 13-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1 Open Data Block 13-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14 Jump Instructions 14-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.1 Overview 14-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.2 Unconditional Jump in a Block 14-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.3 Conditional Jump in a Block 14-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.4 Jump-If-Not 14-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.5 Jump Label 14-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15 Status Bit Instructions 15-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.1 Overview 15-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.2 Exception Bit Binary Result 15-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.3 Result Bits 15-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.4 Exception Bit Unordered 15-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.5 Exception Bit Overflow 15-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.6 Exception Bit Overflow Stored 15-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16 Program Control Instructions 16-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.1 Calling an FC/SFC without Parameters 16-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.2 Calling an FB, FC, SFB, SFC, and Multiple Instances 16-4. . . . . . . . . . . . . . . .

16.3 Return 16-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.4 Master Control Relay Instructions 16-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.5 Master Control Relay Activate/Deactivate 16-10. . . . . . . . . . . . . . . . . . . . . . . . . . .

16.6 Master Control Relay On/Off 16-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Alphabetical Lists of Instructions A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1 List of Instructions with International Names A-2. . . . . . . . . . . . . . . . . . . . . . . .

Contents

xiFunction Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

A.2 List of Instructions with International (English) Names and German Equivalents A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.3 List of Instructions with German SIMATIC Names A-10. . . . . . . . . . . . . . . . . . . .

A.4 List of Instructions with German Names and International (English) Equivalents A-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B Programming Examples B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.1 Overview B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.2 Bit Logic Instructions B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3 Timer Instructions B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.4 Counter and Comparison Instructions B-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.5 Integer Math Instructions B-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.6 Word Logic Instructions B-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C References C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Glossary Glossary-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Index Index-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xiiFunction Block Diagram (FBD) for S7-300 and S7-400

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Contents

1-1Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

Product Overview

FBD stands for Function Block Diagram. FBD is a graphic programminglanguage and uses logic boxes familiar from Boolean algebra to representlogic. Complex functions (for example math functions) can also berepresented directly connected to the logic boxes.

The Function Block Diagram programming language has all the elementsnecessary for creating a complete user program. It contains a wide range ofinstructions. These include the various basic instructions and a wide range ofaddresses and address types. Functions and function blocks allow you tostructure your FBD program clearly.

The FBD programming package is an integral part of the STEP 7 StandardSoftware. This means that following the installation of your STEP 7 software,all the editor functions, compiler functions, and test/debug functions for FBDare available to you.

Using FBD, you can create your own user program. With the IncrementalEditor, the input of the local data structure is made easier with the help oftable editors.

There are three programming languages in the standard software, STL, FBD,and LAD. You can switch from one language to the other almost withoutrestriction and choose the most suitable language for the particular block youare programming.

If you write programs in LAD or FBD, you can always switch over to theSTL representation. If you convert LAD programs into FBD programs andvice versa, program elements that cannot be represented in the destinationlanguage are displayed in STL.

What is FBD?

The FBDProgrammingLanguage

The ProgrammingPackage

1

1-2Function Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01


Configuration and Elements of FunctionBlock Diagram

Section Description Page

2.1 Elements and Box Structure 2-2

2.2 Boolean Logic and Truth Tables 2-6

2.3 Significance of the CPU Registers in Statements 2-9

ChapterOverview

2


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2.1 Elements and Box Structure

FBD instructions consist of elements and boxes that are connectedgraphically to form networks. The elements and boxes can be classified inthe following groups:

STEP 7 represents some of the FBD instructions as individual elements thatdo not require addresses or parameters (see Table 2-1).

Table 2-1 FBD Instruction as an Element without Address or Parameters

Element Description Section in this Manual

Negate binary input 4.7

STEP 7 represents some of the FBD instructions as boxes for which you mustspecify an address (see Table 2-2). For more detailed information aboutaddressing, refer to Chapter 3.

Table 2-2 FBD Instruction as Box with Address


<Address>

=Assign 4.8

STEP 7 represents some of the FBD instructions as boxes for which youspecify an address and a value (for example a timer or counter value, seeTable 2-3).

For more detailed information about addressing, refer to Chapter 3.

Table 2-3 FBD Instruction as a Box with Address and Value


<Address>>

TV

SS

<Time value>

Retentive on-delay timer 4.19

FBD Instructions

Instructions asElements

Instruction as aBox with Address

Instruction as aBox with Addressand Value

Configuration and Elements of Function Block Diagram


STEP 7 represents some of the FBD instructions as boxes with inputs andoutputs (see Table 2-4). The inputs are on the left of the box and the outputson the right. You specify the input parameters and some of the outputparameters. Most outputs are provided by the STEP 7 software. To assignparameters, you must use the specific notation of the data types.

The parameters of the Enable input (EN) and the Enable output (ENO) aredescribed below. For further information about input and output parameters,refer to the descriptions of the individual instructions in this manual.

Table 2-4 FBD Operation as a Box with Inputs and Outputs

Box Description Section in this Manual

DIV_R

IN1

EN

IN2

OUT

ENO

Divide real 8.5

If the Enable input (EN) of an FBD box is activated, the box carries out aspecific function. If the function is executed by the box without errors, theEnable output (ENO) is activated. The parameters EN and ENO of an FBDbox are of the BOOL data type and can be located in the I, Q, M, D, or Lmemory areas (see Table 2-5 and 2-6).

How EN and ENO function is described below:

� If EN is not activated (its signal state is 0), the box does not execute itsfunction and ENO is not activated (its signal state is also 0).

� If EN is activated (its signal state is 1) and if the box executes its functionwithout errors, ENO is also activated (its signal state is also 1).

� If EN is activated (its signal state is 1) and if an error occurs during theexecution of the function, ENO is not activated (its signal state remains0).

The majority of the addresses in FBD refer to memory areas. The followingtable shows the types and their functions.

Instruction as Boxwith Parameters

Enable Input andEnable OutputParameters

Memory Areas andFunctions



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Table 2-5 Memory Areas and Their Functions

Access to Area

Name of Area Function of Area Using Units of theFollowing Size:

Abbr.

Process inputimage

At the beginning of the scan cycle, the operating system readsthe inputs from the process and records the values in this area.The program uses these values when it is running cyclically.

Input bitInput byteInput wordInput double word

IIBIWID

Process outputimage

During the scan cycle, the program calculates output values andenters them in this area. At the end of the scan cycle, theoperating system reads the calculated output values from thisarea and sends them to the process outputs.

Output bitOutput byteOutput wordOutput double word

QQBQWQD

Bit memory This area provides memory space for interim results calculatedin the program.

Memory bitMemory byteMemory wordMemory double word

MMBMWMD

I/Os

Ext. inputs

Using this area, your program has direct access to input andoutput modules (peripheral inputs and outputs).

Peripheral input bytePeripheral input wordPeripheral input doubleword

PIBPIWPID

I/Os:

Ext. outputs

Peripheral output bytePeripheral output wordPeripheral output doubleword

PQBPQWPQD

Timers Timers are function elements in FBD. This area providesmemory space for timer cells. In this area, the clock timingaccesses the timer cells and updates them by decrementing thetimer value. Timer operations access these timer cells.

Timer (T) T

Counters Counters are function elements in FBD. This area providesmemory space for counters. Count instructions access the cellsin this area.

Counter (C) C

Data block This area contains data that can be accessed from within anyblock. If it is necessary to open two data blocks at the sametime, you can open one with the “OPN DB” instruction and theother with the “OPN DI” instruction. The notation of theaddresses, for example L DBWi and L DIWi identifies the datablock to be accessed.Although you can access any data block with the “OPN DI”i i hi i i i i l d i d

Data block opened withthe “OPN DB”instruction:Data bitData byteData wordData double word

DBXDBBDBWDBD

instruction, this instruction is mainly used to open instance datablocks that are assigned to function blocks (FBs) and systemfunction blocks (SFBs). For more detailed information aboutFBs and SFBs, refer to the STEP 7 Online Help.

Data block opened withthe “OPN DI”instruction:Data bitData byteData wordData double word

DIXDIBDIWDID

Local data This area contains temporary local data belonging to a logicblock (FB or FC). This type of data is also called dynamic localdata. This area is used as a buffer. When the logic block isclosed, the data are lost. These data are located in the local datastack (L stack).

Temporary local data bitTemporary local databyteTemporary local datawordTemporary local datadouble word

LLB

LW

LD



Table 2-6 lists the maximum address ranges for the various memory areas.For more detailed information about the address ranges on your CPU, refer tothe corresponding manual /70/ or /101/.

Table 2-6 Memory Areas and Their Address Ranges

Name of AreaAccess Using

M i Add RName of AreaUnits of the Following Sizes: Abbr. Maximum Address Range

Process input imageInput bitInput byteInput wordInput double word

IIBIWID

0.0 to 65 535.70 to 65 5350 to 65 5340 to 65 532

Process outputimage

Output bitOutput byteOutput wordOutput double word

QQBQWQD

0.0 to 65 535.70 to 65 5350 to 65 5340 to 65 532

Bit memory Memory bitMemory byteMemory wordMemory double word

MMBMWMD

0.0 to 255.70 to 2550 to 2540 to 252

I/Os:External inputs

Peripheral input bytePeripheral input wordPeripheral input double word

PIBPIWPID

0 to 65 5350 to 65 5340 to 65 532

I/Os:External outputs

Peripheral output bytePeripheral output wordPeripheral output double word

PQBPQWPQD

0 to 65 5350 to 65 5340 to 65 532

Timers Timer T 0 to 255

Counters Counter C 0 to 255

Data block Data block opened with the DB [OPN]instruction

Data bit in the data blockData byteData wordData double word

DBXDBBDBWDBD

0.0 to 65 535.70 to 65 5350 to 65 5340 to 65 532

Data block opened with the DI [OPN] instruction

Data bit in the instance DBData byteData wordData double word

DIXDIBDIWDID

0.0 to 65 535.70 to 65 5350 to 65 5340 to 65 532

Local data 1) Temporary local data bitTemporary local data byteTemporary local data wordTemporary local data double word

LLBLWLD

0.0 to 65 535.70 to 65 5350 to 65 5340 to 65 532

1) With FBD instructions, you can only use an address in the L memory area when you declare it as VAR_TEMP in the variable declaration table.



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2.2 Boolean Logic and Truth Tables

The FBD programming language is based on the binary logic of Booleanalgebra in which variables can adopt the values “true” (1) or “false” (0).

Each logic instruction checks the signal state of a variable for 1 (true,satisfied) or 0 (false, not satisfied) and then produces a result. The instructionthen either saves the result or uses it to perform a Boolean logic operation.The result of the logic operation is known as the RLO.

To represent the logic, the logic boxes known from Boolean algebra are used.

The results of the logic instructions for all possible combinations of logicalvariables are listed in truth tables.

The rules of Boolean logic are illustrated below based on the AND, OR, andexclusive OR logic operations.

In an AND logic operation, the signal states of two or more specifiedaddresses are checked. If the signal state of the address is 1 the condition issatisfied and the instruction produces the result 1. If the signal state of theaddress is 0, the condition is not satisfied and the operation produces theresult 0.

Figure 2-1 illustrates an AND logic operation in the FBD programminglanguage.

I1.0&

I1.1 =

Q4.0The condition is satisfied when thesignal state is 1 at inputs I1.0 ANDI1.1.

Figure 2-1 AND Logic Operation in FBD

The possible results of an AND logic operation can be represented in a truthtable. Here, 1 means “satisfied” and 0 means “not satisfied”. The possiblelogic instructions and their results are shown in Table 2-7.

Table 2-7 AND Truth Table

If the result of the signalstate check at address I1.0

is as below

and the result of the signalstate check at address I1.1

is as below

the result of the logic instruc-tion is as follows:

1 1 1

0 1 0

1 0 0

0 0 0

Boolean Logic

AND LogicOperation



In an OR logic operation, the signal states of two or more specified addressesare checked. If the signal state of one of the addresses is 1, the condition issatisfied and the instruction provides the result 1. If the signal state of alladdresses is 0, the condition is not satisfied and the instruction produces theresult 0.

Figure 2-2 shows an OR logic operation in the FBD programming language.

I1.0

I1.1 =

Q4.0The condition is satisfied when thesignal state is 1 at inputs I1.0 ORI1.1.

>=1

Figure 2-2 OR Logic Operation in FBD

The possible results of an OR logic operation can be shown in a truth table.Here, 1 means “satisfied” and 0 means “not satisfied”. The possible logicoperations and their results are shown in Table 2-8.

Table 2-8 OR Truth Table

If the result of the sig-nal state check at ad-dress I1.0 is as below

and the result of thesignal state check at

address I1.1 is as below

the result of the logic instructionis as follows:

1 0 1

0 1 1

1 1 1

0 0 0

In an exclusive OR logic operation, the signal states of two or more specifiedaddresses are checked. If the signal state of one of the addresses is 1 thecondition is satisfied and the instruction provides the result 1. If the signalstate of all addresses is 0 or 1, the condition is not satisfied and theinstruction produces the result 0.

Figure 2-3 shows an exclusive OR logic operation in the FBD programminglanguage.

I1.0

I1.1 =

Q4.0The condition is satisfied when thesignal state is 1 at input I1.0 OR atinput I1.1 exclusively (i.e. not atboth).

XOR

Figure 2-3 Exclusive OR Logic Operation in FBD

OR LogicOperation

Exclusive ORLogic Operation



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The possible results of an exclusive OR logic operation can be represented ina truth table. Here, 1 means “satisfied” and 0 means “not satisfied”. Thepossible logic operations and their results are shown in Table 2-9.

Table 2-9 Exclusive OR Truth Table

If the result of thesignal state check at


and the result of thesignal state check at


the result of the logic instructionis as follows:

1 0 1

0 1 1

1 1 0

0 0 0



2.3 Significance of the CPU Registers in Statements

Registers help the CPU perform logic, math, shift, or conversion instructions.These registers are described below.

The accumulators are general-purpose registers that you use to process bytes,words, and double-words. The accumulators are 32-bits wide.

0781516232431

Accumulator (1 or 2)Low wordHigh word

Low byteHigh byteLow byteHigh byte

Figure 2-4 Areas of an Accumulator

The status word contains bits that you can reference in the address of bitlogic instructions. The following sections explain the significance of bits0 through 8.

28215... ...29 2427 26 25 2023 22 21

BR OSCC1 CC0 OV FCOR STA RLO

Figure 2-5 Structure of the Status Word

Value Meaning

0 Sets the signal state to 0

1 Sets the signal state to 1

x Changes the state

– State remains unchanged

Explanation

Accumulators

Status Word

Changes in theBits of the StatusWord



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Bit 0 of the status word is called the first-check bit (FC bit, see Figure 2-5).At the start of an FBD network, the signal state of the FC bit is always 0,unless the previous network ended with the SAVE box

Each logic instruction checks the signal state of the FC bit as well as thesignal state of the contact that the instruction addresses. The signal state ofthe FC bit determines the sequence of a logic string. If the FC bit is 0 (at thestart of an FBD network), the instruction stores the result in the result oflogic operation bit (RLO) of the status word and sets the FC bit to 1. This isknown as the first check. The 1 or 0 that is set in the RLO bit after the firstcheck is then referred to as the result of first check.

If the signal state of the FC bit is 1, an instruction then combines the result ofits signal state check at the addressed contact with the RLO formed at theaddressed contact after the first check, and sets the result in the RLO bit.

A logic string made up of FBD instructions always ends with an outputinstruction (for example set output, reset output, assign) or with a jumpinstruction dependent on the result of the logic operation (RLO). Theseinstructions reset the FC bit to 0.

Bit 1 of the status word is called the result of logic operation bit (RLO bit,see Figure 2-5). This bit stores the result of a string of logic instructions orcompare instructions. The signal state of the RLO bit provides informationabout signal flow.

The first instruction in an FBD network checks the signal state of an addressand produces a result of 1 or 0. The instruction enters the result of this signalstate in the RLO bit. The second instruction in a string of logic operationsalso checks the signal state of an address and produces a result. Theinstruction now combines this result with the value of the RLO bit of thestatus word according to the rules of Boolean logic (see First Check above).The result of the logic operation is entered in the RLO bit of the status wordand replaces the previous value in the RLO bit. Each subsequent instructionin the string of logic operations combines two values: the result of the signalcheck at the specified address and the current RLO.

You can, for example, assign the state of a bit memory location to the RLOduring a first check using a Boolean logic operation or trigger a jumpinstruction.

First Check

Result of LogicOperation



Bit 2 of the status word is called the status bit (STA bit, see Figure 2-5). Thestatus bit stores the value of a bit that is referenced. The status of a logicinstruction that reads memory is always the same as the value of the bit thatthis instruction checks (the bit on which it performs its logic operation). Thestatus of a bit instruction that writes to memory (Set Output, Reset Output, orAssign) is the same as the value of the bit to which the instruction writes. Ifno writing takes place, the value is the same as the value of the bit that theinstruction references. The status bit has no significance for bit instructionsthat do not access memory. These instructions set the status bit to 1 (STA=1).The status bit is not checked by an instruction. It is interpreted duringprogram test (program status) only.

Bit 3 of the status word is called the OR bit (see Figure 2-5). The OR bit isrequired to execute an AND before OR logic operation. An AND logicoperation can contain the instructions AND input and AND NOT input. TheOR bit indicates to the instructions that a previously executed AND logicoperation produced the value 1 so that the result of the OR logic operationhas already been determined. Any other bit-processing instruction resets theOR bit.

Bit 5 of the status word is called the overflow bit (OV bit, see Figure 2-5).The OV bit indicates an error. It is set by a math instruction or a comparefloating-point numbers instruction after an error has occurred (overflow,illegal instruction, illegal floating-point number). The bit is set or resetaccording to the result of the math or compare instruction (error).

Bit 4 of the status word is called the store overflow bit (OS bit, see Figure2-5). The OS bit is set together with the OV bit when an error occurs. Sincethe OS bit is unchanged when math instructions are executed without errors(in contrast to the OV bit), this indicates whether or not an error occurred inone of the previously executed instructions. The following instructions resetthe OS bit: JOS (jump if stored overflow bit = 1, must be programmed inSTL), block calls and block end statements.

Bits 7 and 6 of the status word are called condition code 1 and conditioncode 0 (CC1 and CC0, see Figure 2-5). The CC1 and CC0 bits provideinformation about the following results or bits:

� Result of a math instruction

� Result of a compare instruction

� Result of a digital instruction

� Bits that have been shifted out of the address by a shift or rotateinstruction.

Tables 2-10 to 2-15 list the meaning of CC1 and CC0 after your program hasexecuted certain instructions.

Status Bit

OR Bit

Overflow Bit

Stored OverflowBit

CC1 and CC0



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Table 2-10 CC1 and CC0 after Math Instructions, without Overflow

CC1 CC0 Explanation

0 0 Result = 0

0 1 Result < 0

1 0 Result > 0

Table 2-11 CC1 and CC0 after Integer Math Instructions, with Overflow

CC1 CC0 Explanation

0 0 Negative range overflow in Add Integer and Add Double Integer

0 1

Negative range overflow in Multiply Integer and MultiplyDouble IntegerPositive range overflow in Add Integer, Subtract Integer, AddDouble Integer, Subtract Double Integer, Twos ComplementInteger, and Twos Complement Double Integer

1 0

Positive range overflow in Multiply Integer and Multiply DoubleInteger, Divide Integer, and Divide Double IntegerNegative range overflow in Add Integer, Subtract Integer, AddDouble Integer, and Subtract Double Integer

1 1Division by 0 in Divide Integer, Divide Double Integer, andReturn Fraction Double Integer

Table 2-12 CC1 and CC0 after Floating-Point Math Instructions, with Overflow

CC1 CC0 Explanation

0 0 Gradual underflow

0 1 Negative range overflow

1 0 Positive range overflow

1 1 Not a valid floating-point number



Table 2-13 CC1 and CC0 after Comparison Instructions

CC1 CC0 Explanation

0 0 IN2 = IN1

0 1 IN2 < IN1

1 0 IN2 > IN1

1 1 IN1 or IN2 is not a valid floating-point number

Table 2-14 CC1 and CC0 after Shift and Rotate Instructions

CC1 CC0 Explanation

0 0 Bit shifted out last = 0

1 0 Bit shifted out last = 1

Table 2-15 CC1 and CC0 after Word Logic Instructions

CC1 CC0 Explanation

0 0 Result = 0

1 0 Result <> 0

Bit 8 of the status word is called the binary result bit (BR bit, see Figure 2-5).The BR bit forms a link between the processing of bits and words. This bit isan efficient method with which you can interpret the result of a wordinstruction as a binary result and include this result in a binary string of logicoperations. The BR bit represents an internal memory bit in which the RLOcan be saved prior to a word instruction that changes the RLO so that the oldRLO is available again after the operation when the interrupted series of bitinstructions is resumed.

With the BR bit, you can, for example, program a function block (FB) or afunction (FC) in Statement List (STL) and call the FB or FC in FBD.

If you write a function block or a function that you want to call in FBD,regardless of whether you write the FB or FC in STL or FBD, you must takeinto account the BR bit. The BR bit corresponds to the Enable output (ENO)of an FBD box. You save the RLO in the BR bit using the SAVE instruction(in STL) or with the SAVE FBD box according to the following criteria:

� Save an RLO of 1 in the BR bit when the FB or FC is processed withouterrors.

� Save an RLO of 0 in the BR bit if an error occurs during the processing ofan FB or FC.

Program these instructions at the end of the FB or FC so that they are the lastinstructions executed in the block.

Binary Result Bit



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!Warning

The BR bit can be reset to 0 unintentionally.

When you write FBs or FCs in FBD and do not handle the BR bit asdescribed above, an FB or FC might overwrite the BR bit of another FB orFC.

To avoid this problem, save the RLO at the end of each FB or FC asdescribed above.

The Enable input (EN) and Enable output (ENO) parameters of an FBD boxfunction as explained below:

� If EN is not activated (its signal state is 0), the box does not execute itsfunction and ENO is not activated (it also has a signal state of 0).

� If EN is activated (its signal state is 1) and the box executes its functionwithout errors, ENO is also activated (its signal state is also 1).

� If EN is activated (its signal state is 1) and an error occurs while thefunction is being executed, ENO is not activated (its signal state is 0).

When you call a system function block (SFB) or a system function (SFC) inyour program, the SFB or SFC indicates whether or not the CPU executed thefunction without errors by setting the signal state of the BR bit:

� If an error occurred during execution, the BR bit is set to 0.

� If the function was executed without errors, the BR bit is 1.

Meaning ofEN/ENO



Addressing


3.1 Overview 3-2

3.2 Types of Addresses 3-4

ChapterOverview

3


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3.1 Overview

Many FBD instructions operate with one or more addresses. The addressspecifies a constant or a location at which the instruction finds a variablewhich it uses to perform a logic operation. This location can be a bit, byte,word, or double word.

Examples of possible addresses are as follows:

� A constant, the value of a timer or counter, or an ASCII character string

� A bit in the status word of the programmable controller

� A data block and a location within the data block area

The following types of addressing are available:

� Immediate addressing (specifying a constant as the address)

� Direct addressing (specifying a variable as the address)

Figure 3-1 shows an example of immediate and direct addressing.

The function of the box is to compare two input parameters (in this case, two16-bit integers) to see if the first input is less than or equal to the second. Theconstant 50 is entered as input parameter IN1. Memory word MW200, alocation in memory, is entered as input parameter IN2.

Because the constant 50 in the example is the actual value with which IN1 ofthe box will work, 50 is an immediate address of the instruction box. BecauseMW200 points to a location in memory where there is another value withwhich IN2 of the box will work, MW200 is a direct address. MW200 is alocation, not the actual value itself.

CMP

IN1

<= I

50

MW200 IN2

Figure 3-1 Immediate and Direct Addressing

What isAddressing?

Immediate andDirect Addressing

Addressing


Table 3-1 Constant Formats for Immediate Addressing Using Addresses of Elementary Data Types

Type andDescription

Size inBits

Format Options Range and Number Notation (Lowest Value to Highest Value)

Example

BOOL(Bit)

1 Boolean Text TRUE/FALSE TRUE

BYTE(Byte)

8 Hexadecimal B#16#0 to B#16#FF B#16#10byte#16#10

WORD(Word)

16 Binary

Hexadecimal

BCDUnsigned decimal

2#0 to2#1111_1111_1111_1111W#16#0 to W#16#FFFF

C#0 to C#999B#(0,0) to B#(255,255)

2#0001_0000_0000_0000

W#16#1000word16#1000C#998B#(10,20)byte#(10,20)

DWORD(Doubleword)

32 Binary

HexadecimalUnsigned decimal

2#0 to2#1111_1111_1111_1111_1111_1111_1111_1111DW#16#0000_0000 toDW#16#FFFF_FFFFB#(0,0,0,0) toB#(255,255,255,255)

2#1000_0001_0001_1000_1011_1011_0111_1111

DW#16#00A2_1234dword#16#00A2_1234B#(1,14,100,120)byte#(1,14,100,120)

INT(Integer)

16 Signed decimal -32768 to 32767 1

DINT(Doubleinteger)

32 Signed decimal L#-2147483648 to L#2147483647 L#1

REAL(Floatingpoint)

32 IEEEfloating point

Upper limit: ±3.402823e+38Lower limit: ±1.175495e-38 )

1.234567e+13

S5TIME(SIMATICtime)

16 S5 Time in 10-ms units (asdefault value)

S5T#0H_0M_0S_10MS toS5T#2H_46M_30S_0MS andS5T#0H_0M_0S_0MS

S5T#0H_1M_0S_0MSS5TIME#0H_1M_0S_0MS

TIME(IEC time)

32 IEC time in 1-msunits, signedinteger

T#-24D_20H_31M_23S_648MS toT#24D_20H_31M_23S_647MS

T#0D_1H_1M_0S_0MSTIME#0D_1H_1M_0S_0MS

DATE(IEC date)

16 IEC date in 1-day units

D#1990-1-1 to D#2168-12-31

D#1994-3-15DATE#1994-3-15

TIME_OF_DAY(Time ofday)

32 Time of day in1-ms units

TOD#0:0:0.0 toTOD#23:59:59.999

TOD#1:10:3.3TIME_OF_DAY#1:10:3.3

CHAR(Character)

8 Character ’A’,’B’, etc. ’E’

Addressing


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3.2 Types of Addresses

One of the following elements can be used as the address of an FBDinstruction:

� A bit whose signal state will be checked

� A bit to which the signal state of the logic operation string will beassigned

� A bit to which the result of logic operation (RLO) will be assigned

� A bit that will be set or reset

� A number that indicates a counter that will be incremented ordecremented

� A number that indicates a timer to be used

� An edge memory bit that saves the previous RLO

� An edge memory bit that saves the previous signal state of a differentaddress

� A byte, word, or double word containing a value with which the FBDelement or box will work

� The number of a data block (DB or DI) that will be opened or created

� The number of a function (FC), system function (SFC), a function block(FB), or system function block (SFB) that will be called

� A label as the destination for a jump

Variables as addresses consist of an address identifier and an address withinthe memory area indicated by the address identifier. An address identifier canbe one of the following two basic types:

� An address identifier that indicates the following two data objects:

– The memory area in which the instruction finds a value (data object)with which it can perform a logic operation (for example “I” forprocess input image, see Table 2-5).

– The size of a value (data object) with which the instruction willperform a logic operation (for example B for “Byte”, W for “Word”and D for “Double Word”, see Table 2-5).

� An address identifier that indicates a memory area but not the size of thedata object in the area (for example an identifier for the T area (timers), C(counters), or DB or DI (data block) and the number of the timer, counter,or data block, see Table 2-5).

PossibleAddresses

Address Identifiers

Addressing


A pointer identifies the location of a variable. A pointer contains an addressinstead of a value. When assigning an actual parameter for the parametertype “Pointer”, you provide the memory address. With STEP 7, you can enterthe pointer either in the pointer format or simply as an address (for exampleM 50.0). The following example illustrates the pointer format for accessingdata starting at M 50.0.

P#M50.0

If you are working with an instruction whose address identifier indicates amemory area of your programmable controller and a data object that is eithera word or double word in size, remember that the memory location is alwaysreferenced as a byte address. This byte address is the smallest byte number orthe number of the high byte within the word or double word. The address inthe instruction shown in Figure 3-2, for example, references four successivebytes in the memory area M starting at byte 10 (MB10) through to byte 13(MB13).

Instruction: L MD10

Address identifier Byte address

Figure 3-2 Example of a Memory Location Referenced as a Byte Address

Figure 3-3 shows data objects with the following sizes:

� Double word: memory double word MD10

� Word: memory word MW10, MW11 and MW12

� Byte: memory bytes MB10, MB11, MB12 and MB13

If you use absolute addresses that are a word or double word long, make surethat you avoid any overlapping byte assignments.

MB10 MB11 MB12 MB13

MW11

MD10

MW10 MW12

Figure 3-3 Referencing a Memory Location as a Byte Address

Pointers

Working withWords or DoubleWords as the DataObject

Addressing


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Addressing


Bit Logic Instructions


4.1 Overview 4-2

4.2 AND Logic Operation 4-3

4.3 OR Logic Operation 4-4

4.4 AND-before-OR Logic Operation and OR-before-ANDLogic Operation

4-5

4.5 Exclusive OR Logic Operation 4-6

4.6 Insert Binary Input 4-7

4.7 Negate Binary Input 4-8

4.8 Assign 4-9

4.9 Midline Output 4-10

4.10 Save RLO to BR Memory 4-11

4.11 Set Output 4-12

4.12 Reset Output 4-13

4.13 Set Counter Value 4-14

4.14 Up Counter Instruction 4-16

4.15 Down Counter Instruction 4-17

4.16 Pulse Timer Instruction 4-18

4.17 Extended Pulse Timer Instruction 4-20

4.18 On-Delay Timer Instruction 4-22

4.19 Retentive On-Delay Timer Instruction 4-24

4.20 Off-Delay Timer Instruction 4-26

4.21 Positive RLO Edge Detection 4-28

4.22 Negative RLO Edge Detection 4-29

4.23 Address Positive Edge Detection 4-30

4.24 Address Negative Edge Detection 4-31

4.25 Set_Reset Flip Flop 4-32

4.26 Reset_Set Flip Flop 4-33

ChapterOverview

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4.1 Overview

Bit logic instructions work with two digits, 1 and 0. These two digits formthe base of a number system called the binary system. The two digits 1 and 0are called binary digits or simply bits. In conjunction with AND, OR, XORand outputs, a 1 stands for logical YES and a 0 for logical NO.

The bit logic instructions interpret the signal states 1 and 0 and combinethem according to the rules of Boolean logic. These combinations produce aresult of 1 or 0 known as the result of logic operation (RLO, see Section 2.2).The logic operations triggered by the bit logic instructions execute a varietyof functions.

Bit logic instructions are available for the following functions:

� AND, OR, and XOR: these instructions check the signal state andproduce a result that is either copied to the RLO bit or combined with it.With AND logic operations, the result of the signal state check iscombined according to the AND truth table (see Table 2-7). With ORlogic operations, the result of the signal state check is combinedaccording to the OR truth table (see Table 2-8), with exclusive OR logicoperations, according to the exclusive OR truth table (see Table 2-9).

� Assign and Midline Output: these instructions assign the RLO or store ittemporarily.

� The following instructions react to an RLO of 1:

– Set Output and Reset Output

– Set_Reset Flip Flop and Reset_Set Flip Flop

� Some instructions react to a rising or falling edge so that you can executethe following functions:

– Increment or decrement the value of a counter

– Start a timer

– Produce an output of 1

� The remaining instructions affect the RLO directly in the following ways:

– Negate the RLO

– Save the RLO in the binary result bit of the status word

In this chapter, the counter and timer instructions are shown in theinternational and SIMATIC forms.

Explanation

Functions



4.2 AND Logic Operation

With the AND instruction, you can check the signal states of two or morespecified addresses at the inputs of an AND box.

If the signal state of all addresses is 1, the condition is satisfied and theinstruction provides the result 1. If the signal state of an address is 0, thecondition is not satisfied and the instruction produces the result 0.

If the AND instruction is the first instruction in a string of logic operations, itsaves the result of its signal state check in the RLO bit.

Every AND instruction that is not the first instruction in the string of logicoperations, combines the result of its signal state check with the value storedin the RLO bit. These values are combined according to the AND truth table.

Table 4-1 AND Box and Parameters

FBD Box Parameters Data Type Memory Area Description

<address> &<address>

<address> BOOLTIMERCOUNTER

I, Q, M, T, C, D, L The address indicates the bit whosesignal state will be checked.

I0.0

Status Word Bits

Output Q4.0 is set when the signal state is 1 at inputI0.0 AND I0.1.

BR CC1 CC0 OV OS OR STA RLO FC

writes – – – – – x x x 1

&

I0.1 =

Q4.0

Figure 4-1 AND Logic Operation

Description



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4.3 OR Logic Operation

With the OR instruction, you can check the signal states of two or morespecified addresses at the inputs of an OR box.

If the signal state of one of the addresses is 1, the condition is satisfied andthe instruction produces the result 1. If the signal state of all addresses is 0,the condition is not satisfied and the instruction produces the result 0.

If the OR instruction is the first instruction in a string of logic operations, itsaves the result of its signal state check in the RLO bit.

Each OR instruction that is not the first instruction in the string of logicoperations combines the result of its signal state check with the value storedin the RLO bit. These values are combined according to the OR truth table.

Table 4-2 OR Box and Parameters


<address> >=1<address>


I, Q, M, T, C, D, L The address specifies the bit whosesignal state will be checked

Status Word Bits

Output Q4.0 is set when the signal state is 1 at input I0.0 OR at inputI0.1.


writes – – – – – x x x 1

I0.0 >=1

I0.1 =Q4.0

Figure 4-2 OR Logic Operation

Description



4.4 AND-before-OR Logic Operation and OR-before-AND LogicOperation

With the AND-before-OR instruction, you can check the result of a signalstate according to the OR truth table.

With an AND-before-OR logic operation the signal state is 1 when at leastone AND logic operation is satisfied.

I0.0The signal state is 1 at output Q3.1 whenat least one AND logic operation is satisfied.

&

I0.1

I0.2 &

I0.3

>=1

Q3.1The signal state is 0 at output Q3.1 whenno AND logic operation is satisfied.

Status Word Bits


writes – – – – – x x x 1

=

Figure 4-3 AND-before-OR Logic Operation

With the OR-before-AND instruction, you can check the result of a signalstate check according to the AND truth table.

With an OR-before-AND logic operation the signal state is 1 when all ORlogic operations are satisfied.

I1.0The signal state is 1 at output Q3.1 whenboth OR logic operations are satisfied.I1.1

I1.2

I1.3

>=1Q3.1

The signal state is 0 at output Q3.1 whenat least one OR logic operation is not satisfied.

>=1

Status Word Bits


writes – – – – – x x x 1

=

&

Figure 4-4 OR-before-AND Logic Operation

Description

Description



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4.5 Exclusive OR Logic Operation

With the Exclusive OR instruction, you can check the result of a signal statecheck according to the Exclusive OR truth table.

With an Exclusive OR logic operation, the signal state is 1 when the signalstate of one of the two specified addresses is 1.

Table 4-3 Exclusive OR Box and Parameters


XOR<address><address>


I, Q, M, T, C, D, L The address specifies the bit whosesignal state will be checked.

Status Word Bits

The signal state is 1 at output Q3.1 when the signal state is 1 ateither input I0.0 OR at input I0.2 (exclusively, in other words not at both).


writes – – – – – x x x 1

I0.0XOR

I0.2 =Q3.1

Figure 4-5 Exclusive OR Logic Operation

Description



4.6 Insert Binary Input

The Insert Binary Input instruction inserts a further binary input to an AND,OR, or XOR box.

Table 4-4 Binary Input Element and Parameters

FBD Element Parameters Data Type Memory Area Description

<address><address> BOOL

TIMERCOUNTER

I, Q, M, T, C, D, L The address specifies the bit whosesignal state will be checked

Status Word Bits


writes – – – – – – 1 x –

Output Q4.0 is 1 when the signal state atI1.0 AND I1.1 AND I1.2 is 1.

I1.0 &I1.1

=

Q4.0

I1.2

Figure 4-6 Insert Binary Input

Description



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4.7 Negate Binary Input

The Negate Binary Input instruction negates the RLO.

When you negate the result of logic operation, you must remember certainrules:

� If the result of logic operation at the first input of an AND or OR box isnegated, there is no nesting.

� If the result of logic operation is negated but not at the first input of anOR box, the entire binary logic operation before the input is included inthe OR logic operation.

� If the result of logic operation is negated but not at the first input of aAND box, the entire binary logic operation before the input is included inthe AND logic operation.

Table 4-5 Negate Binary Input Element

FBD Element Parameters Data Type Memory Area Description

None – – –

Status Word Bits


writes – – – – – – 1 x –

Output Q4.0 is 1 when:

the signal state at I1.0 AND I1.1 is NOT 1

AND the signal state at I1.2 AND I1.3 is NOT 1

OR the signal state at I1.4 is NOT 1.I1.2 &I1.3

I1.4

>=1

I1.0 &I1.1

&

=

Q4.0

Figure 4-7 Negate Binary Input

Description



4.8 Assign

The Assign instruction produces the result of logic operation. The box at theend of a logic operation has the signal 1 or 0 according to the followingcriteria:

� The output has the signal 1 when the conditions of the logic operationbefore the output box are satisfied

� The output has the signal 0 when the conditions of the logic operationbefore the output box are not satisfied.

The FBD logic operation assigns the signal state to the output that isaddressed by the instruction (to achieve the same effect, the signal state ofthe RLO bit could also be assigned to the address). If the conditions of theFBD logic operations are satisfied, the signal state at the output box is 1.Otherwise the signal state is 0. The Assign instruction is influenced by theMaster Control Relay (MCR).

For more detailed information about the functions of the MCR, refer toSection 16.4.

You can only place the Assign box at the right-hand end of the string of logicoperations. You can, however, use several Assign boxes.

You can create a negated assignment with the Negate Input instruction.

Table 4-6 Assign Box and Parameters


<address>=

<address> BOOL I, Q, M, D, L The address specifies the bit to whichthe signal state of the string of logicoperations is assigned.

Status Word Bits

The signal state at output Q4.0 is 1 when the signalstate is 1 at inputs I0.0 AND I0.1, OR I0.2 is 0.


writes – – – – – 0 x – 0

Q4.0

I0.0 &

I0.1

I0.2

>=1

=

Figure 4-8 Assign

Description



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4.9 Midline Output

The Midline Output instruction is an intermediate element that buffers theRLO. More precisely, this element buffers the bit logic operation of the lastbranch to be opened before the Midline Output.

The Midline Output instruction is influenced by the Master Control Relay(MCR). For more information about the MCR functions, see Section 16.4.

You can create a negated Midline Output by negating the input of theMidline Output.

Table 4-7 Midline Output Box and Parameters


<address>#

<address> BOOL I, Q, M, D, L1 The address specifies the bit towhich the RLO will be assigned.

1 With the Connector instruction you can only use an address in the L memory area if you declare the address inVAR_TEMP; you cannot use the L memory area for absolute addresses.

Status Word Bits


writes – – – – – 0 x – 1

The Midline Outputs buffer the following results of the logic operations:

M0.0 buffers the negated M1.1 the negated

RLO of RLO of

DB5.DBX3.2 the negated RLO of the entireM2.2 the RLO of bit logic operation in bit 2 of the 3rd bytes in DB 5.

I1.2 &I1.3

I1.4

>=1

I1.0 &I1.1 &

=

M0.0

DB5.DBX3.2 Q4.0

I1.0 &I1.1

I1.2 &I1.3

I1.4

#

M1.1#

M2.2# #

#

Figure 4-9 Midline Output

Description



4.10 Save RLO to BR Memory

The Save RLO to BR Memory instruction saves the RLO in the BR bit of thestatus word. The first check bit FC is not reset.

For this reason, if there is an AND logic operation in the next network, thestate of the BR bit is included in the logic operation.

Using the “Save RLO to BR Memory” instruction in conjunction withchecking the BR bit in the same block or on subordinate blocks is notrecommended, because the BR bit can be modified by many instructionsoccurring inbetween. It is advisable to use the SAVE instruction beforeexiting a block, since the ENO output (=BR bit) is then set to the value of theRLO bit and you can then check for errors in the block.

With the “Save RLO to BR Memory” instruction, the RLO of a network canform part of a logic operation in a subordinate block. The CALL instructionin the calling block resets the first check bit.

Table 4-8 Save RLO to BR Memory Box and Parameters


SAVE None – – –

Status Word Bits


writes x – – – – – – – –

The result of logic operation (RLO) is written to the BR bit.SAVE

I1.2 &I1.3

Figure 4-10 Save RLO to BR Memory

Description



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4.11 Set Output

The Set Output instruction is only executed when the RLO is 1. If the RLO is1, this instruction sets the specified address to 1. If the RLO is 0, theinstruction does not affect the specified address which remains unchanged.

The Set Output instruction is influenced by the Master Control Relay (MCR).For more detailed information about the MCR, refer to Section 16.4.

Table 4-9 Set Output Box and Parameters


<address>

S

<address> BOOL I, Q, M, D, L The address specifies which bit willbe set.

Status Word Bits


writes – – – – – 0 x – 0

Q4.0

The signal state at output Q4.0 is set to 1 only when:

� The signal state is 1 at inputs I0.0 AND I0.1

� OR the signal state at input I0.2 is 0.

If the RLO of the branch is 0, the signal state of Q4.0 isnot changed.

I0.0 &I0.1

S

>=1

I0.2

Figure 4-11 Set Output

Description



4.12 Reset Output

The Reset Output instruction is only executed when the RLO is 1. If the RLOis 1, this instruction resets the specified address to 0. If the RLO is 0, theinstruction does not affect the specified address which remains unchanged.

The Reset Output instruction is influenced by the Master Control Relay(MCR). For more detailed information about the MCR, refer to Section 16.4.

Table 4-10 Reset Output Box and Parameters


<address>

R

<address> BOOL

TIMER

COUNTER

I, Q, M, T, C, D, L The address specifies which bit willbe reset.

Status Word Bits


writes – – – – – 0 x – 0

The signal state at output Q4.0 is reset to 0 only when:

� The signal state is 1 at inputs I0.0 AND I0.1

� OR the signal state at input I0.2 is 0.

If the RLO of the branch is 0, the signal state at outputQ4.0 is unchanged.

Q4.0

I0.0 &I0.1

R

>=1

I0.2

Figure 4-12 Reset Output

Description



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4.13 Set Counter Value

With the Set Counter Value instruction, you assign a default value to thecounter you have specified. This instruction is executed only when there is arising edge at the RLO (change from 0 to 1 in the RLO).

You can only place the Set Counter Value box at the right-hand end of thestring of logic operations. You can, however, use several Set Counter Valueboxes.

Table 4-11 Set Counter Value Box and Parameters, with SIMATIC Mnemonics

FBD Box Parameters Data Type MemoryArea

Description

<address1>

SZ

Counternumber

COUNTER Z Address1 specifies the number of thecounter that will be assigned a presetvalue.

<address2> ZW

ZW WORD E, A, M, D, Lor constant

The value that is preset (address2)can be in the range between 0 and999. If you enter a constant, thecharacters, C# must precede thevalue indicating the BCD format, forexample C#100.

Table 4-12 Set Counter Value Box and Parameters with International Mnemonics


Description

<address1>

SC

Counternumber

COUNTER C Address1 specifies the number of thecounter that will be assigned a presetvalue.

CV<address2>

CV WORD I, Q, M, D, Lor constant

The value that is preset (address2)can be in the range between 0 and999. If you enter a constant, thecharacters, C# must precede thevalue indicating the BCD format, forexample C#100.

Description



Status Word Bits


writes – – – – – 0 – – 0

I0.0

C5 The counter C5 has the value 100 preset when the signalstate of I0.0 changes from 0 to 1 (rising edge in the RLO).C# specifies that you are entering a value in BCD format.

If there is no rising edge, the value of counter C5 is notchanged.C#100 CV

SC

Figure 4-13 Set Counter Value



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4.14 Up Counter Instruction

The Up Counter instruction increments the value of a specified counter by 1when there is a rising edge at the RLO (change from 0 to 1) and the value ofthe counter is less than 999. If there is no rising edge at the RLO, or thecounter has already reached the value 999, it is not incremented.

The Set Counter Value instruction sets the value of the counter (seeSection 4.13).

You can only place the Up Counter box at the right-hand end of the string oflogic operations. You can, however, use several Up Counter boxes.

Table 4-13 Up Counter Boxes and Parameters with SIMATIC and International Mnemonics

FBD Boxes Parameters Data Type Memory Area Description

<address>

ZV

<address>

CU

Counternumber

COUNTER Z

C

The address specifies the number ofthe counter that will be incremented.

Status Word Bits


writes – – – – – 0 – – 0

I0.0

C10 If the signal state of I0.0 changes from 0 to 1 (rising edgein the RLO), the value of the counter C10 is incrementedby 1 (unless the value of C10 is 999).

If there is no rising edge, the value of C10 remainsunchanged.

CU

Figure 4-14 Up Counter

Description



4.15 Down Counter Instruction

The Down Counter instruction decrements the value of a specified counter by1 when there is a rising edge at the RLO (change from 0 to 1) and the valueof the counter is higher than 0. If there is no rising edge at the RLO, or if thecounter has already reached the value 0, the value of the counter is notdecremented.

The Set Counter Value instruction sets the value of the counter (seeSection 4.13).

You can only place the Down Counter box at the right-hand end of the stringof logic operations. You can, however, use more than one Down Counterboxes.

Table 4-14 Down Counter Boxes and Parameters with SIMATIC and International Mnemonics

FBD Boxes Parameters Data Type Memory Area Description

<address>

ZR

<address>

CD

Counternumber

COUNTER Z

C

The address specifies the number ofthe counter to be decremented.

Status Word Bits


writes – – – – – 0 – – 0

I0.0

C10If the signal state of input I0.0 changes from 0 to 1 (risingedge at the RLO), the value of counter C10 is decrementedby 1 (unless the value of C10 is already 0).

If there is no rising edge, the value of C10 is not changed.CD

Figure 4-15 Down Counter

Description



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4.16 Pulse Timer Instruction

The Pulse Timer instruction starts a timer with a specified value when thereis a rising edge at the RLO (change from 0 to 1). As long as the RLO ispositive, the timer continues to run for the specified time. A signal statecheck for 1 produces 1 as long as the timer is running. If the RLO changesfrom 1 to 0 before the time has expired, the timer is stopped. In this case, asignal state check for 1 produces a result of 0.

The time units used for timers are d (days), h (hours), m (minutes), s(seconds) and ms (milliseconds).

For more detailed information about the memory area and the components ofa timer, refer to Section 5.1.

You can only place the Pulse Timer box at the right-hand end of the string oflogic operations. You can, however, use more than one Pulse Timer box.

Table 4-15 Pulse Timer Box and Parameters with SIMATIC Mnemonics


<address>

SI

Timernumber

TIMER T The address specifies thenumber of the timer to bestarted.

TW<timevalue>

TW S5TIME E, A, M, D, L orconstant

Time value (S5TIME format)

Table 4-16 Pulse Timer Box and Parameters with International Mnemonics


<address>

SP

Timernumber


TV<timevalue>

TV S5TIME I, Q, M, D, L orconstant


Description



Status Word Bits


writes – – – – – 0 – – 0

T5If the signal state of input I0.0 changes from 0 to 1 (rising edge atthe RLO), timer T5 is started. As long as the signal state is 1, thetimer continues to run for the specified time of 2 seconds. If thesignal state at I0.0 changes from 1 to 0 before this time hasexpired, the timer is stopped.As long as the timer is running, the signal state at output Q4.0 is 1.

Examples of timer values:

S5T#2s = 2 seconds

S5T#12m_18s = 12 minutes and 18 seconds

I0.0

TV

SP

S5T#2s

Q4.0=T5

Network 1:

Network 2:

Figure 4-16 Pulse Timer



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4.17 Extended Pulse Timer Instruction

The Extended Pulse Timer instruction starts a timer with a specified value ifthere is a rising edge at the RLO (change from 0 to 1). The timer continues torun for the specified time even if the RLO changes to 0 before this time hasexpired. A signal state check for 1 produces 1 as long as the timer is running.The timer is restarted with the specified time if the RLO changes from 0 to 1while the timer is running.

For more detailed information about the memory area and the components ofa timer, refer to Section 5.1.

You can only place the Extended Pulse Timer box at the right-hand end of thestring of logic operations. You can, however, use more than one ExtendedPulse Timer box.

Table 4-17 Extended Pulse Timer Box and Parameters with SIMATIC Mnemonics


<address>

SV

Timernumber


TW<timevalue>



Table 4-18 Extended Pulse Timer Box and Parameters with International Mnemonics


<address>

SE

Timernumber


TV<timevalue>



Description



Status Word Bits


writes – – – – – 0 – – 0

If the signal state of input I0.0 changes from 0 to 1 (rising edge atthe RLO), timer T5 is started. The timer continues to run withoutbeing influenced by a falling edge at the RLO. If the signal state ofinput I0.0 changes from 0 to 1 before the specified time hasexpired, the timer is retriggered.

As long as the timer is running, the signal state at output Q4.0 is 1.

S5T#2s

I0.0

TV

SE

T5

Q4.0=T5

Network 1:

Network 2:

Figure 4-17 Extended Pulse Timer



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4.18 On-Delay Timer Instruction

The On-Delay Timer instruction starts a specified timer when there is a risingedge at the RLO (change from 0 to 1). A signal state check for 1 produces 1when the specified time has expired without an error occurring and the RLOis still 1. If the RLO changes from 1 to 0 while the timer is running, the timeris stopped. In this case, a signal state check for 1 always produces the result0.

For more detailed information about the address of a timer in memory andthe components of a timer, refer to Section 5.1.

You can only place the On-Delay Timer box at the right-hand end of thestring of logic operations. You can, however, use more than one On-DelayTimer box.

Table 4-19 On-Delay Timer Box and Parameters with SIMATIC Mnemonics


<address>SE

Timernumber


TW<timevalue>



Table 4-20 On-Delay Timer Box and Parameters with International Mnemonics


<address>SD

Timernumber


TV<timevalue>



Description



Status Word Bits


writes – – – – – 0 – – 0

If the signal state of input I0.0 changes from 0 to 1(rising edge at the RLO), timer T5 is started. When thetime expires, and the signal state is still 1, output Q4.0has the value 1. If the signal state changes from 1 to 0,the timer is stopped.

S5T#2s

I0.0

TV

SDT5

Q4.0=T5

Network 1:

Network 2:

Figure 4-18 On-Delay Timer



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4.19 Retentive On-Delay Timer Instruction

The Retentive On-Delay Timer instruction starts the specified timer whenthere is a rising edge at the RLO (change from 0 to 1). The timer continues torun for the specified time if the RLO changes to 0 before the time hasexpired. A signal state check for 1 produces the result 1 regardless of theRLO if the time has expired. If the RLO changes from 0 to 1 while the timeris running, the timer is restarted with the specified value.

Fore more detailed information about the address of a timer in memory andthe components of a timer, refer to Section 5.1.

You can only place the Retentive On-Delay Timer box at the right-hand endof the string of logic operations. You can, however, use more than oneRetentive On-Delay Timer box.

Table 4-21 Retentive On-Delay Timer Box and Parameters with SIMATIC Mnemonics


<address>

SS

Timernumber


TW<timevalue>



Table 4-22 On-Delay Timer Box and Parameters with International Mnemonics


<address>

SS

Timernumber


TV<timevalue>



Description



Status Word Bits


writes – – – – – 0 – – 0

If the signal state of input I0.0 changes from 0 to 1 (risingedge at the RLO), timer T5 is started. The timer continues torun regardless of whether the signal state at I0.0 changesfrom 1 to 0. If the signal state changes from 0 to 1 before thetime has expired, the timer is retriggered. Output Q4.0 has the value 1 when the time has expired.S5T#2s

I0.0

TV

SST5

Q4.0=T5

Network 1:

Network 2:

Figure 4-19 Retentive On-Delay Timer



C79000-G7076-C566-01

4.20 Off-Delay Timer Instruction

The Off-Delay Timer instruction starts the specified timer when the RLO hasa falling edge (change from 1 to 0). A signal state check for 1 produces 1when the RLO is 1 or when the timer is running. The timer is reset when theRLO changes from 0 to 1 while the timer is running. The time is onlyrestarted when the RLO changes from 1 to 0.

For more detailed information about the address of a timer in memory andthe components of a timer, refer to Section 5.1.

You can only place the Off-Delay Timer box at the right-hand end of thestring of logic operations. You can, however, use more than one Off-DelayTimer box.

Table 4-23 Off-Delay Timer Box and Parameters with SIMATIC Mnemonics


<address>

SA

Timernumber


TW<timevalue>



Table 4-24 Off-Delay Timer Box and Parameters with International Mnemonics


<address>

SF

Timernumber


TV<timevalue>



Description



Status Word Bits


writes – – – – – 0 – – 0

The timer is started when the signal state at I0.0 changes from1 to 0.

If the signal state changes from 0 to 1, the timer is reset.

The signal state at output Q4.0 is 1, when the signal state atinput I0.0 is 1 or the timer is running.

S5T#2s

I0.0

TV

SFT5

Q4.0=T5

Network 1:

Network 2:

Figure 4-20 Off-Delay Timer



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4.21 Positive RLO Edge Detection

The Positive RLO Edge Detection instruction detects a change from 0 to 1(rising edge) at the specified address and indicates this with an RLO of 1after the instruction. The current signal state at the RLO is compared with thesignal state of the address (the edge memory bit). If the signal state of theaddress is 0 and the RLO is 1 before the instruction, the RLO will be 1(pulse) after the instruction, in all other cases the RLO is 0. The RLO prior tothe instruction is stored in the address.

Table 4-25 Positive RLO Edge Detection Box and Parameter


P

<address> <address> BOOL I, Q, M, D, L The address specifies which edgememory bit will store the previousRLO.

Status Word Bits


writes – – – – – 0 x x 1

The edge memory bit M3.3 stores thesignal state of the previous RLO.

I1.2 &I1.3

I1.4&

>=1

I1.0 &I1.1 &

=

Q4.0

P

M0.0

N

M1.1

P

M2.2

N

M3.3

Figure 4-21 Positive RLO Edge Detection

Description



4.22 Negative RLO Edge Detection

The Negative RLO Edge Detection instruction detects a change from 1 to 0(falling edge) at the specified address and indicates this by setting the RLO to1 after the instruction. The current signal state of the RLO is compared withthe signal state of the address (the edge memory bit). If the signal state of theaddress is 1 and the RLO prior to the instruction was 0, the RLO is 1 (pulse)after the instruction, in all other cases it is 0. The RLO prior to the instructionis stored in the address.

Table 4-26 Negative RLO Edge Detection Box and Parameter


N

<address> <address> BOOL I, Q, M, D, L The address specifies which edgememory bit will store the previousRLO.

Status Word Bits


writes – – – – – 0 x x 1

The edge memory bit M3.3 stores thesignal state of the previous RLO.

I1.2 &I1.3

I1.4&

>=1

I1.0 &I1.1 &

=

Q4.0

P

M0.0

N

M1.1

P

M2.2

N

M3.3

Figure 4-22 Negative RLO Edge Detection

Description



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4.23 Address Positive Edge Detection

The Address Positive Edge Detection instruction compares the signal state of<address1> with the signal state of the previous signal check that is stored inthe parameter M_BIT. If there has been a change from 0 to 1, output Q hasthe value 1, in all other cases it has the value 0.

Table 4-27 Address Positive Edge Detection Box and Parameters


POS<address1> <address1> BOOL I, Q, M, D, L Signal to be checked for a positive

(rising) edge.

M_BIT Q

M_BIT BOOL Q, M, D The M_BIT address specifies theedge memory bit used to store theprevious signal state of POS. Youshould only use the process imageinput area I for the M_BIT whenno input module is already usingthis address.

Q BOOL I, Q, M, D, L One-shot output.

Status Word Bits


writes x – – – – 0 1 x 1


there is a rising edge at input I0.3 AND the signal state is 1 at input I0.4.

I0.3

POS

M_BIT QM0.0

=Q4.0

I0.4

&

Figure 4-23 Address Positive Edge Detection

Description



4.24 Address Negative Edge Detection

The Address Negative Edge Detection instruction compares the signal state of<address1> with the signal state of the previous check that is stored in theM_BIT parameter. If a change from 1 to 0 occurred, output Q has the value1, in all other situations it has the value 0.

Table 4-28 Address Negative Edge Detection Box and Parameters


NEG<address1> <address1> BOOL I, Q, M, D, L Signal to be checked for a

negative (falling) edgechange.

M_BIT Q

M_BIT BOOL Q, M, D The M_BIT addressspecifies the edge memorybit in which the previoussignal state of NEG isstored. Only use theprocess input image Imemory area for theM_BIT when no inputmodule is already usingthis address.

Q BOOL I, Q, M, D, L One-shot output.

Status Word Bits


writes x – – – – 0 1 x 1


there is a falling edge at input I0.3AND the signal state at input I0.4 is 1.

I0.3

NEG

M_BIT QM0.0

=Q4.0

I0.4

&

Figure 4-24 Address Negative Edge Detection

Description



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4.25 Set_Reset Flip Flop

The Set_Reset Flip Flop instruction executes Set (S) or Reset (R) instructionsonly when the RLO is 1. An RLO of 0 has no effect on these instructions, theaddress specified in the instruction remains unchanged.

Set_Reset Flip Flop is set when the signal state at input S is 1 and the signalstate at input R is 0. If input S is 0 and input R is 1, the flip flop is reset. Ifthe RLO at both inputs is 1 the flip flop is reset.

The Set_Reset Flip Flop instruction is influenced by the Master ControlRelay (MCR). For more detailed information about how the MCR functions,refer to Section 16.4.

Table 4-29 Set_Reset Flip Flop Box and Parameters


<address>

SR

<address> BOOL I, Q, M, D, L The address specifies which bit willbe set or reset.

S S BOOL I, Q, M, D, L, T, C Set instruction enabled

R QR BOOL I, Q, M, D, L, T, C Reset instruction enabled

R QQ BOOL I, Q, M, D, L Signal state of <address>

Status Word Bits


writes – – – – – x x x 1

If I0.0 is 1 and I0.1 is 0, memory bit M0.0is set and Q4.0 is 1.If I0.0 is 0 and I0.1 is 1, the memory bitM0.0 is reset and Q4.0 is 0.

If both signal state are 0, there is nochange. If both signal states are 1, thereset instruction dominates due to theorder of the instructions. M0.0 is reset and Q 4.0 is 0.

M0.0

R Q

SI0.0

&

I0.1

I0.0I0.1

&

=

Q4.0

SR

Figure 4-25 Set_Reset Flip Flop

Description



4.26 Reset_Set Flip Flop

The Reset_Set Flip Flop instruction executes instructions such as Set (S) orReset (R) only when the RLO is 1. An RLO of 0 does not affect theseinstructions, the address specified in the instruction is not changed.

Reset_Set Flip Flop is reset when the signal state at input R is 1 and thesignal state at input S is 0. If input R is 0 and input S is 1, the flip flop is set.If the RLO at both inputs is 1, the flip flop is set.

The Reset_Set Flip Flop instruction is affected by the Master Control Relay(MCR). For more detailed information about the way in which the MCRfunctions, refer to Section 16.4.

Table 4-30 Reset_Set Flip Flop Box and Parameters


R

<address>

RS

<address> BOOL I, Q, M, D, L The address specifies which bit willbe set or reset.

RS BOOL I, Q, M, D, L, T, C Reset instruction enabled

QS R BOOL I, Q, M, D, L, T, C Set instruction enabled

Q BOOL I, Q, M, D, L Signal state of <address>

Status Word Bits


writes – – – – – x x x 1

If I0.0 is 1 and I0.1 is 0, the memory bit M0.0is reset and output Q4.0 is 0. If I0.0 is 0 andI0.1 is 1, the memory bit M0.0 is set andoutput Q4.0 is 1.

If both signal states are 0, there is no change.If both signal states are 1, the Set instructiondominates due to the order of theinstructions. M 0.0 is set and Q4.0 is 1.

M0.0

S Q

RI0.0

&

I0.1

I0.0I0.1

&

=

Q4.0

RS

Figure 4-26 Reset_Set Flip Flop

Description



C79000-G7076-C566-01



Timer Instructions


5.1 Memory Areas and Components of a Timer 5-2

5.2 Choosing the Right Timer 5-4

5.3 Pulse S5 Timer 5-5

5.4 Extended Pulse S5 Timer 5-7

5.5 On-Delay S5 Timer 5-9

5.6 Retentive On-Delay S5 Timer 5-11

5.7 Off-Delay S5 Timer 5-13

ChapterOverview

5


C79000-G7076-C566-01

5.1 Memory Areas and Components of a Timer

Timers have an area reserved for them in the memory of your CPU. Thismemory area reserves one 16-bit word for each timer address. When youprogram in FBD, 256 timers are supported. Please refer to your CPU’stechnical information to check the number of timer words available.

The following functions access the timer memory area:

� Timer instructions

� Updating of timer words by the clock timing. In the RUN mode, this CPUfunction decrements a given time value by one unit at the intervalspecified by the time base until the time value is zero.

Bits 0 through 9 of the timer word contain the time value in binary code. Thetime value specifies a number of units. When the timer is updated, the timevalue is decremented by one unit at intervals specified by the time base. Thetime value is decremented until it is equal to zero.

You can load a predefined time value with the following syntax.

� S5T#aH_bbM_ccS_dddMS

– where: a = hours, bb = minutes, cc = seconds and ddd = milliseconds

– The time base is selected automatically, and the value is roundeddown to the next lower number with that time base.

The maximum time value you can enter is 9,990 seconds, or 2H_46M_30S.

Bits 12 and 13 of the timer word contain the time base in binary code. Thetime base defines the interval at which the time value is decremented by oneunit (see Table 5-1 and Figure 5-1). The smallest time base is 10 ms; thelargest is 10 s.

Table 5-1 Time Base and Binary Code

Time Base Binary Code for the Time Base

10 ms 00

100 ms 01

1 s 10

10 s 11

Memory Area

Time Value

Time Base

Timer Instructions


Because time values are saved at only one time interval, values that are notexact multiples of a time interval are truncated. Values with a resolution toohigh for the required range are rounded down to within the required range butnot to the desired resolution. The following table shows the possibleresolutions and the corresponding ranges.

Table 5-2 Resolution and Ranges of the Time Base

Resolution Time Base

0.01 seconds 10MS to 9S_990MS

0.1 seconds 100MS to 1M_39S_900MS

1 second 1S to 16M_39S

10 seconds 10S to 2HR_46M_30S

When a timer is started, the contents of the timer cell are used as the timevalue. Bits 0 through 11 of the timer cell contain the time value in binarycoded decimal format (BCD format: each group of four bits contains thebinary code for one decimal value). Bits 12 and 13 contain the time base inbinary code (see Table 5-2). Figure 5-1 shows the contents of the timer cellloaded with timer value 127 with a time base of 1 second.

Time base1 second

Irrelevant: These bits are ignored when the timer is started.

Time value in BCD (0 to 999)

15... ...8 7... ...0

1 2 7

x x 1 0 0 0 0 1 0 0 1 0 0 1 1 1

Figure 5-1 Contents of the Timer Cell for Timer Value 127, Time Base 1 Second

Each timer box provides two outputs, BI and BCD, for which you can specifya word location. The BI output provides the time value in binary format, thetime base is not displayed. The BCD output provides the time base and thetime value in binary coded decimal (BCD) format.

Bit Configurationin the Timer Cell

Reading the Timeand the Time Base

Timer Instructions


C79000-G7076-C566-01

5.2 Choosing the Right Timer

The following figure provides an overview of the five types of timersdescribed in this chapter. This overview is intended to help you choose theright timer for your timing job.

I0.0

Q4.0

S_PEXT

S_ODT

S_ODTS

S_OFFDT

Input signal

Output signal(Pulse timer) t

S_PULSE

t

t

t

t

The maximum time that the output signal remains at 1 is thesame as the programmed time value t. The output signalstays at 1 for a shorter period if the input signal changes to 0.

The output signal remains at 1 for the programmed length oftime, regardless of how long the input signal stays at 1.

The output signal changes to 1 only when the programmedtime has elapsed and the input signal is still 1.

The output signal changes from 0 to 1 only when theprogrammed time has elapsed, regardless of how long theinput signal stays at 1.

The output signal changes to 1 when the input signal changesto 1 or while the timer is running. The time is started when theinput signal changes from 1 to 0.

Q4.0Output signal(Extended pulsetimer)

Q4.0Output signal(On-delay timer)

Q4.0Output signal(Retentiveon-delay timer)

Q4.0Output signal(Off-delay timer)

Figure 5-2 Choosing the Right Timer

Timer Instructions


5.3 Pulse S5 Timer

The Pulse S5 Timer instruction starts a specified timer if there is a rising edge(a change in signal state from 0 to 1) at the Start (S) input. A signal change isalways necessary to start a timer. The timer continues to run for the timespecified at the Time Value (TV) input until the programmed time elapses, aslong as the signal state at input TV is 1. While the timer is running, a signalstate check for 1 at output Q produces a result of 1. If there is a change from1 to 0 at the S input before the time has elapsed, the timer is stopped. Then asignal state check for 1 at output Q produces a result of 0.

While the timer is running, a change from 0 to 1 at the Reset (R) input of thetimer resets the timer. This change also resets the time and the time base tozero. A signal state of 1 at the R input of the timer has no effect if the timeris not running.

The current time value can be scanned at outputs BI and BCD. The timevalue at BI is in binary format; at BCD it is in binary coded decimal format.

Table 5-3 Pulse S5 Timer Box and Parameters with SIMATIC Mnemonics


T–Nr.

Nr. TIMER T Timer identification number. The rangedepends on the CPU. T Nr.

S IMPULSS BOOL E, A, M, D, L, T, Z Start input

S_IMPULS

S DUALTW S5TIME E, A, M, D, L or

constantPreset time value (range 0 to 9999)

DEZTW R BOOL E, A, M, D, L, T, Z Reset input

R Q DUAL WORD E, A, M, D, L Time remaining (value in integer format)QDEZ WORD E, A, M, D, L Time remaining (value in BCD format)

Q BOOL E, A, M, D, L Status of the timer

Table 5-4 Pulse S5 Timer Box and Parameters with International Mnemonics


T no.

no. TIMER T Timer identification number. The rangedepends on the CPU. T no.

S PULSES BOOL I, Q, M, D, L, T, C Start input

S_PULSE

S BITV S5TIME I, Q, M, D, L or

constantPreset time value (range 0 to 9999)

BCDTV R BOOL I, Q, M, D, L, T, C Reset input

R Q BI WORD I, Q, M, D, L Time remaining (value in integer format)

BCD WORD I, Q, M, D, L Time remaining (value in BCD format)

Q BOOL I, Q, M, D, L Status of the timer

Description

Timer Instructions


C79000-G7076-C566-01

Figure 5-3 illustrates the Pulse S5 Timer instruction, describes the status wordbits, and shows the characteristics of the instruction.

If the signal state of input I0.0 changes from 0 to 1 (ifthere is a rising edge in the RLO), timer T5 is started.The timer continues to run with the specified time oftwo seconds (2s) as long as input I0.0 is 1. If thesignal state of input I0.0 changes from 1 to 0 beforethe time elapses, the timer is stopped. If the signalstate of input I0.1 changes from 0 to 1 while the timeris running, the timer is reset. The signal state ofoutput Q4.0 is 1 as long as the timer is running.

Examples of other preset time values:Available units: h (hours), m (minutes), s (seconds),ms (milliseconds)

S5T#4s ––> 4 secondsS5T#1h_15m ––> 1 hour and 15 minutesS5T#2h_46m_30s––>2 hours, 46 minutes, and30 seconds

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites – – – – – x x x 1

Timing Diagram

RLO at input S

RLO at input R

Timer running

RLO at output Q

Negated RLO at output Q

–– t ––

t = programmed time

T5

R Q

TV

BI

BCDS5T# 2s

I0.1Q4.0

SI0.0

=

S_PULSE

–– t –– –– t ––

Figure 5-3 Pulse S5 Timer

Example

Timer Instructions


5.4 Extended Pulse S5 Timer

The Extended Pulse S5 Timer instruction starts a specified timer if there is arising edge (change in signal state from 0 to 1) at the Start (S) input. A signalchange is always necessary to start a timer. The timer continues to run for thetime specified at the Time Value (TV) input, even if the signal state at the Sinput changes to 0 before the time has elapsed. A signal state check for 1 atoutput Q produces a result of 1 as long as the timer is running. The timer isrestarted with the specified time if the signal state at input S changes from 0to 1 while the timer is running.

A change from 0 to 1 at the Reset (R) input of the timer while the timer isrunning resets the timer. This change also resets the time and the time base tozero.

The current time value can be scanned at the outputs BI and BCD. The timevalue at BI is in binary format; at BCD it is in binary coded decimal format.

Table 5-5 Extended Pulse S5 Timer Box and Parameters with SIMATIC Mnemonics


T Nr.Nr. TIMER T

Timer identification number. The rangedepends on the CPU.

S_VIMP S BOOL E, A, M, D, L, T, Z Start input_

S DUAL TW S5TIMEE, A, M, D, L orconstant

Preset time value (range 0 to 9999)

DEZTW R BOOL E, A, M, D, L, T, Z Reset input

R Q DUAL WORD E, A, M, D, L Time remaining (value in integer format)

DEZ WORD E, A, M, D, L Time remaining (value in BCD format)


Table 5-6 Extended Pulse S5 Timer Box and Parameters with International Mnemonics


T no.no. TIMER T Timer identification number. The range

depends on the CPU.

S_PEXT S BOOL I, Q, M, D, L, T, C Start input

BCD

S

TV

BI TV S5TIME I, Q, M, D, L orconstant

Preset time value (range 0 to 9999)

BCDTV

QR BOOL I, Q, M, D, L, T, C Reset input




Description

Timer Instructions


C79000-G7076-C566-01

Figure 5-4 illustrates the Extended Pulse S5 Timer instruction, describes thestatus word bits, and shows the characteristics of the instruction.

If the signal state of input I0.0 changes from 0 to 1(rising edge in the RLO), timer T5 is started. Thetimer continues to run for the specified time of twoseconds (2s) regardless of a falling edge at input S. Ifthe signal state of input I0.0 changes from 0 to 1before the time has elapsed, the timer is restarted. Ifthe signal state of input I0.1 changes from 0 to 1while the timer is running, the timer is reset. Thesignal state of output Q4.0 is 1 as long as the timer isrunning.

Status Word Bits


Timing Diagram

RLO at input S

RLO at input R

Timer running

–– t –– –– t ––

t = programmed time

T5

S_PEXT

R Q

TV

BI

BCDS5T# 2s

I0.1Q4.0

SI0.0

=

–– t –– –– t ––

RLO at output Q


Figure 5-4 Extended Pulse S5 Timer

Example

Timer Instructions


5.5 On-Delay S5 Timer

The On-Delay S5 Timer instruction starts a specified timer if there is a risingedge (change in signal state from 0 to 1) at the Start (S) input. A signalchange is always necessary to start a timer. The timer continues to run for thetime specified at the Time Value (TV) input as long as the signal state atinput S is 1. A signal state check for 1 at output Q produces a result of 1when the time has elapsed without error and when the signal state at input Sis still 1. When the signal state at input S changes from 1 to 0 while the timeris running, the timer is stopped. In this case, a signal state check for 1 atoutput Q always produces the result 0.

A change from 0 to 1 at the Reset (R) input of the timer while the timer isrunning resets the timer. This change also resets the time and the time base tozero. The timer is also reset if the signal state is 1 at the R input while thetimer is not running.


Table 5-7 On-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics


T–Nr.Nr. TIMER T Timer identification number. The range

depends on the CPU.

S_EVERZ S BOOL E, A, M, D, L, T, Z Start input

DEZ

S

TW

DUAL TW S5TIME E, A, M, D, L orconstant

Preset time value (range 0 – 9999)

DEZTWR BOOL E, A, M, D, L, T, Z Reset input




Table 5-8 On-Delay S5 Timer Box and Parameters with International Mnemonics



depends on the CPU.

S_ODT S BOOL I, Q, M, D, L, T, C Start input

BCD

S

TV



BCDTV R BOOL I, Q, M, D, L, T, C Reset input




Description

Timer Instructions


C79000-G7076-C566-01

Figure 5-5 illustrates the On-Delay S5 Timer instruction, describes the bits inthe status word and shows the characteristics of the instruction.

If the signal state of input I0.0 changes from 0 to 1(rising edge in the RLO), timer T5 is started. If thespecified time of two seconds (2s) elapses andthe signal state of input I0.0 is still 1, the signalstate of output Q4.0 is 1. If the signal state ofinput I0.0 changes from 1 to 0, the timer isstopped and output Q4.0 is 0. If the signal state ofinput I0.1 changes from 0 to 1 while the timer isrunning, the timer is restarted.

Status Word Bits


Timing Diagram

RLO at input S

RLO at input R

Timer running

–– t –– –– t ––

t = programmed time

T5

R Q

TV

BI

BCDS5T# 2s

I0.1Q4.0

SI0.0

=

S_ODT

–– t ––

RLO at output Q


Figure 5-5 On-Delay S5 Timer

Example

Timer Instructions


5.6 Retentive On-Delay S5 Timer

The Retentive On-Delay S5 Timer instruction starts a specified timer if thereis a rising edge (change in signal state from 0 to 1) at the Start (S) input. Asignal change is always necessary to start a timer. The timer continues to runfor the time specified at the Time Value (TV) input, even if the signal state atinput S changes to 0 before the timer has expired. A signal state check for 1at output Q produces a result of 1 when the time has elapsed, regardless ofthe signal state at input S when the reset input (R) remains at 0. The timer isrestarted with the specified time if the signal state at input S changes from 0to 1 while the timer is running.

A change from 0 to 1 at the Reset (R) input of the timer resets the timerregardless of the RLO at the S input.


Table 5-9 Retentive On-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics


T–Nr.

S SEVERZ

Nr. TIMER T Timer identification number. The rangedepends on the CPU.

S_SEVERZ S BOOL E, A, M, D, L, T, Z Start input

DEZ

S

TW



DEZTW

R QR BOOL E, A, M, D, L, T, Z Reset input




Table 5-10 Retentive On-Delay S5 Timer Box and Parameters with International Mnemonics


T no.

S ODTS

no. TIMER T Timer identification number. The rangedepends on the CPU.

S_ODTS S BOOL I, Q, M, D, L, T, C Start input

BCD

S

TV



BCDTV

R QR BOOL I, Q, M, D, L, T, C Reset input




Description

Timer Instructions


C79000-G7076-C566-01

Figure 5-6 illustrates the Retentive On-Delay S5 Timer instruction, describesthe status word bits, and shows the characteristics of the instruction.

If the signal state of input I0.0 changes from 0 to1 (rising edge in the RLO), timer T5 is started.The timer continues to run regardless of a signalchange at input I0.0 from1 to 0. If the signalstate of input I0.0 changes from 0 to 1 beforethe time has elapsed, the timer is restarted. Ifthe signal state of input I0.1 changes from 0 to 1while the timer is running, the timer is restarted.The signal state of output Q4.0 is 1 if the timehas elapsed and the signal state at I 0.1remains 0.

Status Word Bits


Timing Diagram

RLO at input S

RLO at input R

Timer running

–– t –– –– t ––

t = programmed time

T5

R Q

TV

BI

BCDS5T# 2s

I0.1Q4.0

SI0.0

=

S_ODTS

–– t –– – t –

RLO at output Q


Figure 5-6 Retentive On-Delay S5 Timer

Example

Timer Instructions


5.7 Off-Delay S5 Timer

The Off-Delay S5 Timer instruction starts a specified timer if there is a fallingedge (change in signal state from 1 to 0) at the Start (S) input. A signalchange is always necessary to start a timer. The result of a signal state checkfor 1 at output Q is 1 when the signal state at the S input is 1 or when thetimer is running. The timer is reset when the signal state at input S changesfrom 0 to 1 while the timer is running. The timer is not restarted until thesignal state at input S changes again from 1 to 0.

A change from 0 to 1 at the Reset (R) input of the timer while the timer isrunning resets the timer.

The actual time value can be scanned at the outputs BI and BCD. The timevalue at BI is in binary format; at BCD it is in binary coded decimal format.

Table 5-11 Off-Delay S5 Timer Box and Parameters with SIMATIC Mnemonics


T–Nr.Nr. TIMER T Timer identification number. The range

depends on the CPU.

S_AVERZ S BOOL E, A, M, D, L, T, Z Start input

DEZ

S

TW



DEZTW

QR BOOL E, A, M, D, L, T, Z Reset input




Table 5-12 Off-Delay S5 Timer Box and Parameters with International Mnemonics



depends on the CPU.

S_OFFDT S BOOL I, Q, M, D, L, T, C Start input

BCD

S

TV



BCDTV

QR BOOL I, Q, M, D, L, T, C Reset input




Description

Timer Instructions


C79000-G7076-C566-01

Figure 5-7 illustrates the Off-Delay S5 Timer instruction, describes the statusword bits, and shows the characteristics of the instruction.

If the signal state at input I0.0 changes from 1 to 0,the timer is started. Output Q4.0 is 1 when I0.0 is 1 orthe timer is running. If the signal state at I0.1 changesfrom 0 to 1, while the timer is running, the timer isreset.

Status Word Bits


Timing Diagram

RLO at input S

RLO at input R

Timer running

t = programmed time

–– t –– –– t ––

T5

R Q

TV

BI

BCDS5T# 2s

I0.1Q4.0

SI0.0

=

S_OFFDT

–– t –––– t ––

RLO at output Q


Figure 5-7 Off-Delay S5 Timer

Example

Timer Instructions


Counter Instructions


6.1 Memory Address and Components of a Counter 6-2

6.2 Up-Down Counter 6-3

6.3 Up Counter 6-5

6.4 Down Counter 6-7

ChapterOverview

6


C79000-G7076-C566-01

6.1 Memory Address and Components of a Counter

Counters have an area reserved for them in the memory of your CPU. Thismemory area reserves one 16-bit word for each counter address. When youprogram in FBD, 256 counters are supported.

The counter instructions are the only functions that can access the countermemory area.

Bits 0 through 9 of the counter word contain the count value in binary code.The count value is taken from the accumulator and entered in the counterword when a counter is set. The range of the count value is 0 to 999. You canincrement/decrement the count value within this range using the Up-DownCounter, Up Counter, and Down Counter instructions.

A counter is set to a required value by loading a number between 0 and 999as the count value, for example 127, in the following format:

C# 127

The C# stands for binary coded decimal format (BCD format: each group offour bits contains the binary code for one decimal value).

Bits 0 through 11 of the counter contain the count value in binary codeddecimal format . Figure 6-1 shows the contents of the counter after you haveloaded the count value 127 and the contents of the counter cell after thecounter has been set.

irrelevant

15

1 2 7

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 111 10000000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 110 111100

irrelevant Binary count value

Count value in BCD (0 to 999)

Figure 6-1 Contents of the Counter Cell after the Counter has been Set with CountValue 127

Memory Area

Count Value

Bit Configurationin the Counter



6.2 Up-Down Counter

A rising edge (change in signal state from 0 to 1) at input S of the Up-DownCounter instruction sets the counter with the value at the Preset Value (PV)input. The counter is incremented by 1 if the signal state at input CU changesfrom 0 to 1 (rising edge) and the value of the counter is less than 999. Thecounter is decremented by 1 if the signal state at input CD changes from 0 to1 (rising edge) and the value of the counter is higher than 0. If there is arising edge at both count inputs, both operations are executed and the countremains the same. The counter is reset if there is a rising edge at input R.Resetting the counter sets the count value to 0.

A signal state check for 1 at output Q produces a result of 1 when the count isgreater than 0; the check produces a result of 0 when the count is equal to 0.

Table 6-1 Up-Down Counter Box and Parameters with SIMATIC Mnemonics


Z-Nr

Nr. COUNTER Z Counter identification number. Therange depends on the CPU.

Z-Nr.ZAEHLER

ZV BOOL E, A, M, D, L ZV input: Up CounterZAEHLER

ZV ZR BOOL E, A, M, D, L ZR input: Down Counter

ZR S BOOL E, A, M, D, L, T, Z Input for presetting the counter

DEZ

Q

DUALS

ZW

R

ZW WORD E, A, M, D, L

or constant

Count value in the range between 0and 999 or

Count value entered as C#<value> inBCD format

R BOOL E, A, M, D, L, T, Z Reset input

DUAL WORD E, A, M, D, L Current count value (integer format)

DEZ WORD E, A, M, D, L Current count value (BCD format)

Q BOOL E, A, M, D, L Status of the counter

Description



C79000-G7076-C566-01

Table 6-2 Up-Down Counter Box and Parameters with International Mnemonics


no. COUNTER C Counter identification number. Therange depends on the CPU.

C no.S CUD

CU BOOL I, Q, M, D, L CU input: Up CounterS_CUD CD BOOL I, Q, M, D, L CD input: Down Counter

CU S BOOL I, Q, M, D, L, C Input for presetting the counter

CV

Q

CD

CV_BCDSPVR

PV WORD I, Q, M, D, L

or

constant

Count value in the range between 0and 999

or


R BOOL I, Q, M, D, L, C Reset input

CV WORD I, Q, M, D, L Current count value (integer format)

CV_BCD WORD I, Q, M, D, L Current count value (BCD format)

Q BOOL I, Q, M, D, L Status of the counter

Status Word Bits


A change in signal state from 0 to 1 atinput I0.2 sets counter C10 with the value55. If the signal state of input I0.0changes from 0 to 1, the value of counterC10 is incremented by 1, except whenthe value of counter C10 is already 999.If input I0.1 changes from 0 to 1, counterC10 is decremented by 1, except whenthe value of counter C10 is already 0. IfI0.3 changes from 0 to 1, the value ofC10 is set to 0. Q4.0 is 1, when C 10 is not equal to 0.

C10

S_CUD

CV

Q

CU

CD

CV_BCD

S

PV

R

I0.0

I0.1

I0.2

C#55

I0.3Q4.0

=

Figure 6-2 Up-Down Counter



6.3 Up Counter

A rising edge (change in signal state from 0 to 1) at input S of the UpCounter instruction sets the counter with the value at the Preset Value (PV)input. With a rising edge at input CU, the count value is incremented by 1when the count value is less than 999. The counter is reset by a rising edge atinput R. Resetting the counter sets the count value to 0.

A signal state check for 1 at output Q produces a result of 1 when the count isgreater than 0. The check produces a result of 0 when the count is equal to 0.

Table 6-3 Up Counter Box and Parameters with SIMATIC Mnemonics

FBD Box Parameter Data Type Memory Area Description


Z NrZV BOOL E, A, M, D, L ZV input: Up Counter

Z-Nr.Z VORW

S BOOL E, A, M, D, L, T, Z Input for presetting the counterZ_VORW

DEZ

ZV

DUALS

ZW


or

constant


or


QR R BOOL E, A, M, D, L, T, Z Reset input




Table 6-4 Up Counter Box and Parameters with International Mnemonics


C no.S CU


S_CU

CUCU BOOL I, Q, M, D, L CU input: Up Counter

CU S BOOL I, Q, M, D, L, T, C Input for presetting the counter

CV

Q

CV_BCD

S

R

PV


or

constant


or


R BOOL I, Q, M, D, L, T, C Reset input




Description



C79000-G7076-C566-01

Status Word Bits


A change in signal state from 0 to 1 atinput I0.2 sets counter C10 with the value901. If the signal state of I0.0 changesfrom 0 to 1, the value of counter C10 isincremented by 1, unless the value ofC10 is equal to 999. If I0.3 changes from0 to 1, the value of C 10 is set to 0. Thesignal state of output Q 4.0 is 1 if C10 isnot equal to 0.

C10

S_CU

CV

Q

CU

CV_BCD

S

PV

R

I0.0

I0.2

C#901

I0.3Q4.0

=

Figure 6-3 Up Counter



6.4 Down Counter

A rising edge (change in signal state from 0 to 1) at input S of the DownCounter instruction sets the counter with the value at the Preset Value input(PV). With a rising edge at input CD, the counter is decremented by 1 whenthe count value is greater than 0. The counter is reset by rising edge at inputR.

A signal state check for 1 at output Q produces a result of 1 when the count isgreater than 0; the check produces a result of 0 when the count is equal to 0.

Table 6-5 Down Counter Box and Parameters with SIMATIC Mnemonics


Z-Nr.Z RUECK


Z_RUECK ZR BOOL E, A, M, D, L ZR input: Down Counter

ZR S BOOL E, A, M, D, L, T, Z Input for presetting the counter

DEZ

Q

DUALS

ZW

R


or

constant


or


R BOOL E, A, M, D, L, T, Z Reset input




Table 6-6 Down Counter Box and Parameters with International Mnemonics


C no.S CD


S_CD CD BOOL I, Q, M, D, L CD input: Down Counter

CD S BOOL I, Q, M, D, L, T, C Input for presetting the counter

CV

Q

CV_BCD

S

PV

R


or

constant


or


R BOOL I, Q, M, D, L, T, C Reset input




Description



C79000-G7076-C566-01

Status Word Bits


A change in signal state from 0 to 1 at input I0.2sets counter C10 with the value 89. If the signalstate of input I0.0 changes from 0 to 1, the valueof counter C10 is decreased by 1, unless thevalue of counter C 10 is equal to 0. The signalstate of output Q 4.0 is 1 if counter C10 is notequal to 0. If I0.3 changes from 0 to 1, the valueof C 10 is set to 0.

Z10

CV

Q

CD

BCD

S

PV

R

I0.0

I0.2

C#901

I0.3Q4.0

=

S_CD

Figure 6-4 Down Counter



Integer Math Instructions


7.1 Add Integer 7-2

7.2 Add Double Integer 7-3

7.3 Subtract Integer 7-4

7.4 Subtract Double Integer 7-5

7.5 Multiply Integer 7-6

7.6 Multiply Double Integer 7-7

7.7 Divide Integer 7-8

7.8 Divide Double Integer 7-9

7.9 Return Fraction Double Integer 7-10

7.10 Evaluating the Bits of the Status Word with Integer MathInstructions

7-11

ChapterOverview

7


C79000-G7076-C566-01

7.1 Add Integer

A signal state of 1 at the Enable (EN) input activates the Add Integerinstruction. This instruction adds inputs IN1 and IN2. The result can bescanned at O. If the result is outside the permissible range for an integer, theOV and OS bit of the status word are 1 and the ENO is 0.

Table 7-1 Add Integer Box and Parameters


ADD IEN BOOL I, Q, M, D, L, T, C Enable input

ADD_I

ENIN1 INT I, Q, M, D, L

or constantFirst value for addition

IN1

IN2

OUT

ENO

IN2 INT I, Q, M, D, Lor constant

Second value for addition

IN2 ENOOUT INT I, Q, M, D, L Result of addition

ENO BOOL I, Q, M, D, L Enable output

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites x x x x x 0 x x 1

A signal state of 1 at input I 0.0 activates theADD_I box. The result of the addition MW0 +MW2 is entered in memory word MW10. Ifthe result is outside the permitted range foran integer or the signal state of input I 0.0 is0, output Q 4.0 is set to 0 and the instructionis not executed.

ADD_I

IN2

OUT

MW2

MW10IN1MW0

Instruction is executed (EN = 1):

EN

ENOQ 4.0

I 0.0

=

Figure 7-1 Add Integer

Description



7.2 Add Double Integer

A signal state of 1 at the Enable (EN) input activates the Add Double Integerinstruction. This instruction adds inputs IN1 and IN2. The result can bescanned at O. If the result is outside the permissible range for a doubleinteger, the OV and the OS bit of the status word are 1 and the ENO is 0.

Table 7-2 Add Double Integer Box and Parameters


ADD DIEN BOOL I, Q, M, D, L, T, C Enable input

ADD_DI

ENIN1 DINT I, Q, M, D, L or

constantFirst value for addition

IN1

IN2

OUT

ENO

IN2 DINT I, Q, M, D, L orconstant

Second value for addition

IN2 ENOOUT DINT I, Q, M, D, L Result of addition


Status Word Bits


A signal state of 1 at input I 0.0 activates theADD_DI box. The result of the addition MD0 +MD4 is entered in memory double wordMD10. If the result is outside the permittedrange for a double integer or the signal stateof input I 0.0 is 0, output Q 4.0 is set to 0 andthe instruction is not executed.


MD4

MD10MD0Q 4.0

I 0.0

=IN2

OUTIN1

EN

ENO

ADD_DI

Figure 7-2 Add Double Integer

Description



C79000-G7076-C566-01

7.3 Subtract Integer

A signal state of 1 at the Enable (EN) input activates the Subtract Integerinstruction. This instruction subtracts input IN2 from IN1. The result can bescanned at O. If the result is outside the permitted range for an integer, theOV and the OS bit of the status word are 1 and the ENO is 0.

Table 7-3 Subtract Integer Box and Parameters


SUB IEN BOOL I, Q, M, D, L, T, C Enable input

SUB_I

ENIN1 INT I, Q, M, D, L or

constantMinuend (value from which second valueis subtracted)

IN1

IN2

OUT

ENO

IN2 INT I, Q, M, D, L orconstant

Subtrahend (value subtracted from thefirst value)IN2 ENO

OUT INT I, Q, M, D, L Result of subtraction


Status Word Bits


A signal state of 1 at input I 0.0 activates theSUB_I box. The result of the subtraction MW0– MW2 is entered in memory word MW10. Ifthe result is outside the permitted range for aninteger or the signal state of input I 0.0 is 0,output Q 4.0 is set to 0 and the instruction isnot executed.


SUB_I

IN2

OUT

MW2

MW10IN1MW0

EN

ENOQ 4.0

I 0.0

=

Figure 7-3 Subtract Integer

Description



7.4 Subtract Double Integer

A signal state of 1 at the Enable (EN) input activates the Subtract DoubleInteger instruction. This instruction subtracts input IN2 from IN1. The resultcan be scanned at O. If the result is outside the permitted range for a doubleinteger, the OV and the OS bit of the status word are 1 and the ENO is 0.

Table 7-4 Subtract Double Integer Box and Parameters


SUB DIEN BOOL I, Q, M, D, L, T, C Enable input

SUB_DI


constantMinuend (value from which secondvalue is subtracted)

IN1

IN2

OUT

ENO


Subtrahend (value subtracted fromthe first value)

OUT DINT I, Q, M, D, L Result of subtraction


Status Word Bits


A signal state of 1 at input I 0.0 activates theSUB_DI box. The result of the subtractionMD0 – MD4 is entered in memory double wordMD10. If the result is outside the permittedrange for a double integer or the signal state ofinput I 0.0 is 0, output Q 4.0 is set to 0 and theinstruction is not executed.


MD4

MD10MD0Q 4.0

I 0.0

=IN2

OUTIN1

EN

ENO

SUB_DI

Figure 7-4 Subtract Double Integer

Description



C79000-G7076-C566-01

7.5 Multiply Integer

A signal state of 1 at the Enable (EN) input activates the Multiply Integerinstruction. This instruction multiplies input IN1 by IN2. The result is a32-bit integer that can be scanned at O. If the result is outside the permittedrange for a 16-bit integer, the OV and the OS bit of the status word are 1 andthe ENO is 0.

Table 7-5 Multiply Integer Box and Parameters


MUL IEN BOOL I, Q, M, D, L, T, C Enable input

MUL_I


constantMultiplicand (value that is multipliedby the second value)

IN1

IN2

OUT

ENO


Multiplier (value by which the firstvalue is multiplied)

IN2 ENOOUT DINT I, Q, M, D, L Result of the multiplication


Status Word Bits


A signal state of 1 at input I 0.0 activates theMUL_I box. The result of the multiplicationMW0 x MW2 is entered in memory double wordMD10. If the result is outside the permittedrange for a 16-bit integer or the signal state ofinput I 0.0 is 0, output Q 4.0 is set to 0 and theinstruction is not executed.


MUL_I

IN2

OUT

MW2

MD10IN1MW0

EN

ENOQ 4.0

I 0.0

=

Figure 7-5 Multiply Integer

Description



7.6 Multiply Double Integer

A signal state of 1 at the Enable (EN) input activates the Multiply DoubleInteger instruction. This instruction multiplies inputs IN1 and IN2. The resultcan be scanned at O. If the result is outside the permitted range for a doubleinteger, the OV and the OS bit of the status word are 1 and the ENO is 0.

Table 7-6 Multiply Double Integer Box and Parameters


MUL DIEN BOOL I, Q, M, D, L, T, C Enable input

MUL_DI


constantMultiplicand (value that is multipliedby the second value)

IN1

IN2

OUT

ENO


Multiplier (value by which the firstvalue is multiplied)

OUT DINT I, Q, M, D, L Result of the multiplication


Status Word Bits


A signal state of 1 at input I 0.0 activates theMUL_DI box. The result of the multiplicationMD0 x MD4 is entered in memory double wordMD10. If the result is outside the permittedrange for a double integer or the signal state ofinput I 0.0 is 0, output Q 4.0 is set to 0 and theinstruction is not executed.


MD4

MD10MD0Q 4.0

I 0.0

=IN2

OUTIN1

EN

ENO

MUL_DI

Figure 7-6 Multiply Double Integer

Description



C79000-G7076-C566-01

7.7 Divide Integer

A signal state of 1 at the Enable (EN) input activates the Divide Integerinstruction. This instruction divides input IN1 by IN2. The integer quotient(truncated result) can be scanned at O. The remainder cannot be scanned. Ifthe quotient is outside the permitted range for an integer, the OV and the OSbit of the status word are 1 and the ENO is 0.

Table 7-7 Divide Integer Box and Parameters


DIV IEN BOOL I, Q, M, D, L, T, C Enable input

DIV_I


constantDividend

IN1

IN2

OUT

ENO


Divisor

IN2 ENOOUT INT I, Q, M, D, L Result of division


Status Word Bits


A signal state of 1 at input I 0.0 activates theDIV_I box. The quotient of dividing MW0 byMW2 is entered in memory word MW10. If thequotient is outside the permitted range for aninteger or the signal state of input I 0.0 is 0,output Q 4.0 is set to 0 and the instruction isnot executed.


DIV_I

IN2

OUT

MW2

MW10IN1MW0

EN

ENOQ 4.0

I 0.0

=

Figure 7-7 Divide Integer

Description



7.8 Divide Double Integer

A signal state of 1 at the Enable (EN) input activates the Divide DoubleInteger instruction. This instruction divides input IN1 by IN2. The quotient(truncated result) can be scanned at O. The Divide Double Integer instructionstores the quotient as a single 32-bit value in DINT format. This instructiondoes not produce a remainder. If the quotient is outside the permitted rangefor a double integer, the OV and the OS bit of the status word are 1 and theENO is 0.

Table 7-8 Divide Double Integer Box and Parameters


DIV DIEN BOOL I, Q, M, D, L, T, C Enable input

DIV_DI


constantDividend

IN1

IN2

OUT

ENO


Divisor

OUT DINT I, Q, M, D, L Result of division


Status Word Bits


A signal state of 1 at input I 0.0 activates theDIV_DI box. The quotient of dividing MD0 byMD4 is entered in memory double wordMD10. If the quotient is outside the permittedrange for a double integer or the signal stateof input I 0.0 is 0, output Q 4.0 is set to 0 andthe instruction is not executed.


MD4

MD10MD0Q 4.0

I 0.0

=IN2

OUTIN1

EN

ENO

DIV_DI

Figure 7-8 Divide Double Integer

Description



C79000-G7076-C566-01

7.9 Return Fraction Double Integer

A signal state of 1 at the Enable (EN) input activates the Return FractionDouble Integer instruction. This instruction divides input IN1 by IN2. Theremainder (fraction) can be scanned at O. If the result is outside the permittedrange for a double integer, the OV and the OS bit of the status word are 1 andthe ENO is 0.

Table 7-9 Return Fraction Double Integer Box and Parameters


MODEN BOOL I, Q, M, D, L, T, C Enable input

MOD


constantDividend

IN1

IN2

OUT

ENO


Divisor

OUT DINT I, Q, M, D, L Remainder


Status Word Bits


A signal state of 1 at input I 0.0 activates theMOD box. The remainder (fraction) ofdividing MD0 by MD4 is stored in memorydouble word MD10. If the result is outsidethe permitted range for a double integer orthe signal state of input I 0.0 is 0, output Q4.0 is set to 0 and the instruction is notexecuted.


MD4

MD10MD0Q 4.0

I 0.0

=IN2

OUTIN1

EN

ENO

MOD

Figure 7-9 Return Fraction Double Integer

Description



7.10 Evaluating the Bits of the Status Word with Integer MathInstructions

The integer math instructions influence the following bits in the status word:

� CC1 and CC0

� OV

� OS

A dash (-) in the table means that the bit is not affected by the result of theinstruction.

Table 7-10 Signal State of the Status Word Bits (Result in Valid Range)

Valid Range of the Result Status Word Bits

Integers (16 and 32 bits) CC1 CC0 OV OS

0 (zero) 0 0 0 -

16 bits: -32 768 � result � 0 (negative number)32 bits: -2 147 483 648 � result � 0 (negative number)

0 1 0 -

16 bits: 32 767 � result �0 (positive number)32 bits: 2 147 483 647 � result �0 (positive number)

1 0 0 -

Table 7-11 Signal State of the Status Word Bits (Result not in Valid Range)

Invalid Range for the Result Status Word Bits

Integers (16 and 32 bits) CC1 CC0 OV OS

16 bits: result � 32 767 (positive number)32 bits: result � 2 147 483 647 (positive number)

1 0 1 1

16 bits: result � -32 768 (negative number)32 bits: result � -2 147 483 648 (negative number)

0 1 1 1

Table 7-12 Signal State of the Status Word Bits (Math Instructions with Integers(32 Bits) +D, /D and MOD)

Operation Status Word Bits

CC1 CC0 OV OS

+D: result = -4 294 967 296 0 0 1 1

/D or MOD: division by 0 1 1 1 1

Description



C79000-G7076-C566-01



Floating-Point Math Instructions


8.1 Overview 8-2

8.2 Add Real 8-3

8.3 Subtract Real 8-4

8.4 Multiply Real 8-5

8.5 Divide Real 8-6

8.6 Evaluating the Bits of the Status Word with Floating-PointInstructions

8-7

8.7 Forming the Absolute Value of a Floating-Point Number 8-8

8.8 Forming the Square (SQR) of a Floating-Point Number 8-9

8.9 Forming the Square Root (SQRT) of a Floating-PointNumber

8-10

8.10 Forming the Natural Logarithm of a Floating-Point Number 8-11

8.11 Forming the Exponential Value of a Floating-Point Number 8-12

8.12 Forming Trigonometric Functions of Angles asFloating-Point Numbers

8-13

ChapterOverview

8


C79000-G7076-C566-01

8.1 Overview

You can use the floating-point math instructions to perform the followingmath operations using two 32-bit IEEE floating-point numbers:

� Add

� Subtract

� Multiply

� Divide

The IEEE 32-bit floating-point numbers belong to the data type known asREAL. Using floating-point math, you can carry out the following operationswith one 32-bit IEEE floating-point number:

� Form the absolute value (ABS) of a floating-point number

� Form the square (SQR) or square root (SQRT) of a floating-point number

� Form the natural logarithm (LN) of a floating-point number

� Form the exponential value of a floating-point number (EXP) to base e (= 2.71828...)

� Form the following trigonometric functions of an angle, represented as a32-bit floating-point number:

– Form the sine of a floating-point number (SIN) and form the arc sineof a floating-point number (ASIN)

– Form the cosine of a floating-point number (COS) and form the arccosine of a floating-point number (ACOS)

– Form the tangent of a floating-point number (TAN) and form the arctangent of a floating-point number (ATAN)



8.2 Add Real

A signal state of 1 at the Enable input (EN) activates the Add Realinstruction. This instruction adds inputs IN1 and IN2. The result can bescanned at output OUT. If either of the inputs or the result is not afloating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0.

For more detailed information about evaluating the bits in the status word,refer to Section 8.6.

Table 8-1 Add Real Box and Parameters


ADD REN BOOL I, Q, M, D, L, T, C Enable input

ADD_R

IN1

EN

OUT

IN1 REAL I, Q, M, D, L orconstant

First number to be added

IN1

IN2

OUT

ENOIN2 REAL I, Q, M, D,or

constant LSecond number to be added

OUT REAL I, Q, M, D, L Result of addition


Status Word Bits


A signal state of 1 at input I0.0 activates theADD_R box. The result of the addition MD0+ MD4 is entered in memory double wordMD10. If either of the inputs or the result isnot a floating-point number and if the signalstate of I0.0 is 0, output Q4.0 is set to 0 andthe instruction is not executed.


MD4

MD10MD0Q4.0

I0.0

=IN2

OUTIN1

EN

ENO

ADD_R

Figure 8-1 Add Real

Description



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8.3 Subtract Real

A signal state of 1 at the Enable input (EN) activates the Subtract Realinstruction. This instruction subtracts input IN2 from IN1. The result can bescanned at output OUT. If either of the inputs or the result is not afloating-point number, the OV bit and the OS bit are set to 1 and ENO is setto 0.


Table 8-2 Subtract Real Box and Parameters


SUB REN BOOL I, Q, M, D, L, T, C Enable input

SUB_R

IN1

EN

OUT


Minuend (from which the secondvalue is subtracted)

IN1

IN2

OUT

ENOIN2 REAL I, Q, M, D, L or

constantSubtrahend (that is subtractedfrom the first value)

OUT REAL I, Q, M, D, L Result of subtraction


Status Word Bits


A signal state of 1 at input I0.0 activates theSUB_R box. The result of the subtractionMD0 – MD4 is entered in memory doubleword MD10. If either of the inputs or theresult is not a floating-point number and ifthe signal state of I0.0 is 0, output Q4.0 isset to 0 and the instruction is not executed.


MD4

MD10MD0Q4.0

I0.0

=IN2

OUTIN1

EN

ENO

SUB_R

Figure 8-2 Subtract Real

Description



8.4 Multiply Real

A signal state of 1 at the Enable input (EN) activates the Multiply Realinstruction. This instruction multiplies input IN1 by IN2. The result can bescanned at output OUT. If either of the inputs or the result is not afloating-point number, the OV bit and the OS bit are set to 1 and ENO is setto 0.


Table 8-3 Multiply Real Box and Parameters


MUL REN BOOL I, Q, M, D, L, T, C Enable input

MUL_R

IN1

EN

OUT


Multiplicand (value to bemultiplied)

IN1

IN2

OUT


constantMultiplier (value by which firstvalue is multiplied)

OUT REAL I, Q, M, D, L Result of multiplication


Status Word Bits


A signal state of 1 at input I0.0 activates theMUL_R box. The result of the multiplicationMD0 x MD4 is entered in memory doubleword MD10. If either of the inputs or theresult is not a floating-point number and if thesignal state of I0.0 is 0, output Q4.0 is set to0 and the instruction is not executed.


MD4

MD10MD0

Q4.0

I0.0

=IN2

OUTIN1

EN

ENO

MUL_R

Figure 8-3 Multiply Real

Description



C79000-G7076-C566-01

8.5 Divide Real

A signal state of 1 at the Enable input (EN) activates the Divide Realinstruction. This instruction divides input IN1 by IN2. The result can bescanned at output OUT. If either of the inputs or the result is not afloating-point number, the OV bit and the OS bit are set to 1 and ENO is setto 0.


Table 8-4 Divide Real Box and Parameters


DIV REN BOOL I, Q, M, D, L, T, C Enable input

DIV_R

IN1

ENIN1 REAL I, Q, M, D, L or

constantDividend (value to be divided bysecond value)

IN1

IN2

OUT


constantDivisor (value by which firstvalue is divided)

OUT REAL I, Q, M, D, L Result of division


Status Word Bits


A signal state of 1 at input I0.0 activates theDIV_R box. The result of dividing MD0 byMD4 is entered in memory double wordMD10. If either of the inputs or the result isnot a floating-point number and if the signalstate of I0.0 is 0, output Q4.0 is set to 0 andthe instruction is not executed.


MD4

MD10MD0Q4.0

I0.0

=IN2

OUTIN1

EN

ENO

DIV_R

Figure 8-4 Divide Real

Description



8.6 Evaluating the Bits of the Status Word with Floating-PointInstructions

Floating-point instructions affect the following bits in the status word:

� CC1 and CC0

� OV

� OS

A dash (–) in the table means that the bit is not affected by the result of theinstruction.

Table 8-5 Signal State of the Status Word Bits for Results of Instructions withFloating-Point Numbers (Result in the Valid Range)

Valid Range for Result Status Word Bits

Instruction with Floating-Point Numbers (32Bits)

CC1 CC0 OV OS

+0, –0 (zero) 0 0 0 –

–3.402823E+38 < result < –1.175494E–38 (negative number)

0 1 0 –

+1.175494E–38 < result < 3.402823E+38 (positive number)

1 0 0 –

Table 8-6 Signal State of the Status Word Bits for Results of Instructions withFloating-Point Numbers (Result outside the Valid Range)

Invalid Range for Result Status Word Bits

Instruction with Floating-Point Numbers (32Bits)

CC1 CC0 OV OS

–1.175494E–38 < result < – 1.401298E–45(negative number) below minimum

0 0 1 1

+1.401298E–45 < result < +1.175494E–38(positive number) below minimum

0 0 1 1

result < –3.402823E+38 (negative number) above maximum

0 1 1 1

result > 3.402823E+38 (positive number) above maximum

1 0 1 1

result < –3.402823E+38 or result > +3.402823E+38 not a floating-point number

1 1 1 1

Description



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8.7 Forming the Absolute Value of a Floating-Point Number

With the Form the Absolute Value of a Floating-Point Number instruction,you can form the absolute value of floating-point number.

Table 8-7 ABS Box and Parameters


ABSEN BOOL I, Q, M, D, L, T, C Enable input

ABS

EN OUTIN REAL I, Q, M, D, L or

constantInput value: floating-point number

IN ENO OUT REAL I, Q, M, D, L Output value: absolute value of thefloating-point number


Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites X – – – – 0 X X 1


MD8

MD12Q4.0

I0.0

=IN

OUTEN

ENO

ABS

If I0.0 = 1, the absolute value of MD8 isoutput at MD12.

MD8 = +6.234 x 10–3 results in MD12 = 6.234 x 10–3.

Output Q4.0 is 0 if the conversion is notexecuted (ENO = EN = 0).

Figure 8-5 Forming the Absolute Value of a Floating-Point Number

Description



8.8 Forming the Square (SQR) of a Floating-Point Number

With the Form the Square of a Floating-Point Number instruction, you cansquare a floating-point number. If either of the inputs or the result is not afloating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0.

Table 8-8 shows the SQR box and describes the parameters.

Table 8-8 SQR Box and Parameters

FBD Box Parameters DataType

Memory Area Description

EN BOOL I, Q, M, D, L, T, C Enable input

SQR

EN OUT

IN REAL I, Q, M, D, L orconstant

Number

EN

IN

OUT

ENO

OUT REAL I, Q, M, D, L Square of thenumberIN ENO


Status Word Bits



A signal state of 1 at input I0.0 activates theSQR box. The result of SQR (MD0) isentered in the memory double word MD10. IfMD0 is less than 0 or if either of the inputs orthe result is not a floating-point number and ifthe signal state of I0.0 is 0, output Q4.0 is setto 0.

MD0

MD10Q4.0

I0.0

=IN

OUTEN

ENO

SQR

Figure 8-6 Forming the Square of a Floating-Point Number

Description

Parameter



C79000-G7076-C566-01

8.9 Forming the Square Root (SQRT) of a Floating-Point Number

With the Form the Square Root of a Floating-Point Number instruction, youcan extract the square root of a floating-point number. This instructionreturns a positive result, if the value at the address is greater than “0”. Ifeither of the inputs or the result is not a floating-point number, the OV bitand OS bit are set to 1 and ENO is set to 0.

Table 8-9 shows the SQRT box and describes the parameters.

Table 8-9 SQRT Box and Parameters




SQRT


constantNumber

IN ENOOUT REAL I, Q, M, D, L Square root of

the number


Status Word Bits



A signal state of 1 at input I0.0 activates theSQRT box. The result of SQRT (MD0) isentered in memory double word MD10. IfMD0 is less than 0 or if either of the inputs orthe result is not a floating-point number and ifthe signal state of I0.0 is 0, output Q4.0 is setto 0.

MD0

MD10Q4.0

I0.0

=IN

OUTEN

ENO

SQRT

Figure 8-7 Forming the Square Root of a Floating-Point Number

Description

Parameter



8.10 Forming the Natural Logarithm of a Floating-Point Number

With the Form the Natural Logarithm of a Floating-Point Numberinstruction, you can form the natural logarithm of a floating-point number. Ifeither of the inputs or the result is not a floating-point number, the OV bitand OS bit are set to 1 and ENO is set to 0.

Table 8-10 LN Box and Parameters




LN

EN OUT


Number

EN

IN

OUT

ENO

OUT REAL I, Q, M, D, L Naturallogarithm of thenumber


Status Word Bits



A signal state of 1 at input I0.0 activates theLN box. The result of LN (MD0) is entered inmemory double word MD10. If MD0 is lessthan 0 or if either of the inputs or the result isnot a floating-point number and if the signalstate of I0.0 is 0, output Q4.0 is set to 0.MD0

MD10Q4.0

I0.0

=IN

OUTEN

ENO

LN

Figure 8-8 Forming the Natural Logarithm of a Floating-Point Number

Description



C79000-G7076-C566-01

8.11 Forming the Exponential Value of a Floating-Point Number

With the Form the Exponential Value of a Floating-Point Numberinstruction, you can form the exponential value of a floating-point number tobase e (= 2.71828...). If either of the inputs or the result is not afloating-point number, the OV bit and OS bit are set to 1 and ENO is set to 0.

Table 8-11 EXP Box and Parameters




EXP

EN OUT


Number

IN ENOOUT REAL I, Q, M, D, L Exponent of

the number


Status Word Bits



A signal state of 1 at input I0.0 activates theEXP box. The result of EXP (MD0) is enteredin memory double word MD10. If either of theinputs or the result is not a floating-pointnumber and if the signal state of E 0.0 is 0,output Q4.0 is set to 0.MD0

MD10Q4.0

I0.0

=IN

OUTEN

ENO

EXP

Figure 8-9 Forming the Exponential Value of a Floating-Point Number

Description



8.12 Forming Trigonometric Functions of Angles as Floating-PointNumbers

With the following instructions, you can form trigonometric functions ofangles represented as 32-bit IEEE floating-point numbers.

Instruction Meaning

SIN Form the sine of a floating-point number of an angle specified inradians.

ASIN Form the arc sine of a floating-point number . The result is an anglespecified in radians. The value is in the following range:

��/ 2 � arc sine � + � / 2, where � = 3.14...

COS Form the cosine of a floating-point number of an angle specified inradians.

ACOS Form the arc cosine of a floating-point number . The result is an anglespecified in radians. The value is in the following range:

0 � arc cosine� + �, where � = 3.14...

TAN Form the tangent of a floating-point number of an angle specified inradians.

ATAN Form the arc tangent of a floating-point number . The result is an anglespecified in radians. The value is in the following range:

��/ 2 � arc tangent � + � / 2, where � = 3.14...

Tables 8-12 through 8-17 show the SIN, ASIN, COS, ACOS, TAN and ATANboxes and describe the parameters.

Table 8-12 SIN Box and Parameters




SIN

EN OUT


Number

IN ENOOUT REAL I, Q, M, D, L Sine of the

number


Description

Parameter



C79000-G7076-C566-01

Table 8-13 ASIN Box and Parameters




ASIN


constantNumber

IN ENOOUT REAL I, Q, M, D, L Arc sine of the

number


Table 8-14 COS Box and Parameters



COSEN BOOL I, Q, M, D, L, T, C Enable input

COS


constantNumber

IN ENOOUT REAL I, Q, M, D, L Cosine of the

number


Table 8-15 ACOS Box and Parameters


Memory Area

Description


ACOS

EN OUT


Number

IN ENOOUT REAL I, Q, M, D, L Arc cosine of

the number


Table 8-16 TAN Box and Parameters


Memory Area

Description


TAN

EN OUT


Number

IN ENOOUT REAL I, Q, M, D, L Tangent of the

number




Table 8-17 ATAN Box and Parameters


Memory Area

Description


ATAN

EN OUT


Number

IN ENOOUT REAL I, Q, M, D, L Arc tangent of

the number


Status Word Bits



A signal state of 1 at input I0.0 activates theSIN box. The result of SIN (MD0) is entered inmemory double word MD10. If either of theinputs or the result is not a floating-pointnumber and if the signal state of I0.0 is 0,output Q4.0 is set to 0.MD0

MD10Q4.0

I0.0

=IN

OUTEN

ENO

SIN

Figure 8-10 Forming the Sine of a Floating-Point Number



C79000-G7076-C566-01



Comparison Instructions


9.1 Compare Integer 9-2

9.2 Compare Double Integer 9-3

9.3 Compare Real 9-4

ChapterOverview

9


C79000-G7076-C566-01

9.1 Compare Integer

The Compare Integer instruction compares two values on the basis of 16-bitfloating-point numbers. This instruction compares inputs IN1 and IN2according to the type of comparison you select from the list box. Thefollowing table lists the available types of comparison.

If the comparison is true, the result of logic operation (RLO) of thecomparison is 1. Otherwise, it is 0. You cannot negate the comparison resultitself, but you can achieve the same effect as negation by using the oppositecompare function.

Table 9-1 Types of Comparison for Integers

Type of Comparison Relational Operator

IN1 is equal to IN2. ==

IN1 is not equal to IN2. <>

IN1 is greater than IN2. >

IN1 is less than IN2. <

IN1 is greater than or equal to IN2. >=

IN1 is less than or equal to IN2. <=

Table 9-2 Compare Integer Box and Parameters (Example using Equal)


CMP== I

IN1 INTI, Q, M, D, L orconstant

First value to compare

IN1

IN2

== I

IN2 INTI, Q, M, D, L orconstant

Second value to compare

IN2Box output BOOL I, Q, M, D, L Result of comparison

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites x x x 0 – 0 1 x 1

Q4.0 is set when:

MW0 is equal to MW2 AND the signal stateis 1 at input I0.0

Comparison is true:

MW2

MW0Q4.0I0.0

S

CMP== I

IN2

IN1

&

Figure 9-1 Compare Integer

Description



9.2 Compare Double Integer

The Compare Double Integer instruction compares two values on the basis of32-bit floating-point numbers. This instruction compares inputs IN1 and IN2according to the type of comparison you select from the list box. Thefollowing table lists the available types of comparison.


Table 9-3 Types of Comparison for Double Integers








Table 9-4 Compare Double Integer Box and Parameters (Example using Not Equal)


CMP<> D

IN1 DINTI, Q, M, D, L orconstant


<> D

IN1

IN2

IN2 DINTI, Q, M, D, L orconstant



Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites – x x 0 – 0 x x 1

Q4.0 is set when:

� MD0 is not equal to MD4

� AND the signal state at at input I0.0 is 1

Comparison is true:

MD4

MD0 Q4.0

S

CMP<> D

IN2

IN1 I0.0

&

Figure 9-2 Compare Double Integer

Description



C79000-G7076-C566-01

9.3 Compare Real

The Compare Real instruction compares two values on the basis offloating-point numbers. This instruction compares inputs IN1 and IN2according to the type of comparison you select from the list box. Thefollowing table lists the available types of comparison.


Table 9-5 Types of Comparison for Floating-Point Numbers








Table 9-6 Compare Real Box and Parameters (Example using Less Than)


CMP< R

IN1 REALI, Q, M, D, L orconstant


IN1

IN2

< R

IN2 REALI, Q, M, D, L orconstant



Status Word Bits


writes – x x x x 0 x x 1

Q4.0 is set when:

� MD0 is less than MD4

� AND the signal state at input I0.0 is 1

Comparison is true:

MD4

MD0 Q4.0

S

CMP< R

IN2

IN1 I0.0

&

Figure 9-3 Compare Real

Description



Move and Conversion Instructions


10.1 Assign Value 10-2

10.2 BCD to Integer 10-3

10.3 Integer to BCD 10-4

10.4 Integer to Double Integer 10-5

10.5 BCD to Double Integer 10-6

10.6 Double Integer to BCD 10-7

10.7 Double Integer to Real 10-8

10.8 Ones Complement Integer 10-9

10.9 Ones Complement Double Integer 10-10

10.10 Twos Complement Integer 10-11

10.11 Twos Complement Double Integer 10-12

10.12 Negate Real Number 10-13

10.13 Round to Double Integer 10-14

10.14 Truncate Double Integer Part 10-15

10.15 Ceiling 10-16

10.16 Floor 10-17

ChapterOverview

10


C79000-G7076-C566-01

10.1 Assign Value

With the Assign Value instruction, you can assign specific values to variables.

The value specified at the IN input is copied to the address specified at theOUT output. ENO has the same signal state as EN.

With the MOVE box, the Assign Value instruction can copy all data typeswith lengths of 8, 16, or 32 bits. User-defined data types such as arrays orstructures must be be copied with the system function SFC20 “BLKMOV”(see the Reference Manual /235/).

The Assign Value instruction is affected by the Master Control Relay (MCR).For more information on how the MCR functions, see Section 16.5.

Table 10-1 Assign Value Box and Parameters



MOVE

EN OUT

IN All data types with alength of 8, 16 or32 bits

I, Q, M, D, L orconstant

Source value

IN ENOOUT All data types with a

length of 8, 16 or32 bits

I, Q, M, D, L Destination address


The instruction is executed, when input I0.0 is1. The content of MW10 is copied to data word12 of the open DB.

If the instruction is executed, Q4.0 is set to 1.

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites 1 – – – – 0 1 1 1


MW10

DBW12Q4.0

I0.0

=IN

OUTEN

ENO

MOVE

Figure 10-1 Assign Value

For information about integrated system functions that can be used as moveinstructions and that can assign a specific value to a variable or can copyvariables of varying types, refer to the Reference Manual /235/.

Description

Assigning Valuesto Variables



10.2 BCD to Integer

The BCD to Integer instruction reads the content of the input parameter IN asa three-digit number in binary coded decimal format (BCD, � 999) andconverts this number to an integer value. The output parameter OUT containsthe result.

ENO always has the same signal state as EN.

If any of the individual decimal numbers in the BCD number is in the invalidrange between 10 and 15, a BCD error occurs when the conversion isattempted, causing the following reaction:

� The CPU changes to the STOP mode. “BCD conversion error” is enteredin the diagnostic buffer with event ID number 2521.

� If OB121 is programmed, it is called.

For more detailed information about programming OB121, refer to theReference Manual /235/.

Table 10-2 BCD to Integer Box and Parameters


BCD IEN BOOL I, Q, M, D, L, T, C Enable input

BCD_I

EN

IN

OUT

ENO

IN WORD I, Q, M, D, L orconstant

Number in BCD format

IN ENO OUT INT I, Q, M, D, L Integer value of the BCD number


Status Word Bits


The conversion is executed if the signalstate of I0.0 is 1. The content of memoryword MW10 is read as a three-digitnumber in BCD format and converted toan integer. The result is stored in memoryword MW12. If the conversion is executed,the signal state of output Q4.0 is 1 (ENO =EN).


MW10

MW12Q4.0

I0.0

=IN

OUTEN

ENO

BCD_I

Figure 10-2 BCD to Integer

Description



C79000-G7076-C566-01

10.3 Integer to BCD

The Integer to BCD instruction reads the content of the input parameter IN asan integer value and converts this value to a three-digit number in binarycoded decimal format (BCD, � 999). The output parameter OUT containsthe result. If an overflow occurs, ENO is set to 0.

Table 10-3 Integer to BCD Box and Parameters


I BCDEN BOOL I, Q, M, D, L, T, C Enable input

I_BCD

EN OUTIN INT I, Q, M, D,or

constant LInteger

IN ENO OUT WORD I, Q, M, D, L BCD value of the integer


Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites x – – x x 0 x x 1

The conversion is executed if the signalstate of I0.0 is 1. The content of memoryword MW10 is read as an integer andconverted to a three-digit number in BCDformat. The result is stored in memoryword MW12. If an overflow occurs, thesignal state of output Q4.0 is 0. If thesignal state at input EN is 0 (meaningthat the conversion is not executed), thesignal state of output Q4.0 is also 0.


MW10

MW12Q4.0

I0.0

=IN

OUTEN

ENO

I_BCD

Figure 10-3 Integer to BCD

Description



10.4 Integer to Double Integer

The Integer to Double Integer instruction reads the content of the inputparameter IN as an integer and converts the integer to a double integer. Theoutput parameter OUT contains the result. ENO always has the same signalstate as EN.

Table 10-4 Integer to Double Integer Box and Parameters


I DIEN BOOL I, Q, M, D, L, T, C Enable input

I_DI

EN

IN

OUT

ENO

IN INT I, Q, M, D, L orconstant

Value to be converted

IN ENO OUT DINT I, Q, M, D, L Result


Status Word Bits


The conversion is executed if the signalstate of I0.0 is 1. The content of memoryword MW10 is read as an integer andconverted to a double integer. The result isstored in memory double word MD12. If theconversion is executed, the signal state ofoutput Q4.0 is 1 (ENO = EN).


MW10

MD12Q4.0

I0.0

=IN

OUTEN

ENO

I_DI

Figure 10-4 Integer to Double Integer

Description



C79000-G7076-C566-01

10.5 BCD to Double Integer

The BCD to Double Integer instruction reads the content of the inputparameter IN as a seven-digit number in binary coded decimal format (BCD,� 9,999,999) and converts this number to a double integer value. The outputparameter OUT contains the result.

ENO always has the same signal state as EN.

If any of the individual decimal numbers in the BCD number is in the invalidrange between 10 and 15, a BCD error occurs when the conversion isattempted, causing the following reaction:

� The CPU changes to the STOP mode. “BCD conversion error” is enteredin the diagnostic buffer with event ID number 2521.

� If OB121 is programmed, it is called.

For more detailed information about programming OB121, refer to theReference Manual /235/.

Table 10-5 BCD to Double Integer Box and Parameters


BCD DIEN BOOL I, Q, M, D, L, T, C Enable input

BCD_DI

EN OUTIN DWORD I, Q, M, D, L or

constantNumber in BCD format

IN ENO OUT DINT I, Q, M, D, L Double integer value of the BCDnumber


Status Word Bits

The conversion is executed if the signalstate of I0.0 is 1. The content of memorydouble word MD8 is read as a seven-digitnumber in BCD format and converted to adouble integer. The result is stored in MD12.If the conversion is executed, the signalstate of output Q4.0 is 1 (ENO = EN).



MD8

MD12Q4.0

I0.0

=IN

OUTEN

ENO

BCD_DI

Figure 10-5 BCD to Double Integer

Description



10.6 Double Integer to BCD

The Double Integer to BCD instruction instruction reads the content of theinput parameter IN as a double integer value and converts this value to aseven-digit number in BCD format (� 9 999 999). The output parameterOUT contains the result. If an overflow occurs, ENO is set to 0.

Table 10-6 Double Integer to BCD Box and Parameters


DI BCDEN BOOL I, Q, M, D, L, T, C Enable input

DI_BCD

EN OUTIN DINT I, Q, M, D, L or

constantDouble integer

IN ENO OUT DWORD I, Q, M, D, L BCD value of the double integer


Status Word Bits


The conversion is executed if the signalstate of I0.0 is 1. The content of memorydouble word MD8 is read as a doubleinteger and converted to a seven-digitnumber in BCD format. The result is storedin MD12. If an overflow occurs, the signalstate of output Q4.0 is 0. If the signal state atinput EN is 0 (meaning that the conversion isnot executed), the signal state of outputQ4.0 is also 0.


MD8

MD12Q4.0

I0.0

=IN

OUTEN

ENO

DI_BCD

Figure 10-6 Double Integer to BCD

Description



C79000-G7076-C566-01

10.7 Double Integer to Real

The Double Integer to Real instruction reads the content of the inputparameter IN as a double integer value and converts this value to a realnumber. The output parameter OUT contains the result. ENO always has thesame signal state as EN.

Table 10-7 Double Integer to Real Box and Parameters


DI REN BOOL I, Q, M, D, L, T, C Enable input

DI_R

EN

IN

OUT

ENO

IN DINT I, Q, M, D, L orconstant

Value to be converted

IN ENO OUT REAL I, Q, M, D, L Result


Status Word Bits

The conversion is executed if the signalstate of I0.0 is 1. The contents of memorydouble word MD8 is read as an integerand converted to a real number. The resultis stored in memory double word MD12. Ifthe conversion is not executed, the signalstate of output Q4.0 is 0 (ENO=EN).



MD8

MD12Q4.0

I0.0

=IN

OUTEN

ENO

DI_R

Figure 10-7 Double Integer to Real

Description



10.8 Ones Complement Integer

The Ones Complement Integer instruction reads the content of the inputparameter IN and performs the Boolean word logic instruction Exclusive OrWord (see Section 11.6) masked by FFFFH, so that the value of every bit isinverted. The output parameter OUT contains the result. ENO always has thesame signal state as EN.

Table 10-8 Ones Complement Integer Box and Parameters


INV IEN BOOL I, Q, M, D, L, T, C Enable input

INV_I

EN OUTIN INT I, Q, M, D, L or

constantInput value

IN ENO OUT INT I, Q, M, D, L Ones complement of the integer


Status Word Bits

The conversion is executed if the signalstate of I0.0 is 1. The value of every bit inMW8 is inverted.MW8 = 01000001 10000001 →MW10 = 10111110 01111110The conversion is not executed when thesignal state of I0.0 is 0 and Q4.0 is 0 (ENO= EN).



MW8

MW10Q4.0

I0.0

=IN

OUTEN

ENO

INV_I

Figure 10-8 Ones Complement Integer

Description



C79000-G7076-C566-01

10.9 Ones Complement Double Integer

The Ones Complement Double Integer instruction reads the content of theinput parameter IN and performs the Boolean word logic operation ExclusiveOr Word (see Section 11.6) masked by FFFF FFFFH, so that the value ofevery bit is inverted. The output parameter OUT contains the result. ENOalways has the same signal state as EN.

Table 10-9 Ones Complement Double Integer Box and Parameters


INV DIEN BOOL I, Q, M, D, L, T, C Enable input

INV_DI

EN

IN

OUT

ENO

IN DINT I, Q, M, D, L orconstant

Input value

IN ENO OUT DINT I, Q, M, D, L Ones complement of the doubleinteger


Status Word Bits

The conversion is executed if the signal state ofI0.0 is 1. The value of every bit of memory doubleword MD8 is inverted:

MD8 = F0FF FFF0 → MD12 = 0F00 000F

The conversion is not executed when I0.0 is 0 andQ4.0 is 0 (ENO = EN).



MD8

MD12Q4.0

I0.0

=IN

OUTEN

ENO

INV_DI

Figure 10-9 Ones Complement Double Integer

Description



10.10 Twos Complement Integer

The Twos Complement Integer instruction reads the content of the inputparameter IN and changes the sign (for example, from a positive value to anegative value). The output parameter OUT contains the result. The signalstate of EN is and ENO is always the same except when the signal state ofEN is 1 and an overflow occurs. In this case, the signal state of ENO is 0.

Table 10-10 Twos Complement Integer Box and Parameters


NEG IEN BOOL I, Q, M, D, L, T, C Enable input

NEG_I

EN OUTIN INT I, Q, M, D, L or

constantInput value

IN ENO OUT INT I, Q, M, D, L Twos complement of the integer


Status Word Bits

The conversion is executed if the signal stateof I0.0 is 1. The value of memory word MW8is output at OUT to memory word MW10 withthe opposite sign:

Example:MW8 = +10 → MW10 = – 10

If the signal state of EN is 1 and an overflowoccurs, ENO is 0 and the signal state of Q4.0is 0. If the conversion is not executed,Q4.0 is 0 (ENO = EN).



MW8

MW10Q4.0

I0.0

=IN

OUTEN

ENO

NEG_I

Figure 10-10 Twos Complement Integer

Description



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10.11 Twos Complement Double Integer

The Twos Complement Double Integer instruction reads the content of theinput parameter IN and changes the sign (for example, from a positive valueto a negative value). The output parameter OUT contains the result. Thesignal state of EN is and ENO is always the same except when the signalstate of EN is 1 and an overflow occurs. In this case, the signal state of ENOis 0.

Table 10-11 Twos Complement Double Integer Box and Parameters


NEG DIEN BOOL I, Q, M, D, L, T, C Enable input

NEG_DI

EN OUTIN DINT I, Q, M, D, L or

constantInput value

IN ENO OUT DINT I, Q, M, D, L Twos complement of the doubleinteger


Status Word Bits

The conversion is executed if the signal state of I0.0is 1. The value of memory double word MD8 isoutput at OUT to memory double word MD10 withthe opposite sign:

Example:MD8 = +60 000 → MW10 = – 60 000

If the signal state of EN is 1 and an overflow occurs,ENO is 0 and the signal state of Q4.0 is 0. If theconversion is not executed, Q4.0 is 0 (ENO = EN).



MD8

MD12I0.0

=IN

OUTEN

ENO

NEG_DI

Q4.0

Figure 10-11 Twos Complement Double Integer

Description



10.12 Negate Real Number

The Negate Real Number instruction reads the content of the input parameterIN and inverts the sign bit (the instruction changes the sign of the number. forexample, from 0 for plus to 1 for minus). The bits of the exponent andmantissa remain the same. The output parameter OUT provides the result.ENO always has the same signal state as EN except when the signal state ofEN is 1 and an overflow occurs. In this case, the signal state of ENO is 0.

Table 10-12 Negate Real Number Box and Parameters


NEG REN BOOL I, Q, M, D, L, T, C Enable input

NEG_R

EN

IN

OUT

ENO


Input value

IN ENO OUT REAL I, Q, M, D, L The result is the negated input value.


Status Word Bits

The conversion is executed if the signal state ofI0.0 is 1. The value of memory double word MD8is output at OUT to memory double word MD12with the opposite sign as shown in the followingexample:

MD8 = + 6.234 x 10–3 → MD12 = – 6.234 x 10–3

If the conversion is not executed, the signal stateof output Q4.0 is 0 (ENO = EN).


BR CC1 CC0 OV OS OR STA RLO FCwrites x – – – – 0 x x 1

MD8

MD12Q4.0

I0.0

=IN

OUTEN

ENO

NEG_R

Figure 10-12 Negate Real Number

Description



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10.13 Round to Double Integer

The Round to Double Integer instruction reads the content of the inputparameter IN as a real number and converts this number to a double integer.The result is the nearest integer and is contained in output parameter OUT. Ifthe fraction is x.5, the number is rounded to the even number (for example:2.5 –> 2, 1.5 –> 2). If an overflow occurs, ENO is set to 0. If the input valueis not a real number, the OV bit and the OS bit have the value 1 and ENO hasthe value 0.

Table 10-13 Round to Double Integer Box and Parameters


ROUNDEN BOOL I, Q, M, D, L, T, C Enable input

ROUND


constantValue to be rounded

IN ENO OUT DINT I, Q, M, D, L IN rounded to the next doubleinteger


Status Word Bits


The conversion is executed if I0.0 is 1. Thecontent of memory double word MD8 is readas a real number and converted to a doubleinteger. The result of this round-to-nearestfunction is stored in memory double wordMD12. If an overflow occurs, the signal stateof output Q4.0 is 0. If the signal state at inputEN is 0 (meaning that the conversion is notexecuted), the signal state of output Q4.0 isalso 0.


MD8

MD12Q4.0

I0.0

=IN

OUTEN

ENO

ROUND

Figure 10-13 Round to Double Integer

Description



10.14 Truncate Double Integer Part

The Truncate Double Integer Part instruction reads the content of the inputparameter IN as a real number and converts this number to a double integer(for example 1.5 becomes 1). The result is the integer component of the realnumber). The output parameter OUT contains the result. If an overflowoccurs, ENO is set to 0. If the input value is not a real number, the OV bitand the OS bit have the value 1 and ENO has the value 0.

Table 10-14 Truncate Double Integer Part Box and Parameters


TRUNCEN BOOL I, Q, M, D, L, T, C Enable input

TRUNC

EN

IN

OUT

ENO


Value to be truncated

IN ENO OUT DINT I, Q, M, D, L Integer component of IN


Status Word Bits


The conversion is executed if the signalstate of I0.0 is 1. The content of memorydouble word MD8 is read as a real numberand converted to a double integeraccording to the “round to zero principle”.The integer component is the result and isstored in memory double word MD12. If anoverflow occurs, the signal state of outputQ4.0 is 0. If the signal state at input EN is 0(meaning that the conversion is notexecuted), the signal state of output Q4.0 isalso 0.


MD8

MD12Q4.0

I0.0

=IN

OUTEN

ENO

TRUNC

Figure 10-14 Truncate Double Integer Part

Description



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10.15 Ceiling

The Ceiling instruction reads the content of the input parameter IN as a realnumber and converts this number to a double integer (for example: +1.2 –>+2; –1.5 –> –1). The result is the lowest integer which is greater than orequal to the specified real number. The output parameter OUT contains theresult. If an overflow occurs, ENO is 0. If the input value is not a realnumber, the OV bit and the OS bit have the value 1 and ENO has the value 0.

Table 10-15 Ceiling Box and Parameters


CEILEN BOOL I, Q, M, D, L, T, C Enable input

CEIL


constantValue to be converted



Status Word Bits


The conversion is executed if I0.0 is 1.Thecontent of memory double word MD8 is read asa real number and converted to a doubleinteger by rounding to the next higher (or equal)whole number. The result is stored in memorydouble word MD12. If an overflow occurs, thesignal state of output Q4.0 is 0. If the signalstate at input EN is 0 (meaning that theconversion is not executed), the signal state ofoutput Q4.0 is also 0.


MD8

MD12Q4.0

I0.0

=IN

OUTEN

ENO

CEIL

Figure 10-15 Ceiling

Description



10.16 Floor

The Floor instruction reads the content of the input parameter IN as a realnumber and converts this number to a double integer. The result is thehighest integer which is lower than or equal to the specified real number. Theoutput parameter OUT contains the result. If an overflow occurs, ENO is setto 0. If the input value is not a real number, the OV bit and the OS bit havethe value 1 and ENO has the value 0.

Table 10-16 Floor Box and Parameters


FLOOREN BOOL I, Q, M, D, L, T, C Enable input

FLOOR


constantValue to be converted



Status Word Bits


The conversion is executed if I0.0 is 1. Thecontent of memory double word MD8 is read asa real number and converted to a doubleinteger by rounding to the next lower (or equal)whole number. The result is stored in memorydouble word MD12. If an overflow occurs, thesignal state of output Q4.0 is 0. If the signalstate at input EN is 0 (meaning that theconversion is not executed), the signal state ofoutput Q4.0 is also 0.


MD8

MD12Q4.0

I0.0

=IN

OUTEN

ENO

FLOOR

Figure 10-16 Floor

Description



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Word Logic Instructions


11.1 Overview 11-2

11.2 (Word) AND Word 11-3

11.3 (Word) AND Double Word 11-4

11.4 (Word) OR Word 11-5

11.5 (Word) OR Double Word 11-6

11.6 (Word) Exclusive OR Word 11-7

11.7 (Word) Exclusive OR Double Word 11-8

ChapterOverview

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11.1 Overview

Word logic instructions compare pairs of words (16 bits) and double words(32 bits) bit by bit, according to Boolean logic. The following instructionsare available for performing word logic operations:

� (Word) AND Word: This instruction combines two words bit by bit,according to the AND truth table.

� (Word) AND Double Word: This instruction combines two double wordsbit by bit, according to the AND truth table.

� (Word) OR Word: This instruction combines two words bit by bit,according to the OR truth table.

� (Word) OR Double Word: This instruction combines two double words bitby bit, according to the OR truth table.

� (Word) Exclusive OR Word: This instruction combines two words bit bybit, according to the Exclusive OR truth table.

� (Word) Exclusive OR Double Word: This instruction combines twodouble words bit by bit, according to the Exclusive OR truth table.

What AreWord LogicInstructions?



11.2 (Word) AND Word

The (Word) AND Word instruction is activated by signal state 1 at the Enableinput (EN) and combines the two digital values at inputs IN1 and IN2 bit bybit according to the AND truth table. The values are interpreted as pure bitpatterns. The result can be scanned at output OUT. ENO has the same signalstate as EN.

The value of the result at output OUT relative to 0 affects the CC1 bit of thestatus word as follows:

� If the result at output OUT is not equal to 0, the CC1 bit of the statusword is set to 1 .

� If the result at output OUT is 0, the CC1 bit of the status word is set to 0.

Table 11-1 (Word) AND Word Box and Parameters


WAND WEN BOOL I, Q, M, D, L, T, C Enable input

WAND_W

ENIN1 WORD I, Q, M, D, L or

constantFirst value of the logic operation

IN1

IN2

OUT

ENO

IN2 WORD I, Q, M, D, L orconstant

Second value of the logic operation

ENOOUT WORD I, Q, M, D, L Result of the logic operation


Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites 1 x 0 0 – x 1 1 1

The instruction is activated when thesignal state of I0.0 is 1. Only bits 0 to 3are relevant, all other bits of MW0 aremasked.IN1 = 0101010101010101IN2 = 0000000000001111OUT = 0000000000000101

Q4.0 is 1 if the instruction is executed.

WAND_W

IN2

OUT

EN

ENO2# 0000000000001111

MW2IN1MW0


Q4.0

I0.0

=

Figure 11-1 (Word) AND Word

Description



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11.3 (Word) AND Double Word

The (Word) AND Double Word instruction is activated by signal state 1 at theEnable input (EN) and combines the two digital values at inputs IN1 and IN2bit by bit according to the AND truth table. The values are interpreted aspure bit patterns. The result can be scanned at output OUT. ENO has thesame signal state as EN.




Table 11-2 (Word) AND Double Word Box and Parameters


WAND DWEN BOOL I, Q, M, D, L, T, C Enable input

WAND_DW

ENIN1 DWORD I, Q, M, D, L or


IN1

IN2

OUT

ENO

IN2 DWORD I, Q, M, D, L orconstant


IN2 ENOOUT DWORD I, Q, M, D, L Result of the logic operation


Status Word Bits


The instruction is activated when I0.0 is 1. Only bits 0to 11 are relevant, all other bits of MD4 are masked.IN1 = 0101010101010101 0101010101010101IN2 = 0000000000000000 0000111111111111OUT = 0000000000000000 0000010101010101


WAND_DW

IN2

OUT

EN

ENODW#16#FFF

MD4IN1MD0


Q4.0

I0.0

=

Figure 11-2 (Word) AND Double Word

Description



11.4 (Word) OR Word

The (Word) OR Word instruction is activated by signal state 1 at the Enableinput (EN) and combines the two digital values at inputs IN1 and IN2 bit bybit according to the OR truth table. The values are interpreted as pure bitpatterns. The result can be scanned at output OUT. ENO has the same signalstate as EN.




Table 11-3 (Word) OR Word Box and Parameters


WOR WEN BOOL I, Q, M, D, L, T, C Enable input

WOR_W



IN1

IN2

OUT

ENO

IN2 WORD I, Q, M, D,orconstant L


OUT WORD I, Q, M, D, L Result of the logic operation


Status Word Bits


The instruction is activated when I0.0 is 1. Thebits in MW0 and in the constant are ORed andbits 0 to 3 set to 1, all other bits of MW0 areentered unchanged in MW2

IN1 = 0101010101010101IN2 = 0000000000001111OUT = 0101010101011111


WOR_W

IN2

OUT

EN

ENO2#0000000000001111

MW2IN1MW0


Q4.0

I0.0

=

Figure 11-3 (Word) OR Word

Description



C79000-G7076-C566-01

11.5 (Word) OR Double Word

The (Word) OR Double Word instruction is activated by signal state 1 at theEnable input (EN) and combines the two digital values at inputs IN1 and IN2bit by bit according to the OR truth table. The values are interpreted as purebit patterns. The result can be scanned at output OUT. ENO has the samesignal state as EN.




Table 11-4 (Word) OR Double Word Box and Parameters


WOR DWEN BOOL I, Q, M, D, L, T, C Enable input

WOR_DW



IN1

IN2

OUT

ENO



ENOOUT DWORD I, Q, M, D, L Result of the logic operation


Status Word Bits


The instruction is activated when I0.0 is 1. The bits inMD0 and in the constant are ORed and bits 0 to 11set to 1, all other bits of MD0 are entered unchangedin MD4IN1 = 0101010101010101 0101010101010101IN2 = 0000000000000000 0000111111111111OUT = 0101010101010101 0101111111111111


WOR_DW

IN2

OUT

EN

ENODW#16#FFF

MD4IN1MD0


Q4.0

I0.0

=

Figure 11-4 (Word) OR Double Word

Description



11.6 (Word) Exclusive OR Word

The (Word) Exclusive OR Word instruction is activated by signal state 1 at theEnable input (EN) and combines the two digital values at inputs IN1 and IN2bit by bit according to the EXCLUSIVE OR truth table. The values areinterpreted as pure bit patterns. The result can be scanned at output OUT.ENO has the same signal state as EN.

The value of the result at output OUT relative to 0 affects the CC1 bit in thestatus word as follows:

� If the result at output OUT is not equal to 0, the CC1 bit in the statusword is set to 1.

� If the result at output OUT is 0, the CC1 bit in the status word is set to 0.

Table 11-5 (Word) Exclusive OR Word Box and Parameters


WXOR WEN BOOL I, Q, M, D, L, T, C Enable input

WXOR_W



IN1

IN2

OUT

ENO

IN2 WORD I, Q, M, D, L orconstant


OUT WORD I, Q, M, D, L Result of the logic operation


Status Word Bits


WXOR_W

IN2

OUT

EN

ENO2#0000000000001111

MW2IN1MW0


The instruction is activated when input I0.0is 1.

IN1 = 0101010101010101IN2 = 0000000000001111OUT = 0101010101011010


Q4.0

I0.0

=

Figure 11-5 (Word) Exclusive OR Word

Description



C79000-G7076-C566-01

11.7 (Word) Exclusive OR Double Word

The (Word) Exclusive OR Double Word instruction is activated by signal state1 at the Enable input (EN) and combines the two digital values at inputs IN1and IN2 bit by bit according to the EXCLUSIVE OR truth table. The valuesare interpreted as pure bit patterns. The result can be scanned at output OUT.ENO has the same signal state as EN.

The value of the result at output OUT relative to 0 affects the CC1 bit in thestatus word as follows:

� If the result at output OUT is not equal to 0, the CC1 bit in the statusword is set to 1.

� If the result at output OUT is 0, the CC1 bit in the status word is set to 0.

Table 11-6 (Word) Exclusive OR Double Word Box and Parameters


WXOR DWEN BOOL I, Q, M, D, L, T, C Enable input

WXOR_DW



IN1

IN2

OUT

ENO



OUT DWORD I, Q, M, D, L Result of the logic operation


Status Word Bits


The instruction is activated when input I0.0 is 1.

IN1 = 0101010101010101 0101010101010101IN2 = 0000000000000000 0000111111111111OUT = 0101010101010101 0101101010101010


WXOR_DW

IN2

OUT

EN

ENODW#16#FFF

MD4IN1MD0


Q4.0

I0.0

=

Figure 11-6 (Word) Exclusive OR Double Word

Description



Shift and Rotate Instructions


12.1 Shift Instructions 12-2

12.2 Rotate Instructions 12-10

ChapterOverview

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12.1 Shift Instructions

You can use the Shift instructions to move the contents of input IN bit by bitto the left or the right (see Section 2.3). Shifting n bits to the left multipliesthe contents of input IN by 2 to the power n (2n); shifting n bits to the rightdivides the contents of input IN by 2 to the power n (2n). For example, if youshift the binary equivalent of the decimal value 3 to the left by 3 bits, youobtain the binary equivalent of the decimal value 24. If you shift the binaryequivalent of the decimal value 16 to the right by 2 bits, you obtain thebinary equivalent of the decimal value 4.

The number that you supply for input parameter N indicates the number ofbits by which the value is shifted. The bit places that are vacated by the Shiftinstruction are either padded with zeros or with the signal state of the sign bit(0 stands for positive and 1 stands for negative). The signal state of the bitthat is shifted last is loaded into the CC1 bit of the status word (seeSection 2.3). The CC0 and OV bits of the status word are reset to 0. You canuse jump instructions to evaluate the CC1 bit.

The following Shift instructions are available:

� Shift Left Word, Shift Left Double Word

� Shift Right Word, Shift Right Double Word

� Shift Right Integer, Shift Right Double Integer

A signal state of 1 at the Enable input (EN) activates the Shift Left Wordinstruction. This instruction shifts bits 0 to 15 of input IN bit by bit to theleft.

Input N specifies the number of bits by which to shift the value. If N ishigher than 16, the command writes 0 to output OUT and sets the CC0 andOV bits of the status word to 0. The bit positions at the right are padded withzeros. The result of the shift operation can be scanned at output OUT.

The operation triggered by this instruction always resets the CC0 and OV bitsof the status word to 0 if the value of N is not equal to 0. ENO has the samesignal state as EN.

Description

Shift Left Word



15... ...8 7... ...0

0 1 0 1

0 1 0 1 0 1 0 10 0 0 0

0 1 0 01 1 0 1

IN

N

OUT 0 0 0 0

1 1 1 1

0 0 0 0 1 1

6 places

Parameters:

These six bitsare lost.

The vacated placesare padded withzeros.

Figure 12-1 Shifting the Bits of Input IN Six Bits to the Left

Table 12-1 Shift Left Word Box and Parameters


EN BOOL I, Q, M, L, D, T, C Enable input

SHL_W

ENIN WORD I, Q, M, L, D Value to be shifted

IN

EN

OUTN WORD I, Q, M, L, D Number of bit positions by which

the value will be shifted

N ENO OUT WORD I, Q, M, L, D Result of the shift instructionENOENO BOOL I, Q, M, L, D Enable output

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites x x x x – x x x 1

The instruction is activated if the signalstate of I0.0 is 1.

Memory word MW0 is shifted to the left bythe number of bits specified in memoryword MW2.

The result is entered in memory wordMW4.

Q4.0

SHL_W

N

OUT

EN

ENOMW2

IN


MW4MW0

I0.0

S

Figure 12-2 Shift Left Word



C79000-G7076-C566-01

A signal state of 1 at the Enable input (EN) activates the Shift Left DoubleWord instruction. This instruction shifts bits 0 to 31 of input IN bit by bit tothe left. Input N specifies the number of bits by which the value will beshifted. If N is greater than 32, the command writes 0 to output OUT and setsthe CC0 and OV bits of the status word to 0. The vacated bit positions at theright are padded with zeros. The result of the shift operation can be scannedat output OUT.

The operation triggered by this instruction always resets the CC0 and OV bitsof the status word to 0 if the value of N is not equal to 0. ENO has the samesignal state as EN.

Table 12-2 Shift Left Double Word Box and Parameters


SHL DWEN BOOL I, Q, M, L, D, T, C Enable input

SHL_DW

EN IN DWORD I, Q, M, L, D Value to be shifted

IN

N

OUT

ENO

N WORD I, Q, M, L, D Number of bit positions by whichthe value will be shifted

N ENO OUT DWORD I, Q, M, L, D Result of the shift instruction

ENO BOOL I, Q, M, L, D Enable output

Status Word Bits



Memory double word MD0 is shifted tothe left by the number of bits specifiedin memory word MW4.

The result is entered in memorydouble word MD10.

SHL_DW

N

OUT

EN

ENOMW4

IN


MD10MD0Q4.0

I0.0

S

Figure 12-3 Shift Left Double Word

Shift Left DoubleWord



A signal state of 1 at the Enable input (EN) activates the Shift Right Wordinstruction. This instruction shifts bits 0 to 15 of input IN bit by bit to theright. Bits 16 to 31 are not affected. Input N specifies the number of bits bywhich the value will be shifted. If N is greater than 16, the command writes 0to output OUT and resets the CC0 and OV bits of the status word to 0. Thevacated bit positions at the left are padded with zeros. The result of the shiftoperation can be scanned at output OUT.

The operation triggered by this instruction always resets the CC0 and OV bitsof the status word to 0 if N is not equal to zero. ENO has the same signalstate as EN.

Table 12-3 Shift Right Word Box and Parameters


SHR WEN BOOL I, Q, M, L, D, T, C Enable input

SHR_W

ENIN WORD I, Q, M, L, D Value to be shifted

IN

EN



N ENO OUT WORD I, Q, M, L, D Result of the shift instruction


Status Word Bits



Memory word MW0 is shifted to the rightby the number of bits specified in memoryword MW2.


SHR_W

N

OUT

EN

ENOMW2

IN


MW4MW0Q4.0

I0.0

S

Figure 12-4 Shift Right Word

Shift Right Word



C79000-G7076-C566-01

A signal state of 1 at the Enable input (EN) activates the Shift Right DoubleWord instruction. This instruction shifts bits 0 to 31 of input IN bit by bit tothe right. Input N specifies the number of bits by which the value will beshifted. If N is higher than 32, the command writes 0 to output OUT andresets the CC0 and OV bits of the status word to 0. The vacated bit positionsat the left are padded with zeros. The result of the shift operation can bescanned at output OUT.


1 1 1

31... ...16 15... ...0

1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1

0 1 0 10 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1

3 places

The vacated bitpositions are paddedwith zeros.

These threebits are lost.

IN

N

OUT

Parameters:

Figure 12-5 Shifting Bits of Input IN Three Bits to the Right

Table 12-4 Shift Right Double Word Box and Parameters


SHR DWEN BOOL I, Q, M, L, D, T, C Enable input

SHR_DW

ENIN DWORD I, Q, M, L, D Value to be shifted

IN

EN



N ENO OUT DWORD I, Q, M, L, D Result of the shift instruction


Shift Right DoubleWord



Status Word Bits



Memory double word MD0 is shifted tothe right by the number of bits specifiedin memory word MW4.

The result is entered in MD10.

SHR_DW

N

OUT

MW4

IN


MD10MD0

EN

ENOQ4.0

I0.0

S

Figure 12-6 Shift Right Double Word

A signal state of 1 at the Enable input (EN) activates the Shift Right Integerinstruction. This instruction shifts bits 0 to 15 of input IN bit by bit to theright. Input N specifies the number of bits by which the value will be shifted.If N is higher than 16, the command behaves as if N were 16. The bitpositions at the left are padded according to the signal state of bit 15 (the signof an integer number). They are filled with zeros if the number is positive,and with ones if it is negative. The result of the shift operation can bescanned at output OUT.


15... ...8 7... ...0

1 0 1 0

0 0 0 0 1 0 1 01 0 1 0

1 1 1 11 1 1 1 0 0 0 0

1 1 1 1

4 places

The vacated bitpositions are paddedwith the signal state ofthe sign bit.

1 0 1 0

These four bitsare lost.

Sign bit

IN

N

OUT

Parameters:

Figure 12-7 Shifting Bits of Input IN Four Bits to the Right with Sign

Shift Right Integer



C79000-G7076-C566-01

Table 12-5 Shift Right Integer Box and Parameters


SHR IEN BOOL I, Q, M, L, D, T, C Enable input

SHR_I

ENIN INT I, Q, M, L, D Value to be shifted

IN

EN



N ENO OUT INT I, Q, M, L, D Result of the shift instruction


Status Word Bits



Memory word MW0 is shifted to the rightby the number of bits specified in memoryword MW2.


SHR_I

N

OUT

MW2

IN


MW4MW0

EN

ENO

Q4.0

I0.0

S

Figure 12-8 Shift Right Integer



A signal state of 1 at the Enable input (EN) activates the Shift Right DoubleInteger instruction. This instruction shifts the entire contents of input IN bitby bit to the right. Input N specifies the number of bits by which the valuewill be shifted. If N is higher than 32, the command behaves as if N were 32.The bit positions at the left are padded according to the signal state of bit 31(the sign of a double integer number). They are filled with zeros if thenumber is positive, and with ones if it is negative. The result of the shiftoperation can be scanned at output OUT.


Table 12-6 Shift Right Double Integer Box and Parameters


EN BOOL I, Q, M, L, D, T, C Enable input

SHR_DI

ENIN DINT I, Q, M, L, D Value to be shifted

IN

EN



N ENO OUT DINT I, Q, M, L, D Result of the shift instruction


Status Word Bits



Memory double word MD0 is shifted tothe right by the number of bits specifiedin memory word MW4.

The result is entered in memory doubleword MD10.

SHR_DI

N

OUT

MW4

IN


MD10MD0

EN

ENO

Q4.0

I0.0

S

Figure 12-9 Shift Right Double Integer

Shift Right DoubleInteger



C79000-G7076-C566-01

12.2 Rotate Instructions

You can use the Rotate instructions to rotate the entire contents of input INbit by bit to the left or to the right. The vacated bit positions are filled withthe signal states of the bits that are shifted out of input IN.

The number that you specify for input parameter N is the number of bits bywhich the value will be rotated.

Depending on the instruction, rotation uses the CC1 bit of the status word(see Section 2.3). The CC0 bit of the status word is reset to 0.

The following Rotate instructions are available:

� Rotate Left Double Word

� Rotate Right Double Word

A signal state of 1 at the Enable input (EN) activates the Rotate Left DoubleWord instruction. This instruction rotates the entire contents of input IN bitby bit to the left. Input N specifies the number of bits by which to rotate. If Nis higher than 32, the double word is rotated ((N–1) modulo 32) +1) places.The bit positions at the right are filled with the signal states of the bitsrotated. The result of the rotate operation can be scanned at output OUT.


1 1 1

31... ...16 15... ...0

1 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 1 1 11 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1

3 places

The signal states of the threebits that are shifted out areinserted in the vacatedpositions.

These three bits are lost.

IN

N

OUT

Parameters:

Figure 12-10 Rotating Bits of Input IN Three Bits to the Left

Description

Rotate Left DoubleWord



Table 12-7 Rotate Left Double Word Box and Parameters


ROL DWEN BOOL I, Q, M, L, D, T, C Enable input

ROL_DW

ENIN DWORD I, Q, M, L, D Value to be rotated

IN

EN


the value will be rotated

N ENO OUT DWORD I, Q, M, L, D Result of the rotate instruction


Status Word Bits



Memory double word MD0 is rotated to theleft by the number of bits specified inmemory word MW4.


ROL_DW

N

OUT

EN

ENOMW4

IN


MD10MD0Q4.0

I0.0

S

Figure 12-11 Rotate Left Double Word

A signal state of 1 at the Enable input (EN) activates the Rotate Right DoubleWord instruction. This instruction rotates the entire contents of input IN bitby bit to the right. Input N specifies the number of bits by which the valuewill be rotated. The value of N can be between 0 and 31. If N is higher than32, the double word is rotated ((N–1) modulo 32) +1) places. The bitpositions at the left are filled with the signal states of the bits rotated. Theresult of the rotate operation can be scanned at output OUT.


Rotate RightDouble Word



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1 0 1

31... ...16 15... ...0

1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1

1 1 1 01 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0

3 places

The signal states ofthe three bits that areshifted out are insertedin the vacated places.

IN

N

OUT

Parameters:

Figure 12-12 Rotating Bits of Input IN Three Bits to the Right

Table 12-8 Rotate Right Double Word Box and Parameters


ROR DWEN BOOL I, Q, M, L, D, T, C Enable input

ROR_DW

ENIN DWORD I, Q, M, L, D Value to be rotated

IN

EN


the value will be rotated

N ENO OUT DWORD I, Q, M, L, D Result of the rotate instruction


Status Word Bits



Memory double word MD0 is rotated tothe right by the number of bits specified inmemory word MW4.


ROR_DW

N

OUT

MW4

IN


MD10MD0

ENO

EN

Q4.0

I0.0

S

Figure 12-13 Rotate Right Double Word



Data Block Instructions


13.1 Open Data Block 13-2

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13.1 Open Data Block

You can use the Open Data Block instruction to open an existing data blockas a shared data block (DB) or instance data block (DI). The number of thedata block is transferred to the DB or DI register. The subsequent DB and DIcommands access the corresponding blocks depending on the registercontents.

Table 13-1 Open Data Block Box and Parameters with SIMATIC Mnemonics


<DB number> or<DI number>

AUF

Number of theDB or DI

BLOCK_DB DB, DI Number of the DB or DI;Range depends on theCPU.

Table 13-2 Open Data Block Box and Parameters with International Mnemonics


<DB number> or<DI number>

OPN

Number of theDB or DI

BLOCK_DB DB, DI Number of the DB or DI;Range depends on theCPU.

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites – – – – – – – – –

DB10 is the currently opened data block. Thescan at DBX0.0 therefore refers to bit 0 ofdata byte 0 of data block DB10. The signalstate of this bit is assigned to output Q 4.0.

DB10

DBX 0.0

Q 4.0

The instruction does not change the bits in the status word.

Network 1

Network 2

OPN

=

Figure 13-1 Open Data Block

Description

Data Block Instructions


Jump Instructions


14.1 Overview 14-2

14.2 Unconditional Jump in a Block 14-3

14.3 Conditional Jump in a Block 14-4

14.4 Jump-If-Not 14-5

14.5 Jump Label 14-6

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14.1 Overview

The address of a Jump instruction is a label. A label consists of a maximumof four characters. The first character must be a letter; the other characterscan be letters or numbers (for example, SEG3). The jump label indicates thedestination to which you want the program to jump.

You enter the label above the jump box (see Figure 14-1).

The destination label must be at the beginning of a network. You enter thedestination label at the beginning of the network by selecting LABEL fromthe FBD list box. An empty box appears. In the box, you type the name ofthe label (see Figure 14-1).

SEG3

JMP

Network1

Network X

Network 2

.

.

.

I0.1

Q4.0

=

SEG3

I0.4

Q4.1

R

Figure 14-1 Jump Label as Address and Destination

Jump Label asAddress

Jump Label asDestination

Jump Instructions


14.2 Unconditional Jump in a Block

The Unconditional Jump in a Block instruction corresponds to a “go to label”instruction. None of the instructions between the jump operation and thelabel is executed.

You can use this instruction in all logic blocks, for example in organizationblocks (OBs), function blocks (FBs) and functions (FCs).

There must not be any logic operation before the Unconditional Jump in aBlock box.

Table 14-1 Unconditional Jump in a Block Box and Parameters


<address>

JMP

Name of a jumplabel

– – The address specifies the label towhich the program will jumpunconditionally.

Status Word Bits


CAS1

JMP

Network 1

Network X

The jump is always executed. None of the instructions betweenthe jump instruction and the label is executed.

CAS1

I0.4Q4.1R

??.?

.

.

.

The instruction does not change the bits in the status word.

Figure 14-2 Unconditional Jump: Jump to Label

Description

Jump Instructions


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14.3 Conditional Jump in a Block

The Conditional Jump in a Block instruction corresponds to a “go to label”instruction if the RLO is 1. The FBD element “Unconditional Jump” is alsoused for this operation, however it is made conditional by the preceding logicoperation. The conditional jump is only executed when the result of this logicoperation is 1. None of the instructions between the jump operation and thelabel is executed.


Table 14-2 Conditional Jump in a Block Box and Parameters


<address>JMP

Name of ajump label

– – The address specifies the label towhich the program will jump if theRLO is 1.

Network 1

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites – – – – – 0 1 1 0

If the signal state of input I0.0 is 1, the jump to label CAS1is executed. The instruction to reset output Q4.0 is notexecuted, even if the signal state of input I0.3 is 1.

CAS1

Network 2

JMP

I0.3

I0.0

Q4.0R

Network 3

CAS1

I0.4Q4.1R

Figure 14-3 Conditional Jump: Jump in the Block If 1

Description

Jump Instructions


14.4 Jump-If-Not

The Jump-If-Not instruction corresponds to a “go to label” instruction that isexecuted if the RLO is 0.


Table 14-3 Jump-If-Not Box and Parameters


<address>

JMPN

Name of a jumplabel

– – The address specifies the label towhich the program will jump if theRLO is 0.

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites – – – – – 0 1 1 0

If the signal state of input I0.0 is 0, the jump to label CAS1is executed. The instruction to reset output Q4.0 is notexecuted, even if the signal state of input I0.3 is 1.

None of the instructions between the jump operation andthe label is executed.

Network 1

CAS1

Network 3

Network 2

JMPN

I0.3

I0.4

Q4.1

R

I0.0

Q4.0R

CAS1

Figure 14-4 Jump-If-Not

Description

Jump Instructions


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14.5 Jump Label

The jump label is the identifier for the destination of a jump instruction. Ajump label must exist for every jump or jump-if-not instruction (JMP orJMPN).

Format Description

LABEL

4 characters: first character must be a letterremaining characters can be letters or numbers

If I0.0 = 1, the jump to label CAS1 is executed.

Due to the jump, the operation “Reset output” at Q 4.0 is notexecuted even if I0.3 = 1.

Network 1

CAS1

Network 3

CAS1

Network 2

JMP

I0.3

I0.4

Q4.1

R

I0.0

Q4.0

R

Figure 14-5 Jump Label

Description

Jump Instructions


Status Bit Instructions


15.1 Overview 15-2

15.2 Exception Bit Binary Result 15-3

15.3 Result Bits 15-4

15.4 Exception Bit Unordered 15-6

15.5 Exception Bit Overflow 15-7

15.6 Exception Bit Overflow Stored 15-8

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15.1 Overview

The status bit instructions are bit logic instructions (see Chapter 4) that workwith the bits of the status word (see Section 2.3). Each of these instructionsreacts to one of the following conditions that is indicated by one or more bitsof the status word:

� The binary result bit is set (has a signal state of 1).

� The result of a math function is relative to 0 in one of the following ways:

– Greater than 0 (>0)

– Less than 0 (<0)

– Greater than or equal to 0 (>=0)

– Less than or equal to 0 (<=0)

– Equal to 0 (==0)

– Not equal to 0 (<>0)

� The result of a math function is unordered (invalid).

� A math function produced an overflow.

In an AND operation, the status bit instructions combine the result of theirsignal state checks with the previous result of logic operation according tothe And truth table (see Section 2.2 and Table 2-7). In an OR operation, theOR truth table is used (see Section 2.2 and Table 2-8).

In this section, the Exception Bit Binary Result element, which checks thesignal state of the BR (Binary Result) bit of the status word, is shown in itsinternational and SIMATIC form.

The status word is a register in the memory of your CPU that contains bitsthat you can reference in the address of bit and word logic instructions.Figure 15-1 shows the structure of the status word. For more information onthe individual bits of the status word, see Section 2.3.

28215... ...29 2427 26 25 2023 22 21

BR OSCC1 CC0 OV FCOR STA RLO

Figure 15-1 Structure of the Status Word

The FBD elements described in the following sections do not have anyselectable parameters.

Description

Status Word

Parameters



15.2 Exception Bit Binary Result

You can use the Exception Bit Binary Result instruction to check the signalstate of the BR bit (Binary Result) of the status word (see Section 2.3). In anAND operation, the result of the check is combined with the previous RLOaccording to the AND truth table (see Section 2.2 and Table 2-7). In an ORoperation, the OR truth table is used (see Section 2.2 and Table 2-8).

Figure 15-2 shows the Exception Bit Binary Result box with SIMATIC andinternational short names.

International elementSIMATIC element

BIE BR

Figure 15-2 Exception Bit Binary Result Box

I0.0 Output Q4.0 is set if the signal state at inputI0.0 is 1 OR the signal state at input I0.2 is 0,and, in addition to this RLO, the signal stateof the BR bit is 1.

I0.2

BR

Q4.0

S

>=1

&

Figure 15-3 Exception Bit Binary Result

Description

FBD Box



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15.3 Result Bits

You can use the Result Bit instructions to determine the relationship of theresult of a math function to zero, in other words, whether the result is >0, <0,>=0, <=0, ==0, or <>0 (see Table 15-1). The condition code bits of the statusword (CC 1 and CC 0, see Section 2.3) are evaluated. If the comparisoncondition indicated in the address is fulfilled, the result of this signal statecheck is 1.

In an AND operation, this instruction combines the result of its check withthe previous result of logic operation (RLO) according to the AND truth table(see Section 2.2 and Table 2-7). In an OR operation, this instructioncombines the result of its check with the previous RLO according to the ORtruth table (see Section 2.2 and Table 2-8).

Table 15-1 Result Bits Boxes

FBD Element Description

> 0The Result Bit instruction for greater than 0 determines whether or not the result of amath instruction is greater than 0. It checks the combination in the condition code bitsCC1 and CC0 in the status word to determine the relationship of a result to 0.

< 0The Result Bit instruction for less than 0 determines whether or not the result of a mathinstruction is less than 0. It checks the combination in the condition code bits CC1 andCC0 in the status word to determine the relationship of a result to 0.

> = 0The Result Bit instruction for greater than or equal to 0 determines whether or not theresult of a math instruction greater than or equal to 0. It checks the combination in thecondition code bits CC1 and CC0 in the status word to determine the relationship of aresult to 0.

< = 0The Result Bit instruction for less than or equal to 0 determines whether or not the resultof a math instruction is less than or equal to 0. It checks the combination in the conditioncode bits CC1 and CC0 in the status word to determine the relationship of a result to 0.

== 0The Result Bit instruction for equal to 0 determines whether or not the result of a mathinstruction is equal to 0. It checks the combination in the condition code bits CC1 andCC0 in the status word to determine the relationship of a result to 0.

< > 0The Result Bit instruction for not equal to 0 determines whether or not the result of amath instruction is not equal to 0. It checks the combination in the condition code bitsCC1 and CC0 in the status word to determine the relationship of a result to 0.

Description



Status Word Bits


If the signal state at input I0.0 is 1, the SUB_I boxis activated. If the value of input word IW0 isgreater than the value of input word IW2, theresult of the math function IW0 – IW2 is greaterthan 0.

If the signal state of EN is 1 (activated) and anerror occurs while the instruction is beingexecuted, the signal state of ENO is 0.

1) Output Q4.0 is set if the function is executedcorrectly and the result is less than or equal to 0.If the signal state of input I0.0 is 0 (not activated),the signal state of both EN and ENO is 0.

2) Output Q4.0 is set if the function is executedcorrectly and the result is less than or equal to 0.If the signal state of input I0.0 is 0 (not activated),the signal state of both EN and ENO is 0.

1)

2)

SUB_I

IN2

OUT

IW2

MW10IN1IW0

EN

ENO

I0.0

SUB_I

IN2

OUT

IW2

MW10IN1IW0

EN

ENO

I0.0

Q4.0S

&

≤0

Q4.0S

&

>0

Figure 15-4 Result Bit for Greater than 0 and Negated Result Bit for Greater than 0



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15.4 Exception Bit Unordered

You can use the Exception Bit Unordered instruction to check whether or notthe result of a floating-point math function is unordered (in other words,whether one of the values in the math function is not a valid floating-pointnumber). The condition code bits of the status word (CC 1 and CC 0, seeSection 2.3) are evaluated. If the result of the math function is unordered(UO) the signal state check produces a result of 1. If the combination in CC 1and CC 0 does not indicate unordered, the result of the signal state check is0.

In an AND operation, this instruction combines the result of its check withthe previous result of logic operation (RLO, see Section 2.3) according to theAND truth table (see Section 2.2 and Table 2-7). In an OR operation, the ORtruth table is used (see Section 2.2 and Table 2-8).

UO

Figure 15-5 Exception Bit Unordered Box

If the signal state at input I0.0 is 1, the DIV_Rbox is activated. If the value of either inputdouble word ID0 or ID4 is not a validfloating-point number, the floating-point mathfunction is unordered. If the signal state of EN is 1 (activated) andan error occurs while the instruction is beingexecuted, the signal state of ENO is 0.

Output Q4.0 is set if the function DIV_R isexecuted, but one of the values in the mathfunction is not a valid floating-point number. Ifthe signal state of input I0.0 is 0 (notactivated), the signal state of both EN andENO is 0.

DIV_R

IN2

OUT

ID4

MD10IN1ID0

EN

ENO

I0.0

Q4.1S

UO Q4.0

S

Network 1:

Network 2:

Figure 15-6 Exception Bit Unordered

Description

FBD Box



15.5 Exception Bit Overflow

You can use the Exception Bit Overflow instruction to detect an overflow(OV) in the last math function. If, after the system executes a math function,the result is outside the permitted negative range or outside the permittedpositive range, the OV bit in the status word (see Section 2.3) is set. Theinstruction checks the signal state of this bit. This bit is reset if the mathfunctions were free of errors

In an AND operation, this instruction combines the result of its check withthe previous result of logic operation according to the AND truth table (seeSection 2.2 and Table 2-7). In an OR operation, the OR truth table is used(see Section 2.2 and Table 2-8).

OV

Figure 15-7 Exception Bit Overflow Box

If the signal state at input I0.0 is 1, the SUB_I box isactivated. If the result of the math function input word IW0minus input word IW2 is outside the permitted range for aninteger, the OV bit in the status word is set.

The result of a signal state check at OV is 1. Output Q4.0is set if the check at OV is 1 and the RLO of network 2 is 1(if the RLO prior to output Q4.0 is 1).

If the signal state of input I0.0 is 0 (not activated), thesignal state of both EN and ENO is 0. If the signal state ofEN is 1 (activated) and the result of the math function isout of range, the signal state of ENO is 0.

Network 1:

Network 2:

SUB_I

IN2

OUT

IW2

MW10IN1IW0

EN

ENO

I0.0

I0.1

I0.2

I0.3

&

>=1

Q4.0

SOV

M 3.3

Network 3:

Figure 15-8 Exception Bit Overflow

Description

FBD Box



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15.6 Exception Bit Overflow Stored

You can use the Exception Bit Overflow Stored instruction to recognize aprevious overflow (overflow stored, OS) in a math function. If, after thesystem executes a math function, the result is outside the permitted negativerange or outside the permitted positive range, the OS bit in the status word(see Section 2.3) is set. The instruction checks the signal state of this bit.Unlike the OV (overflow) bit, the OS bit remains set even if later mathfunctions were executed free of errors (see Section 15.5).

In an AND operation, this instruction combines the result of its check withthe previous result of logic operation according to the AND truth table (seeSection 2.2 and Table 2-7). In an OR operation, the OR truth table is used(see Section 2.2 and Table 2-8).

OS

Figure 15-9 Exception Bit Overflow Stored Box

Description

FBD Box



If the signal state at input I0.0 is 1, the MUL_I box isactivated. If the signal state at input I0.1 is 1, the ADD_I boxis activated. If the result of one of the math functions isoutside the permissible range for an integer, the OS bit in thestatus word is set.

The result of a signal state check at OS is 1 and output Q4.0is set.

Network 1: if the signal state of input I0.0 is 0 (not activated),the signal state of both EN and ENO is 0. If the signal state ofEN is 1 (activated) and the result of the math function is outof range, the signal state of ENO is 0.

Network 2: if the signal state of input I0.1 is 0 (not activated),the signal state of both EN and ENO is 0. If the signal state ofEN is 1 (activated) and the result of the math function is outof range, the signal state of ENO is 0.

Network 1:

Network 2:

Network 3:

MUL_I

IN2

OUT

IW2

MD8IN1IW0

EN

ENO

I0.0

ADD_I

IN2

OUT

IW2

MW12IN1IW0

EN

ENO

I0.1

OS Q4.0

S

Figure 15-10 Exception Bit Overflow Stored



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Program Control Instructions


16.1 Calling an FC/SFC without Parameters 16-2

16.2 Calling an FB, FC, SFB, SFC, and Multiple Instances 16-4

16.3 Return 16-7

16.4 Master Control Relay Instructions 16-8

16.5 Master Control Relay Activate/Deactivate 16-10

16.6 Master Control Relay On/Off 16-13

ChapterOverview

16


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16.1 Calling an FC/SFC without Parameters

With the Call FC/SFC without Parameters instruction, you can call afunction (FC) or a system function (SFC) that has no parameters. The call isconditional or unconditional depending on the preceding logic operation (seethe example).

In the code section of a function (FC), you cannot specify any parameter ofthe type BLOCK_FC as the address for a conditional call. You can, however,specify a parameter of the type BLOCK_FC as the address in a functionblock (FB).

A conditional call is executed only if the RLO is 1. If a conditional call is notexecuted, the RLO after the call instruction is 0. If the instruction isexecuted, the following functions are performed:

� The address required to return to the calling block is saved.

� The data block registers are saved (data block and instance data block).

� The previous local data area is replaced by the current local data area.

� The MA bit (active MCR bit) is written to the block stack (BSTACK).

� The new local data area is created for the called FC or SFC.

Program execution is then continued in the called block.

For more detailed information about transferring parameters, refer to theSTEP 7 Online Help.

Table 16-1 Calling an FC/SFC without Parameters Box


Description

CALL

<Number>Number BLOCK_FC –

Number of the FC or SFC (for example FC10 orSFC59). The SFCs that are available depend onyour CPU.

A conditional call with a parameter of the datatype BLOCK_FC as the address is only possiblein an FB and not in an FC.

Description



If the unconditional call for FC10 is executed, the CALL instruction performs the followingfunctions:

� Saves the address required to return to the current FB.� Saves the selectors for DB10 and for the instance data block of the FB.� Pushes the MA bit, set to 1 in the MCRA instruction, to the block stack (BSTACK) and

resets this bit to 0 for the called FC10

Program execution continues in FC10. If you want to use the MCR function in FC10, you mustreactivate it there. When FC10 is completed, program execution returns to the calling FB. TheMA bit is restored. DB10 and the instance data block of the user-defined FB are the currentDBs again, regardless of which DBs were used by FC10.

After the return jump from FC10, the signal state of input I0.0 is assigned to output Q4.0. Thecall for FC11 is a conditional call. It is executed only if the signal state of input I0.1 is 1. If the callis executed, the function is the same as for calling FC10.

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites – – – – 0 0 1 – 0

I0.0

Q4.0

DB10

MCRA

CALL

CALL

BR CC1 CC0 OV OS OR STA RLO FCwrites – – – – 0 0 1 1 0

Unconditional call

Conditional call

OPN

FC10

MCRD

=

I0.1

FC11

Figure 16-1 Calling an FC/SFC without Parameters



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16.2 Calling an FB, FC, SFB, SFC, and Multiple Instances

You can call function blocks (FBs), functions (FCs), system function blocks(SFBs), and system functions (SFCs), and multiple instances by selectingthem from the “Program Elements” list box. They are at the end of the list ofinstruction families under the following names:

� FB Blocks

� FC Blocks

� SFB Blocks

� SFC Blocks

� Multiple Instances

� Libraries

When you select one of these blocks, a box appears on your screen with thenumber or symbolic name of the function or function block and theparameters that belong to it.

The block that you call must have been compiled and must already exist inyour program file, in the library, or on the CPU.

If the call FB, FC, SFB, SFC, and multiple instances instruction is executed,it performs the following functions:

� It saves the address required to return to the calling block.

� It saves both data block registers (data block and instance data block).

� It replaces the previous local data area with the current local data area.

� It shifts the MA bit (active MCR bit) to the block stack (BSTACK).

� It creates the new local data area for the called FC or SFC.

Note

When the DB and DI registers are saved, it is possible that they do not pointto the data blocks that you opened. Because of the copy mechanisms fortransferring parameters, especially where function blocks are concerned, thecompiler sometimes overwrites the DB register. See the STEP 7 Online Helpfor more details.

Execution of the program then continues in the called block.

Description



The Enable output (ENO) of an FBD box corresponds to the BR bit of thestatus word (see Section 2.3). When you write a function block or functionthat you want to call from FBD regardless of whether you write the FB or FCin STL, LAD or FBD, keep in mind the BR bit. You save the RLO in the BRbit with the SAVE instruction according to the following criteria:

� Save an RLO of 1 in the BR bit when the FB or FC is executed withouterror.

� Save an RLO of 0 in the BR bit when an error occurs in the execution ofthe FB or FC.

You should program these instructions at the end of the FB or FC so thatthese are the last instructions that are executed in the block.

!Warning

Unintentionally resetting the BR bit to 0

When writing FBs and FCs in FBD, if you do not handle the BR bit asdescribed above, one FB or FC may overwrite the BR bit of another FBor FC.

To avoid this problem, store the RLO at the end of each FB or FC asdescribed above.

Figure 16-2 shows the effects of a conditional and an unconditional call of ablock on the bits of the status word (see Section 2.3).

Conditional:Unconditional:

BR CC1 CC0 OV OS OR STA RLO FCwrites x – – – 0 0 1 x xwrites – – – – 0 0 x x x

Figure 16-2 Effect of a Block Call on the Bits of the Status Word

Enable Output

Effect of the Callon the Bits of theStatus Word



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The parameters that have been defined in the VAR section of the block willbe displayed in the FBD box. Supplying parameters differs depending on thetype of block as follows:

� For a function (FC), you must supply actual parameters for all of theformal parameters.

� The entry of actual parameters is optional with function blocks (FBs).You must, however, attach an instance data block (instance DB) to theFB. If an actual parameter has not been attached to a formal parameter,the FB works with the values that exist in its instance DB.

� With multiple instances, you do not need to specify the instance DB sincethe box that is called has already been assigned the DB number (for moreinformation about declaring multiple instances, refer to STEP 7 OnlineHelp

For structured IN/OUT parameters and parameters of the types “Pointer” and“Array”, you must make an actual parameter available (at least during thefirst call).

Every actual parameter that you make available when calling a functionblock must have the same data type as its formal parameter.

For information on how to program a function or how to work with itsparameters, see the STEP 7 Online Help.

Table 16-2 shows a box for calling FBs, FCs, SFBs, SFCs and describes theparameters common to the box for all these blocks. The block numberappears automatically at the top of the block (number of the FB, FC, SFB, orSFC, for example, FC10).

Table 16-2 Box and Parameters for Calling FBs, FCs, SFBs, SFCs


Block no.EN

DB no.DB no. BLOCK_DB –

Data block number. Thisinformation is only necessary forcalling FBs.

EN

IN OUT EN BOOL I, Q, M, D, L, T, C Enable input

ENOIN/OUT ENO BOOL I, Q, M, D, L Enable output

DB13

ENStart

Stop

Length

RunENO

Calls FB10 (usinginstance DB13)

I 1.0

I 1.1

MW20

M2.1

FB10

Actual addresses,the values of whichare copied intoinstance data blockDB13 beforeprocessing FB10.

Formal parameters of the FB

The value of this parameter iscopied from DB13 into M 2.1 afterprocessing FB10.

Figure 16-3 Call FB as Box

Parameters



16.3 Return

You can use the Return instruction to exit blocks. You can exit a blockconditionally.

Table 16-3 Box Return


RET None – – –

If the signal state of input I0.0 is 1, the block isexited.

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites – – – – 0 0 1 1 0

Conditional Return (Return if RLO = 1)

RETI0.0

Figure 16-4 Return

Description



C79000-G7076-C566-01

16.4 Master Control Relay Instructions

The Master Control Relay (MCR, see also Section 16.5) is used to activateand deactivate signal flow. A deactivated signal flow corresponds to aninstruction sequence that writes a zero value instead of the calculated value,or to an instruction sequence that leaves the existing memory valueunchanged. Operations triggered by the instructions shown in Table 16-4 aredependent on the MCR.

The Assign and Midline Output instructions write a 0 to the memory if theMCR is 0. The Set Output and Reset Output instructions leave the existingvalue unchanged (see Table 16-5).

Table 16-4 Instructions Influenced by an MCR Zone

FBD Box Description Section in This Manual

# Midline Output 4.9

= Assign 4.8

S Set Output 4.11

R Reset Output 4.12

SR Set_Reset Flip Flop 4.25

RSSet_Reset Flip Flop 4.26

MOVEAssign a Value 10.1

Table 16-5 Instructions Dependent on MCR and How They React to Its Signal State

Signal State ofMCR

Assign, Midline Output

=

#

Set or Reset Output

S

SR

R

RS

Assign a Value

MOVE

0 Writes 0

(Imitates a relay that falls to itsquiet state when power isturned off)

Does not write

(Imitates a latching relay thatremains in its current statewhen power is turned off)

Writes 0

(Imitates a component thatproduces a value of 0 whenpower is turned off)

1 Normal execution Normal execution Normal execution

Definition of theMaster ControlRelay



Important Notes on Using MCR Functions

Take care with blocks in which the Master Control Relay was activated withMCRA:

� If the MCR is deactivated, the value 0 is written by all assignments inprogram segments between (MCR<) and (MCR>)!

� The MCR is deactivated if the RLO was =0 before an MCR< instruction.

!Danger

PLC in STOP or undefined runtime characteristics!

The compiler also uses write access to local data behind the temporary varia-bles defined in VAR_TEMP for calculating addresses. This means the follo-wing command sequences will set the PLC to STOP or lead to undefinedruntime characteristics:

Formal parameter access

� Access to components of complex FC parameters of the type STRUCT,UDT, ARRAY, STRING

� Access to components of complex FB parameters of the type STRUCT,UDT, ARRAY, STRING from the IN_OUT area in a version 2 block.

� Access to parameters of a version 2 function block if its address isgreater than 8180.0.

� Access in a version 2 function block to a parameter of the typeBLOCK_DB opens DB0. Any subsequent data access sets the CPU toSTOP. T 0, C 0, FC0, or FB0 are also always used for TIMER,COUNTER, BLOCK_FC, and BLOCK_FB.

Parameter passing

� Calls in which parameters are transferred.

KOP/FUP

� T branches and midline outputs in Ladder or FBD starting with RLO = 0.

Remedy

Free the above commands from their dependence on the MCR:

1. Deactivate the Master Control Relay using the Master Control RelayDeactivate instruction before the statement or network in question.

2. Activate the Master Control Relay again using the Master Control RelayActivate instruction after the statement or network in question.



C79000-G7076-C566-01

16.5 Master Control Relay Activate/Deactivate

With the Activate Master Control Relay, instruction, you make subsequentcommands dependent on the MCR. After entering this command, you canprogram the MCR zones with these instructions (see Section 16.6). Whenyour program activates an MCR area, all MCR actions depend on the contentof the MCR stack (see Figure B-4).

Table 16-6 Master Control Relay Activate Box


MCRA None – – Activates the MCR function

With the Deactivate Master Control Relay instruction, subsequent commandsare no longer dependent on the MCR. After this instruction, you cannotprogram any more MCR zones. When your program deactivates an MCRarea, the MCR is always energized irrespective of the entries in the MCRstack.

Table 16-7 Master Control Relay Deactivate Box


MCRD None – – Deactivates the MCR function

The MCR stack and the bit that controls its dependency (the MA bit) relate toindividual levels and must be saved and fetched every time you change thesequence level. They are preset at the beginning of every sequence level(MCR input bits 1 to 8 are set to 1, the MCR stack pointer is set to 0 and theMA bit is set to 0).

The MCR stack is transferred from block to block and the MA bit is savedand set to 0 every time a block is called. It is fetched back at the end of theblock.

The MCR can be implemented in such a way that it optimizes the run time ofcode-generating CPUs. The reason for this is that the dependency of theMCR is not passed on by the block; it must be explicitly activated by anMCR instruction. A code-generating CPU recognizes this instruction andgenerates the additional code necessary for the evaluation of the MCR stackuntil it recognizes an MCR instruction or reaches the end of the block. Withinstructions outside the MCRA/MCRD range, there is no increase of the runtime.

The instructions MCRA and MCRD must always be used in pairs within yourprogram.

MCR Activate

MCR Deactivate



ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ

OB1

MCRA

MCRD

MCRA

MCRA

MCRA

MCRD

BEU

BEU

Operations dependent on the MCR bit

Operations not dependent on the MCR bit

Call FBx

FBx FCy

Call FCy

BEU BEU is an STL instruction. You will find more details in the STL Manual /232/

Figure 16-5 Activating and Deactivating an MCR Area

The operations programmed between MCRA and MCRD depend on thesignal state of the MCR bit. Operations programmed outside anMCRA-MCRD sequence do not depend on the signal state of the MCR bit. Ifan MCRD instruction is missing, the operations programmed between theinstructions MCRA and BEU depend on the MCR bit.



C79000-G7076-C566-01

The MCRA instruction activates the MCR function until the next MCRD. The instructionsbetween MCR< and MCR> are processed dependent on the MA bit (here I0.0):

� If the signal state of input I0.0 is 1:– Output Q4.0 is set to 1 if the signal state of input I0.3 is 1.– Output Q4.0 remains unchanged if the signal state of input I0.3 is 0.– The signal state of input I0.4 is assigned to output Q4.1.

� If the signal state of input I0.0 is 0:– Output Q4.0 remains unchanged regardless of the signal state of input I0.3.– Output Q4.1 is 0 regardless of the signal state of input I0.4.

Status Word Bits


I0.3

Q4.0

MCR<

=

MCRA

MCRD

S

I0.4

Q4.1

MCR>

I0.0

Figure 16-6 Master Control Relay (Activate and Deactivate)

You must program the dependency of the functions (FCs) and function blocks(FBs) in the blocks yourself. If this function or function block is called froman MCRA/MCRD sequence, not all instructions within this sequence areautomatically dependent on the MCR bit. To achieve this, use the instructionMCRA of the block called.

!Warning

Risk of personal injury and damage to equipment:

Never use the instruction MCR as an EMERGENCY OFF or safety devicefor personnel.

MCR is not a substitute for a hardwired master control relay.



16.6 Master Control Relay On/Off

The Master Control Relay On (MCR<) instruction triggers an operation thatsaves the RLO in the MCR stack and opens an MCR zone. The instructionsshown in Table 16-4 are influenced by this RLO saved in the MCR stackwhen the MCR zone is opened. The MCR stack works like a LIFO (Last In,First Out) buffer. Only eight entries are possible. If the stack is already full,the Master Control Relay On instruction produces an MCR stack error(MCRF).

Table 16-8 Master Control Relay On Box


MCR< None – – Opens an MCR zone

The Master Control Relay Off (MCR>) instruction closes the MCR zone thatwas opened last. The instruction does this by removing the RLO entry fromthe MCR stack. The RLO was saved there by the Master Control Relay Oninstruction. The entry released at the other end of the LIFO (Last In, FirstOut) MCR stack is set to 1. If the stack is already empty, the Master ControlRelay Off instruction produces an MCR stack error (MCRF).

Table 16-9 Master Control Relay Off


MCR> None – –Closes the MCR zone that wasopened last

The MCR is controlled by a stack which is one bit wide and eight entriesdeep (see Figure 16-7). The MCR is activated as long as all eight entries inthe stack are equal to 1. The MCR< instruction copies the RLO to the MCRstack. The MCR> instruction removes the last entry from the stack and setsthe released stack address to 1. If an error occurs, for example, if there aremore than eight MCR> instructions in succession, or you attempt to executethe instruction MCR> when the stack is empty, the MCRF error message isactivated. The monitoring of the MCR stack is based on the stack pointer(MSP: 0 = empty, 1 = one entry, 2 = two entries, ..., 8 = eight entries).

MCR On

MCR Off



C79000-G7076-C566-01

RLO

RLO

RLOMSP �

MA

MCRA MCRD1 0

� �

1

2

3

4

5

6

7

8

RLO Shifted bit� �

� �

MSP = MCR stack pointer

MA = Bit controlling MCR dependency

Shifted bit 1

Figure 16-7 Master Control Relay Stack

The instructions MCR< and MCR> must always be used in pairs within yourprogram.

The MCR< instruction adopts the signal state of the RLO and copies it to theMCR bit.

The MCR> instruction sets the MCR bit to 1 unconditionally. Because of thischaracteristic, every other instruction between the instructions MCRA andMCRD operates independent of the MCR bit (for information about MCRAand MCRD, see above).

You can nest the instructions MCR< and MCR>. The maximum nestingdepth is eight, in other words, you can write a maximum of eight MCR<instructions in succession before inserting an MCR> instruction. You mustprogram an equal number of MCR< and MCR> instructions.

If the MCR< instructions are nested, the MCR bit of the lower nesting levelis formed. The MCR< instruction then combines the current RLO with thecurrent MCR bit according to the AND truth table.

When an MCR> instruction completes a nesting level, it fetches the MCR bitfrom the next highest level.

Nesting theInstructions MCR<and MCR>



When the MCRA instruction activates the MCR function, you can create up to eight nested MCRzones. In the example, there are two MCR zones. The first MCR> instruction works together with thesecond MCR< instruction. All instructions between the second set of MCR brackets (MCR<MCR>)belong to the second MCR zone. The operations are executed as follows:� If I0.0 = 1: the signal state of input I0.4 is assigned to output Q4.1.� If I0.0 = 0: the signal state of output Q4.1 is 0 regardless of the signal state of input I0.4. Output

Q4.0 remains unchanged regardless of the signal state of input I0.3.� If I0.0 and I0.1 = 1: output Q4.0 is set to 1 if I0.3 = 1 and Q4.1 = I0.4.� If I0.1 = 0: output Q4.0 remains unchanged regardless of the signal state of input I0.3 and input

I0.0.

Status Word Bits

BR CC1 CC0 OV OS OR STA RLO FCwrites – – – – – 0 1 – 0

I0.3

Q4.0

MCR>

=

MCRA

MCRD

S

I0.4

Q4.1

MCR>

I0.0 MCR<

I0.1 MCR<

Figure 16-8 Master Control Relay Off



C79000-G7076-C566-01


Alphabetical Lists of Instructions A

Programming Examples B

References C

Appendix

P-18Function Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01

A-1Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

Alphabetical Lists of Instructions


A.1 List of Instructions with International Names A-2

A.2 List of Instructions with International (English) Names andGerman Equivalents

A-6

A.3 List of Instructions with German SIMATIC Names A-10

A.4 List of Instructions with German Names and International(English) Equivalents

A-14

ChapterOverview

A

A-2Function Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01

A.1 List of Instructions with International Names

Table A-1 contains an alphabetical list of FBD instructions with international(English) full names, the corresponding short name or mnemonic, and thereference to the page on which the instruction is described.

Table A-1 FBD Instructions Arranged Alphabetically by International (English) Full Names with ShortNames

Full Name Short Name Page

Add Double Integer ADD_DI 7-3

Add Integer ADD_I 7-2

Add Real ADD_R 8-3

Address Negative Edge Detection NEG 4-31

Address Positive Edge Detection POS 4-30

AND & 4-3

Assign = 4-9

Assign a Value MOVE 10-2

BCD to Double Integer BCD_DI 10-6

BCD to Integer BCD_I 10-3

Call FB from Box CALL_FB 16-4

Call FC from Box CALL_FC 16-4

Call FC SFC (without parameters) CALL 16-2

Call System FB from Box CALL_SFB 16-4

Call System FC from Box CALL_SFC 16-4

Ceiling CEIL 10-16

Compare Double Integer (>, <, ==, <>, <=, >=) CMP >=D 9-3

Compare Integer (>, <, ==, <>, <=, >=) CMP >=I 9-2

Compare Real (>, <, ==, <>, <=, >=) CMP >=R 9-4

Divide Double Integer DIV_DI 7-9

Divide Integer DIV_I 7-8

Divide Real DIV_R 8-6

Double Integer to BCD DI_BCD 10-7

Double Integer to Real DI_R 10-8

Down Counter (counter instruction) S_CD 6-7

Down Counter (bit logic instruction) CD 4-17

Exception Bit Binary Result BR 15-3

Exception Bit Overflow OV 15-7

Exception Bit Overflow Stored OS 15-8

Exception Bit Unordered UO 15-6

Exclusive OR XOR 4-6

Extended Pulse S5 Timer (timer instruction) S_PEXT 5-7

Alphabetical List of Instructions


Table A-1 FBD Instructions Arranged Alphabetically by International (English) Full Names with ShortNames, cont.

Full Name PageShort Name

Extended Pulse Timer (bit logic instruction) SE 4-20

Floor FLOOR 10-17

Form the Absolute Value of a Floating-Point Number ABS 8-8

Form the Arc Cosine of a Floating-Point Number ACOS 8-13

Form the Arc Sine of a Floating-Point Number ASIN 8-13

Form the Arc Tangent of a Floating-Point Number ATAN 8-13

Form the Cosine of a Floating-Point Number COS 8-13

Form the Exponential Value of a Floating-Point Number EXP 8-12

Form the Natural Logarithm of a Floating-Point Number LN 8-11

Form the Sine of a Floating-Point Number SIN 8-13

Form the Square of a Floating-Point Number SQR 8-9

Form the Square Root of a Floating-Point Number SQRT 8-10

Form the Tangent of a Floating-Point Number TAN 8-13

Insert Binary Input –––| 4-7

Integer to BCD I_BCD 10-4

Integer to Double Integer I_DI 10-5

Jump JMP 14-3

Jump-If-Not JMPN 14-5

Master Control Relay Activate MCRA 16-10

Master Control Relay Deactivate MCRD 16-10

Master Control Relay Off MCR> 16-13

Master Control Relay On MCR< 16-13

Midline Output # 4-10

Multiply Double Integer MUL_DI 7-7

Multiply Integer MUL_I 7-6

Multiply Real MUL_R 8-5

Negate Binary Input –––o| 4-8

Negate Real Number NEG_R 10-13

Negative RLO Edge Detection N 4-29

Off-Delay S5 Timer (timer instruction) S_OFFDT 5-13

Off-Delay Timer (bit logic instruction) SF 4-26

On-Delay S5 Timer (timer instruction) S_ODT 5-9

On-Delay Timer (bit logic instruction) SD 4-22

Ones Complement Double Integer INV_DI 10-10

Ones Complement Integer INV_I 10-9

Open Data Block: DB or DI OPN 13-2

OR >=1 4-4



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Positive RLO Edge Detection P 4-28

Pulse S5 Timer (timer instruction) S_PULSE 5-5

Pulse Timer (bit logic instruction) SP 4-18

Reset Output R 4-13

Reset_Set Flip Flop RS 4-33

Result Bit Equal 0 ==0 1-6

Result Bit Greater Equal 0 >=0 15-4

Result Bit Greater Than 0 >0 15-4

Result Bit Less Equal 0 <=0 15-4

Result Bit Less Than 0 <0 15-4

Result Bit Not Equal 0 <>0 15-4

Retentive On-Delay S5 Timer (timer instruction) S_ODTS 5-11

Retentive On-Delay Timer (bit logic instruction) SS 4-24

Return RET 16-7

Return Fraction Double Integer MOD 7-10

Rotate Left Double Word ROL_DW 12-11

Rotate Right Double Word ROR_DW 12-12

Round to Double Integer ROUND 10-14

Save RLO to BR Memory SAVE 4-11

Set Output S 4-12

Set Counter Value SC 4-14

Set_Reset Flip Flop SR 4-32

Shift Left Double Word SHL_DW 12-4

Shift Left Word SHL_W 12-3

Shift Right Double Integer SHR_DI 12-9

Shift Right Double Word SHR_DW 12-6

Shift Right Integer SHR_I 12-8

Shift Right Word SHR_W 12-5

Subtract Double Integer SUB_DI 7-5

Subtract Integer SUB_I 7-4

Subtract Real SUB_R 8-4

Truncate Double Integer Part TRUNC 10-15

Twos Complement Double Integer NEG_DI 10-12

Twos Complement Integer NEG_I 10-11

Up Counter (counter instruction) S_CU 6-5

Up Counter (bit logic instruction) CU 4-16

Up-Down Counter S_CUD 6-3





(Word) AND Double Word WAND_DW 11-4

(Word) AND Word WAND_W 11-3

(Word) Exclusive OR Double Word WXOR_DW 11-8

(Word) Exclusive OR Word WXOR_W 11-7

(Word) OR Double Word WOR_DW 11-6

(Word) OR Word WOR_W 11-5



C79000-G7076-C566-01

A.2 List of Instructions with International (English) Names and GermanEquivalents

Table A-4 contains an alphabetical list of FBD instructions with international(English) full names, the German SIMATIC equivalents, and the reference tothe page on which the instruction is described.

Table A-2 FBD Instructions Arranged Alphabetically by International (English) Full Names with GermanEquivalents

Full Name German SIMATIC Equivalent Page

Add Double Integer Ganze Zahlen addieren (32 Bit) 7-3

Add Integer Ganze Zahlen addieren (16 Bit) 7-2

Add Real Gleitpunktzahlen addieren 8-3

Address Negative Edge Detection Signalflanke 1 → 0 abfragen 4-31

Address Positive Edge Detection Signalflanke 0 → 1 abfragen 4-30

AND UND-Verknüpfung 4-3

Assign Zuweisung 4-9

Assign a Value Wert übertragen 10-2

BCD to Double Integer BCD-Zahl in Ganzzahl (32 Bit) wandeln 10-6

BCD to Integer BCD-Zahl in Ganzzahl (16 Bit) wandeln 10-3

Call FB from Box FB aufrufen 16-4

Call FC from Box FC aufrufen 16-4

Call FC SFC (without parameters) FC/SFC aufrufen ohne Parameter 16-2

Call System FB from Box System FB aufrufen 16-4

Call System FC from Box System FC Box aufrufen 16-4

Ceiling Aus Gleitpunktzahl nächsthöhere Ganzzahlerzeugen

10-16

Compare Double Integer (>, <, ==, <>, <=, >=)Ganze Zahlen vergleichen (32 Bit) 9-3

Compare Integer (>, <, ==, <>, <=, >=) Ganze Zahlen vergleichen (16 Bit) 9-2

Compare Real (>, <, ==, <>, <=, >=) Gleitpunktzahlen vergleichen 9-4

Divide Double Integer Ganze Zahlen dividieren (32 Bit) 7-9

Divide Integer Ganze Zahlen dividieren (16 Bit) 7-8

Divide Real Gleitpunktzahlen dividieren 8-6

Double Integer to BCD Ganzzahl (32 Bit) in BCD-Zahl wandeln 10-7

Double Integer to Real Ganzzahl (32 Bit) in Gleitpunktzahl wandeln 10-8

Down Counter (counter instruction) Rückwärtszählen 6-7

Down Counter (bit logic instruction) Rückwärtszählen 4-17

Exception Bit Binary Result Störungsbit BIE-Register 15-3

Exception Bit Overflow Störungsbit Überlauf 15-7

Exception Bit Overflow Stored Störungsbit Überlauf gespeichert 15-8

Exception Bit Unordered Störungsbit Ungültige Operation 15-6



Table A-2 FBD Instructions Arranged Alphabetically by International (English) Full Names with GermanEquivalents, cont.

Full Name PageGerman SIMATIC Equivalent

Exclusive OR EXKLUSIV-ODER-Verknüpfung 4-6

Extended Pulse S5 Timer (timer instruction) Zeit als verlängerten Impuls starten (SV) 5-7

Extended Pulse Timer (bit logic instruction) Zeit als verlängerten Impuls starten (SV) 4-20

Floor Aus Gleitpunktzahl nächstniedere Ganzzahlerzeugen

10-17

Form the Absolute Value of a Floating-PointNumber

Absolutwert einer Gleitpunktzahl bilden 8-8

Form the Arc Cosine of a Floating-PointNumber

Arcuscosinus einer Gleitpunktzahl bilden 8-13

Form the Arc Sine of a Floating-Point NumberArcussinus einer Gleitpunktzahl bilden 8-13

Form the Arc Tangent of a Floating-PointNumber

Arcustangens einer Gleitpunktzahl bilden 8-13

Form the Cosine of a Floating-Point Number Cosinus einer Gleitpunktzahl bilden 8-13

Form the Exponential Value of a Floating-PointNumber

Exponentialwert einer Gleitpunktzahl bilden 8-12

Form the Natural Algorithm of a Floating-PointNumber

Natürlichen Logarithmus einer Gleitpunktzahlbilden

8-11

Form the Sine of a Floating-Point Number Sinus einer Gleitpunktzahl bilden 8-13

Form the Square of a Floating-Point Number Quadrat einer Gleitpunktzahl bilden 8-9

Form the Square Root of a Floating-PointNumber

Quadratwurzel einer Gleitpunktzahl bilden 8-10

Form the Tangent of a Floating-Point NumberTangens einer Gleitpunktzahl bilden 8-13

Insert Binary Input Binären Eingang einfügen 4-7

Integer to BCD Ganzzahl (16 Bit) in BCD-Zahl wandeln 10-4

Integer to Double Integer Ganzzahl (16 Bit) in Ganzzahl (32 Bit) wandeln 10-5

Jump Springe wenn 1 14-3

Jump-If-Not Springe wenn 0 14-5

Master Control Relay Activate Master Control Relay Anfang 16-10

Master Control Relay Deactivate Master Control Relay Ende 16-10

Master Control Relay Off Master Control Relay ausschalten 16-13

Master Control Relay On Master Control Relay einschalten 16-13

Midline Output Konnektor 4-10

Multiply Double Integer Ganze Zahlen multiplizieren (32 Bit) 7-7

Multiply Integer Ganze Zahlen multiplizieren (16 Bit) 7-6

Multiply Real Gleitpunktzahlen multiplizieren 8-5

Negate Binary Input Binären Eingang negieren 4-8

Negate Real Number Vorzeichen einer Gleitpunktzahl wechseln 10-13

Negative RLO Edge Detection Flanke 1 → 0 abfragen 4-29

OR ODER-Verknüpfung 4-4

Off-Delay S5 Timer (timer instruction) Zeit als Ausschaltverzögerung starten (SA) 5-13



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Off-Delay Timer (bit logic instruction) Zeit als Ausschaltverzögerung starten (SA) 4-26

On-Delay S5 Timer (timer instruction) Zeit als Einschaltverzögerung starten (SE) 5-9

On-Delay Timer (bit logic instruction) Zeit als Einschaltverzögerung starten (SE) 4-22

Ones Complement Double Integer 1er Komplement zu Ganzzahl (32 Bit) erzeugen 10-10

Ones Complement Integer 1er Komplement zu Ganzzahl (16 Bit) erzeugen 10-9

Open Data Block: DB or DI Datenbaustein öffnen 13-2

Positive RLO Edge Detection Flanke 0 → 1 abfragen 4-28

Pulse S5 Timer (timer instruction) Zeit als Impuls starten (SI) 5-5

Pulse Timer (bit logic instruction) Zeit als Impuls starten (SI) 4-18

Reset Output Ausgang rücksetzen 4-13

Reset_Set Flip Flop Flipflop rücksetzen setzen 4-33

Result Bit Equal 0 Ergebnisbit bei gleich 0 15-4

Result Bit Greater Equal 0 Ergebnisbit bei größer gleich 0 15-4

Result Bit Greater Than 0 Ergebnisbit bei größer als 0 15-4

Result Bit Less Equal 0 Ergebnisbit bei kleiner gleich 0 15-4

Result Bit Less Than 0 Ergebnisbit bei kleiner 0 15-4

Result Bit Not Equal 0 Ergebnisbit bei ungleich 0 15-4

Retentive On-Delay S5 Timer (timer instruction)Zeit als speich. Einschaltverzögerung starten (SS) 5-11

Retentive On-Delay Timer(Bitverknüpfungsperation)

Zeit als speich. Einschaltverzögerung starten (SS) 4-24

Return Springe zurück 16-7

Return Fraction Double Integer Divisionsrest gewinnen (32 Bit) 7-10

Rotate Left Double Word 32 Bit links rotieren 12-11

Rotate Right Double Word 32 Bit rechts rotieren 12-12

Round to Double Integer Zahl runden 10-14

Save RLO to BR Memory Verknüpfungsergebnis ins BIE-Register laden 4-11

Set Output Ausgang setzen 4-12

Set Counter Value Zähleranfangswert setzen 4-14

Set_Reset Flip Flop Flipflop setzen rücksetzen 4-32

Shift Left Double Word 32 Bit links schieben 12-4

Shift Left Word 16 Bit links schieben 12-3

Shift Right Double Integer Ganzzahl (32 Bit) rechts schieben 12-9

Shift Right Double Word 32 Bit rechts schieben 12-6

Shift Right Integer Ganzzahl (16 Bit) rechts schieben 12-8

Shift Right Word 16 Bit rechts schieben 12-5

Subtract Double Integer Ganze Zahlen subtrahieren (32 Bit) 7-5

Subtract Integer Ganze Zahlen subtrahieren (16 Bit) 7-4

Subtract Real Gleitpunktzahlen subtrahieren 8-4





Truncate Double Integer Part Ganze Zahl erzeugen 10-15

Twos Complement Double Integer 2er Komplement zu Ganzzahl (32 Bit) erzeugen 10-12

Twos Complement Integer 2er Komplement zu Ganzzahl (16 Bit) erzeugen 10-11

Up Counter (counter instruction) Vorwärtszählen 6-5

Up Counter (bit logic instruction) Vorwärtszählen 4-16

Up-Down Counter Vorwärts-/Rückwärtszählen 6-3

(Word) AND Double Word 32 Bit UND verknüpfen 11-4

(Word) AND Word 16 Bit UND verknüpfen 11-3

(Word) Exclusive OR Double Word 32 Bit EXKLUSIV ODER verknüpfen 11-8

(Word) Exclusive OR Word 16 Bit EXKLUSIV ODER verknüpfen 11-7

(Word) OR Double Word 32 Bit ODER verknüpfen 11-6

(Word) OR Word 16 Bit ODER verknüpfen 11-5



C79000-G7076-C566-01

A.3 List of Instructions with German SIMATIC Names

Table A-3 contains an alphabetical list of FBD instructions with the Germanfull names, the corresponding short name or mnemonic, and the reference tothe page on which the instruction is described.

Table A-3 FBD Instructions Arranged Alphabetically by German Full Names, with Short Names

Full Name SIMATIC Short Name Page

1er Komplement zu Ganzzahl (16 Bit) erzeugen INV_I 10-9

1er Komplement zu Ganzzahl (32 Bit) erzeugen INV_DI 10-10

2er Komplement zu Ganzzahl (16 Bit) erzeugen NEG_I 10-11

2er Komplement zu Ganzzahl (32 Bit) erzeugen NEG_DI 10-12

16 Bit EXKLUSIV ODER verknüpfen WXOR_W 11-7

16 Bit links schieben SHL_W 12-2

16 Bit ODER verknüpfen WOR_W 11-5

16 Bit rechts schieben SHR_W 12-5

16 Bit UND verknüpfen WAND_W 11-3

32 Bit EXKLUSIV ODER verknüpfen WXOR_DW 11-8

32 Bit links rotieren ROL_DW 12-11

32 Bit links schieben SHL_DW 12-4

32 Bit ODER verknüpfen WOR_DW 11-6

32 Bit rechts rotieren ROR_DW 12-12

32 Bit rechts schieben SHR_DW 12-6

32 Bit UND verknüpfen WAND_DW 11-4

Absolutwert einer Gleitpunktzahl bilden ABS 8-8

Arcuscosinus einer Gleitpunktzahl bilden ACOS 8-13

Arcussinus einer Gleitpunktzahl bilden ASIN 8-13

Arcustangens einer Gleitpunktzahl bilden ATAN 8-13

Ausgang rücksetzen R 4-13

Ausgang setzen S 4-12

Aus Gleitpunktzahl nächsthöhere Ganzzahl erzeugen CEIL 10-16

Aus Gleitpunktzahl nächstniedere Ganzzahl erzeugen FLOOR 10-17

BCD-Zahl in Ganzzahl (16 Bit) wandeln BCD_I 10-3

BCD-Zahl in Ganzzahl (32 Bit) wandeln BCD_DI 10-6

Binären Eingang einfügen –––| 4-7

Binären Eingang negieren –––o| 4-8

Cosinus einer Gleitpunktzahl bilden COS 8-13

Datenbaustein öffnen AUF 13-2

Divisionsrest gewinnen (32 Bit) MOD 7-10

Ergebnisbit bei gleich 0 ==0 15-4

Ergebnisbit bei größer als 0 >0 15-4



Table A-3 FBD Instructions Arranged Alphabetically by German Full Names, with Short Names, cont.

Full Name PageSIMATIC Short Name

Ergebnisbit bei größer gleich 0 >=0 15-4

Ergebnisbit bei kleiner 0 <0 15-4

Ergebnisbit bei kleiner gleich 0 <=0 15-4

Ergebnisbit bei ungleich 0 <>0 15-4

EXKLUSIV-ODER-Verknüpfung XOR 4-6

Exponentialwert einer Gleitpunktzahl bilden EXP 8-12

FB aufrufen CALL_FB 16-4

FC aufrufen CALL_FC 16-4

FC/SFC aufrufen ohne Parameter CALL 16-2

Flanke 0 → 1 abfragen P 4-28

Flanke 1 → 0 abfragen N 4-29

Flipflop rücksetzen setzen RS 4-33

Flipflop setzen rücksetzen SR 4-32

Ganze Zahlen addieren (16 Bit) ADD_I 7-2

Ganze Zahlen addieren (32 Bit) ADD_DI 7-3

Ganze Zahlen dividieren (16 Bit) DIV_I 7-8

Ganze Zahlen dividieren (32 Bit) DIV_DI 7-9

Ganze Zahlen multiplizieren (16 Bit) MUL_I 7-6

Ganze Zahlen multiplizieren (32 Bit) MUL_DI 7-7

Ganze Zahlen subtrahieren (16 Bit) SUB_I 7-4

Ganze Zahlen subtrahieren (32 Bit) SUB_DI 7-5

Ganze Zahlen vergleichen (16 Bit) CMP >=I 9-2

Ganze Zahlen vergleichen (32 Bit) CMP >=D 9-3

Ganze Zahl erzeugen TRUNC 10-15

Ganzzahl (16 Bit) in Ganzzahl (32 Bit) wandeln I_DI 10-5

Ganzzahl (16 Bit) in BCD-Zahl wandeln I_BCD 10-4

Ganzzahl (16 Bit) rechts schieben SHR_I 12-8

Ganzzahl (32 Bit) in BCD-Zahl wandeln DI_BCD 10-7

Ganzzahl (32 Bit) in Gleitpunktzahl wandeln DI_R 10-8

Ganzzahl (32 Bit) rechts schieben SHR_DI 12-9

Gleitpunktzahlen addieren ADD_R 8-3

Gleitpunktzahlen dividieren DIV_R 8-6

Gleitpunktzahlen multiplizieren MUL_R 8-5

Gleitpunktzahlen subtrahieren SUB_R 8-4

Gleitpunktzahlen vergleichen CMP >=R 9-4

Konnektor # 4-10

Master Control Relay Anfang MCRA 16-10

Master Control Relay ausschalten MCR> 16-13



C79000-G7076-C566-01



Master Control Relay einschalten MCR< 16-13

Master Control Relay Ende MCRD 16-10

Natürlichen Logarithmus einer Gleitpunktzahl bilden LN 8-11

ODER-Verknüpfung >=1 4-4

Quadrat einer Gleitpunktzahl bilden SQR 8-9

Quadratwurzel einer Gleitpunktzahl bilden SQRT 8-10

Rückwärtszählen (Zähloperation) Z_RUECK 6-7

Rückwärtszählen (Bitverknüpfungsoperation) ZR 4-17

Signalflanke 0 → 1 abfragen POS 4-30

Signalflanke 1 → 0 abfragen NEG 4-31

Sinus einer Gleitpunktzahl bilden SIN 8-13

Springe wenn 0 JMPN 14-5

Springe wenn 1 JMP 14-3

Springe zurück RET 16-7

Störungsbit BIE-Register BIE 15-3

Störungsbit Überlauf OV 15-7

Störungsbit Überlauf gespeichert OS 15-8

Störungsbit Ungültige Operation UO 15-6

System FB aufrufen CALL_SFB 16-4

System FC aufrufen CALL_SFC 16-4

Tangens einer Gleitpunktzahl bilden TAN 8-13

UND-Verknüpfung & 4-3

Verknüpfungsergebnis ins BIE-Register laden SAVE 4-11

Vorwärts-/Rückwärtszählen ZAEHLER 6-3

Vorwärtszählen (Zähloperation) Z_VORW 6-5

Vorwärtszählen (Bitverknüpfungsoperation) ZV 4-16

Vorzeichen einer Gleitpunktzahl wechseln NEG_R 10-13

Wert übertragen MOVE 10-2

Zahl runden ROUND 10-14

Zähleranfangswert setzen SZ 4-14

Zeit als Ausschaltverzögerung starten (SA) (Zeitoperation) S_AVERZ 5-13

Zeit als Ausschaltverzögerung starten (SA) (Bitverknüpfungsoperation)SA 4-26

Zeit als Einschaltverzögerung starten (SE) (Zeitoperation) S_EVERZ 5-9

Zeit als Einschaltverzögerung starten (SE) (Bitverknüpfungsoperation)SE 4-22

Zeit als Impuls starten (SI) (Zeitoperation) S_IMPULS

Zeit als Impuls starten (SI) (Bitverknüpfungsoperation) SI 4-18

Zeit als speich. Einschaltverzögerung starten (SS) (Zeitoperation) S_SEVERZ 5-11





Zeit als speich. Einschaltverzögerung starten (SS)(Bitverknüpfungsoperation)

SS 4-24

Zeit als verlängerten Impuls starten (SV) (Zeitoperation) S_VIMP 5-7

Zeit als verlängerten Impuls starten (SV) (Bitverknüpfungsoperation) SV 4-20

Zuweisung = 4-9



C79000-G7076-C566-01

A.4 List of Instructions with German Names and International (English)Equivalents

Table A-4 contains an alphabetical list of FBD instructions with GermanSIMATIC full names, the international (English) equivalents, and thereference to the page on which the instruction is described.

Table A-4 FBD Instructions Arranged Alphabetically by German Full Names with International (English)Equivalents

SIMATIC Full Name International (English) Equivalent Page

1er Komplement zu Ganzzahl (16 Bit) erzeugen Ones Complement Integer 10-9

1er Komplement zu Ganzzahl (32 Bit) erzeugen Ones Complement Double Integer 10-10

2er Komplement zu Ganzzahl (16 Bit) erzeugen Twos Complement Integer 10-11

2er Komplement zu Ganzzahl (32 Bit) erzeugen Twos Complement Double Integer 10-12

16 Bit EXKLUSIV ODER verknüpfen (Word) Exclusive OR Word 11-7

16 Bit links schieben Shift Left Word 12-2

16 Bit ODER verknüpfen (Word) OR Word 11-5

16 Bit rechts schieben Shift Right Word 12-5

16 Bit UND verknüpfen (Word) AND Word 11-3

32 Bit EXKLUSIV ODER verknüpfen (Word) Exclusive OR Double Word 11-8

32 Bit links rotieren Rotate Left Double Word 12-11

32 Bit links schieben Shift Left Double Word 12-4

32 Bit ODER verknüpfen (Word) OR Double Word 11-6

32 Bit rechts rotieren Rotate Right Double Word 12-12

32 Bit rechts schieben Shift Right Double Word 12-6

32 Bit UND verknüpfen (Word) AND Double Word 11-4

Absolutwert einer Gleitpunktzahl bilden Form the Absolute Value of a Floating-PointNumber

8-8

Arcuscosinus einer Gleitpunktzahl bilden Form the Arc Cosine of a Floating-Point Number8-13

Arcussinus einer Gleitpunktzahl bilden Form the Arc Sine of a Floating-Point Number 8-13

Arcustangens einer Gleitpunktzahl bilden Form the Arc Tangent of a Floating-PointNumber

8-13

Ausgang rücksetzen Reset Output 4-13

Ausgang setzen Set Output 4-12

Aus Gleitpunktzahl nächsthöhere Ganzzahl erzeugenCeiling 10-16

Aus Gleitpunktzahl nächstniedere Ganzzahl erzeugenFloor 10-17

BCD-Zahl in Ganzzahl (16 Bit) wandeln BCD to Integer 10-3

BCD-Zahl in Ganzzahl (32 Bit) wandeln BCD to Double Integer 10-6

Binären Eingang einfügen Insert Binary Input 4-7

Binären Eingang negieren Negate Binary Input 4-8

Cosinus einer Gleitpunktzahl bilden Form the Cosine of a Floating-Point Number 8-13

Datenbaustein öffnen Open Data Block: DB or DI 13-2



Table A-4 FBD Instructions Arranged Alphabetically by German Full Names with International (English)Equivalents, cont.

SIMATIC Full Name PageInternational (English) Equivalent

Divisionsrest gewinnen (32 Bit) Return Fraction Double Integer 7-10

Ergebnisbit bei gleich 0 Result Bit Equal 0 15-4

Ergebnisbit bei größer als 0 Result Bit Greater Than 0 15-4

Ergebnisbit bei größer gleich 0 Result Bit Greater Equal 0 15-4

Ergebnisbit bei kleiner 0 Result Bit Less Than 0 15-4

Ergebnisbit bei kleiner gleich 0 Result Bit Less Equal 0 15-4

Ergebnisbit bei ungleich 0 Result Bit Not Equal 0 15-4

EXKLUSIV-ODER-Verknüpfung Exclusive OR 4-6

Exponentialwert einer Gleitpunktzahl bilden Form the Exponential Value of a Floating-PointNumber

8-12

FB aufrufen Call FB from Box 16-4

FC aufrufen Call FC from Box 16-4

FC/SFC aufrufen ohne Parameter Call FC SFC (without parameters) 16-2

Flanke 0 → 1 abfragen Positive RLO Edge Detection 4-28

Flanke 1 → 0 abfragen Negative RLO Edge Detection 4-29

Flipflop rücksetzen setzen Reset_Set Flip Flop 4-33

Flipflop setzen rücksetzen Set_Reset Flip Flop 4-32

Ganze Zahlen addieren (16 Bit) Add Integer 7-2

Ganze Zahlen addieren (32 Bit) Add Double Integer 7-3

Ganze Zahlen dividieren (16 Bit) Divide Integer 7-8

Ganze Zahlen dividieren (32 Bit) Divide Double Integer 7-9

Ganze Zahlen multiplizieren (16 Bit) Multiply Integer 7-6

Ganze Zahlen multiplizieren [32 Bit) Multiply Double Integer 7-7

Ganze Zahlen subtrahieren (16 Bit) Subtract Integer 7-4

Ganze Zahlen subtrahieren (32 Bit) Subtract Double Integer 7-5

Ganze Zahlen vergleichen (16 Bit) Compare Integer (>, <, ==, <>, <=, >=) 9-2

Ganze Zahlen vergleichen (32 Bit) Compare Double Integer (>, <, ==, <>, <=, >=) 9-3

Ganze Zahl erzeugen Truncate Double Integer Part 10-15

Ganzzahl (16 Bit) in Ganzzahl (32 Bit) wandeln Integer to Double Integer 10-5

Ganzzahl (16 Bit) in BCD-Zahl wandeln Integer to BCD 10-4

Ganzzahl (16 Bit) rechts schieben Shift Right Integer 12-8

Ganzzahl (32 Bit) in BCD-Zahl wandeln Double Integer to BCD 10-7

Ganzzahl (32 Bit) in Gleitpunktzahl wandeln Double Integer to Real 10-8

Ganzzahl (32 Bit) rechts schieben Shift Right Double Integer 12-9

Gleitpunktzahlen addieren Add Real 8-3

Gleitpunktzahlen dividieren Divide Real 8-6

Gleitpunktzahlen multiplizieren Multiply Real 8-5

Gleitpunktzahlen subtrahieren Subtract Real 8-4



C79000-G7076-C566-01



Gleitpunktzahlen vergleichen Compare Real (>, <, ==, <>, <=, >=) 9-4

Konnektor Midline Output 4-10

Master Control Relay Anfang Master Control Relay Activate 16-10

Master Control Relay ausschalten Master Control Relay Off 16-13

Master Control Relay einschalten Master Control Relay On 16-13

Master Control Relay Ende Master Control Relay Deactivate 16-10

Natürlichen Logarithmus einer Gleitpunktzahl bildenForm the Natural Algorithm of a Floating-PointNumber

8-11

Quadrat einer Gleitpunktzahl bilden Form the Square of a Floating-Point Number 8-9

Quadratwurzel einer Gleitpunktzahl bilden Form the Square Root of a Floating-PointNumber

8-10

ODER-Verknüpfung OR 4-4

Rückwärtszählen (Zähloperation) Down Counter 6-7

Rückwärtszählen (Bitverknüpfungsoperation) Down Counter 4-17

Signalflanke 0→1 abfragen Address Positive Edge Detection 4-30

Signalflanke 1→0 abfragen Address Negative Edge Detection 4-31

Sinus einer Gleitpunktzahl bilden Form the Sine of a Floating-Point Number 8-13

Springe wenn 0 Jump-If-Not 14-5

Springe wenn 1 Jump 14-3

Springe zurück Return 16-7

Störungsbit BIE-Register Exception Bit Binary Result 15-3

Störungsbit Überlauf Exception Bit Overflow 15-7

Störungsbit Überlauf gespeichert Exception Bit Overflow Stored 15-8

Störungsbit Ungültige Operation Exception Bit Unordered 15-6

System FB aufrufen Call System FB from Box 16-4

System FC aufrufen Call System FC from Box 16-4

Tangens einer Gleitpunktzahl bilden Form the Tangent of a Floating-Point Number 8-13

UND-Verknüpfung AND 4-3

Verknüpfungsergebnis ins BIE-Register laden Save RLO to BR Memory 4-11

Vorwärts-/Rückwärtszählen Up-Down Counter 6-3

Vorwärtszählen (Zähloperation) Up Counter 6-5

Vorwärtszählen (Bitverknüpfungsoperation) Up Counter 4-16

Vorzeichen einer Gleitpunktzahl wechseln Negate Real Number 10-13

Wert übertragen Assign a Value 10-2

Zahl runden Round to Double Integer 10-14

Zähleranfangswert setzen Set Counter Value 4-14

Zeit als Ausschaltverzögerung starten (SA)(Zeitoperation)

Off-Delay S5 Timer 5-13





Zeit als Ausschaltverzögerung starten (SA)(Bitverknüpfungsoperation)

Off-Delay Timer 4-26

Zeit als Einschaltverzögerung starten (SE)(Zeitoperation)

On-Delay S5 Timer 5-9

Zeit als Einschaltverzögerung starten (SE)(Bitverknüpfungsoperation)

On-Delay Timer 4-22

Zeit als Impuls starten (SI) (Zeitoperation) Pulse S5 Timer 5-5

Zeit als Impuls starten (SI) (Bitverknüpfungsoperation)Pulse Timer 4-18

Zeit als speich. Einschaltverzögerung starten (SS)(Zeitoperation)

Retentive On-Delay S5 Timer 5-11

Zeit als speich. Einschaltverzögerung starten (SS)(Bitverknüpfungsoperation)

Retentive On-Delay Timer 4-22

Zeit als verlängerten Impuls starten (SV)(Zeitoperation)

Extended Pulse S5 Timer 5-7

Zeit als verlängerten Impuls starten (SV)(Bitverknüpfungsoperation)

Extended Pulse Timer 4-20

Zuweisung Assign 4-9

Table A-5 FBD Instructions Listed in this Manual with their International Full and Short Names and theirSIMATIC Short Names

SIMATIC Full Name International ShortName

SIMATIC Short Name Page

Down Counter (counter instruction) S_CD Z_RUECK 6-7

Down Counter (bit logic instruction) CD ZR 4-17

Exception Bit Binary Result BR BIE 15-3

Extended Pulse S5 Timer (timer instruction) S_PEXT S_VIMP 5-7

Extended Pulse Timer (bit logic instruction) SE SV 11-5

Off-Delay S5 Timer (timer instruction) S_OFFDT S_AVERZ 5-13

Off-Delay Timer (bit logic instruction) SF SA 4-26

On-Delay S5 Timer (timer instruction) S_ODT S_EVERZ 5-9

On-Delay Timer (bit logic instruction) SD SE 4-22

Open Data Block: DB or DI OPN AUF 13-2

Pulse S5 Timer (timer instruction) S_PULSE S_IMPULS 5-5

Pulse Timer (bit logic instruction) SP SI 4-18

Retentive On-Delay S5 Timer (timerinstruction)

S_ODTS S_SEVERZ 5-11

Retentive On-Delay Timer (bit logicinstruction)

SS SS 4-24

Set Counter Value SC SZ 4-14

Up Counter (counter instruction) S_CU Z_VORW 6-5



C79000-G7076-C566-01

Table A-5 FBD Instructions Listed in this Manual with their International Full and Short Names and theirSIMATIC Short Names, continued

SIMATIC Full Name PageSIMATIC Short NameInternational ShortName

Up Counter (bit logic instruction) CU ZV 4-16

Up-Down Counter S_CUD ZAEHLER 6-3


B-1Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

Programming Examples


B.1 Overview B-2

B.2 Bit Logic Instructions B-3

B.3 Timer Instructions B-7

B.4 Counter and Comparison Instructions B-11

B.5 Integer Math Instructions B-13

B.6 Word Logic Instructions B-14

ChapterOverview

B

B-2Function Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01

B.1 Overview

Each FBD instruction described in this manual executes a specific function.When you combine these instructions into a program, you can accomplish awide variety of automation tasks. This chapter provides the followingexamples of practical applications of the FBD instructions:

� Controlling a conveyor belt using bit logic instructions

� Detecting direction of movement on a conveyor belt using bit logicinstructions

� Generating a clock pulse using timer instructions

� Keeping track of storage space using counter and comparison instructions

� Solving a problem using integer math instructions

� Setting the length of time for heating an oven

The examples in this chapter use the following instructions:

� Add Integer (ADD_I)

� AND

� Assign (=)

� Assign a Value (MOVE)

� Compare Integer (CMP_I>=)

� Compare Integer (CMP_I<=)

� Divide Integer (DIV_I)

� Down Counter (S_CD)

� Extended Pulse Timer (SE)

� Jump-If-Not (JMPN)

� Multiply Integer (MUL_I)

� OR

� Positive RLO Edge Detection (P)

� Reset Output (R)

� Return (RET)

� Set Output (S)

� Up Counter (S_CU)

� (Word) AND Word (WAND_W)

� (Word) OR Word (WOR_W)

PracticalApplications

Instructions Used



B.2 Bit Logic Instructions

Figure B-1 shows a conveyor belt that can be activated electrically. There aretwo push button switches at the beginning of the belt: S1 for START and S2for STOP. There are also two push button switches at the end of the belt: S3for START and S4 for STOP. It it possible to start or stop the belt from eitherend. Sensor S5 stops the belt when an item on the belt reaches the end.

You can write a program to control the conveyor belt shown in Figure B-1using symbols that represent the various components of the conveyor system.If you choose this method, you need to make a symbol table to correlate thesymbols you choose with absolute values (see Table B-1). You define thesymbols in the symbol table (see the STEP 7 Online Help).

Table B-1 Elements of Symbolic Programming for Conveyor Belt System

System ComponentAbsoluteAddress

Symbol Symbol Table

Start button I1.1 S1 I1.1 S1

Stop button I1.2 S2 I1.2 S2

Start button I1.3 S3 I1.3 S3

Stop button I1.4 S4 I1.4 S4

Sensor I1.5 S5 I1.5 S5

Motor Q4.0 MOTOR_ON Q4.0 MOTOR_ON

MOTOR_ON

S1S2

� Start� Stop

S3S4

� Start� Stop

Sensor S5

Figure B-1 Conveyor Belt System

Controlling aConveyor Belt

SymbolicProgramming



C79000-G7076-C566-01

You can write a program to control the conveyor belt shown in Figure B-1using absolute values that represent the different components of the conveyorsystem (see Table B-2). Figure B-2 shows an FBD program to control theconveyor belt.

Table B-2 Elements of Absolute Programming for Conveyor Belt System

System Component Absolute Address

Start button I1.1

Stop button I1.2

Start button I1.3

Stop button I1.4

Sensor I1.5

Motor Q4.0

Q4.0I1.1

I1.3

Network 1: Pressing either start button turns the motor on.

Network 2: Pressing either stop button or the sensor at the end of the belt responding turns themotor off.

Q4.0

I1.2

I1.4

E1.5

>=1

S

>=1

R

Figure B-2 Function Block Diagram to Control a Conveyor Belt

AbsoluteProgramming



Figure B-3 shows a conveyor belt that is equipped with two photoelectricbarriers (PEB1 and PEB2) that are designed to detect the direction in which apackage is moving on the belt.

You can write a program to activate a direction display for the conveyor beltsystem shown in Figure B-3 using symbols that represent the variouscomponents of the conveyor system, including the photoelectric barriers thatdetect direction. If you choose this method, you need to make a symbol tableto correlate the symbols you choose with absolute values (see Table B-3).You define the symbols in the symbol table (see the STEP 7 Online Help).

Table B-3 Elements of Symbolic Programming for Detecting Direction

System ComponentAbsoluteAddress

Symbol Symbol Table

Photoelectric barrier 1 I0.0 PEB1 I0.0 PEB1

Photoelectric barrier 2 I0.1 PEB2 I0.1 PEB2

Display for movement to right Q4.0 RIGHT Q4.0 RIGHT

Display for movement to left Q4.1 LEFT Q4.1 LEFT

Clock memory bit 1 M0.0 PM1 M0.0 PM1

Clock memory bit 2 M0.1 PM2 M0.1 PM2

You can write a program to activate the direction display for the conveyorbelt shown in Figure B-3 using absolute values that represent thephotoelectric barriers that detect direction (see Table B-4). Figure B-4 showsan FBD program to control the direction display for the conveyor belt.

PEB1PEB2 Q4.1Q4.0

Figure B-3 Conveyor Belt System with Photoelectric Light Barriers for DetectingDirection

Detecting theDirection of aConveyor Belt

SymbolicProgramming

AbsoluteProgramming



C79000-G7076-C566-01

Table B-4 Elements of Absolute Programming for Detecting Direction

System Component Absolute Address

Photoelectric barrier 1 I0.0

Photoelectric barrier 2 I0.1

Display for movement to right Q4.0

Display for movement to left Q4.1

Clock memory bit 1 M0.0

Clock memory bit 2 M0.1

Q4.1I0.0

Network 1: If there is a transition in signal state from 0 to 1 (rising edge) at input I0.0 and, at the sametime, the signal state at input I0.1 is 0, then the package on the belt is moving to the left.

I0.1

M 0.0

Network 2: If there is a transition in signal state from 0 to 1 (rising edge) at input I0.1 and, at the sametime, the signal state at input I0.0 is 0, then the package on the belt is moving to the right.

I0.1

If one of the photoelectric light barriers is interrupted, this means that there is a package between thebarriers.

I0.0

I0.1

Q4.1

P &

S

Q4.0

I0.0

M 0.1

P &

S

&Q4.0

R

R

Figure B-4 Function Block Diagram for Detecting the Direction of a Conveyor Belt



B.3 Timer Instructions

You can use a clock pulse generator or flasher relay when you want toproduce a signal that is repeated periodically. Clock pulse generators arecommonly found in signaling systems that control flashing indicator lamps.

When you use the S7-300, you can implement the clock pulse generatorfunction by using time-driven program execution in special organizationblocks. The example shown in the following FBD program illustrates the useof timer functions to generate a clock pulse.

The following example shows how to implement a freewheeling clock pulsegenerator by using a timer (pulse duty factor 1:1). The frequency is dividedinto the values listed in Table B-5.

Clock PulseGenerator



C79000-G7076-C566-01

MW100

T1

S5T#250MS

M0.2

Network 1: If the signal state of timer T1 is 0, load the time value 250 ms into T1 and start T1 as anextended-pulse timer.

Network 4: When the timer T1 expires, the memory word 100 is incremented by 1.

ADD_I

IN1

ENO

EN

IN2

OUTMW100

1

MW100

MOVE

IN ENO

EN OUT QW12

N001

Network 2: The state of the timer is saved temporarily in an auxiliary memory bit.

M0.2

TV

SE

=T1

??.?

??.?

&

N001

Network 3: If the signal state of timer T1 is 1, jump to jump label N001.

JMP

&

M0.2 &

Network 5: The MOVE instruction allows you to output the different clock frequencies atoutputs Q12.0 through Q13.7.

Figure B-5 Function Block Diagram to Generate a Clock Pulse



A signal check of timer T1 produces the result of logic operation (RLO, seeSection 2.3) shown in Figure B-6.

0

1

250 ms

Figure B-6 RLO for the Negated Input Parameter AN T1 in the Clock Pulse TimerExample

As soon as the time runs out, the timer is restarted. Because of this, the signalcheck made by AN M0.2 produces signal state 1 only briefly.

Figure B-7 shows the negated (inverted) RLO bit.

0

1

250 ms

Figure B-7 Negated RLO Bit of Timer T1 in the Clock Pulse Timer Example

Every 250 ms the RLO bit is 0. The jump is ignored and the content ofmemory word MW100 is incremented by 1.

Table B-5 lists the frequencies that you can achieve from the individual bitsof memory bytes MB101 and MB100. Network 5 in the FBD diagram shownin Figure B-5 illustrates how the MOVE instruction allows you to see thedifferent clock frequencies at outputs Q12.0 through Q13.7.

Table B-5 Frequencies for Clock Pulse Timer Example

Bits inMB101/MB100

Frequency in Hz Duration

M101.0 2.0 0.5 s (250 ms on/250 ms off)

M101.1 1.0 1 s (0.5 s on/0.5 s off)

M101.2 0.5 2 s (1 s on/1 s off)

M101.3 0.25 4 s (2 s on/2 s off)

M101.4 0.125 8 s (4 s on/4 s off)

M101.5 0.0625 16 s (8 s on/8 s off)

M101.6 0.03125 32 s (16 s on/16 s off)

M101.7 0.015625 64 s (32 s on/32 s off)

M100.0 0.0078125 128 s (64 s on/64 s off)

M100.1 0.0039062 256 s (128 s on/128 s off)

M100.2 0.0019531 512 s (256 s on/256 s off)

Achieving aSpecificFrequency



C79000-G7076-C566-01

Table B-5 Frequencies for Clock Pulse Timer Example

Bits inMB101/MB100

DurationFrequency in Hz

M100.3 0.0009765 1024 s (512 s on/512 s off)

M100.4 0.0004882 2048 s (1024 s on/1024 s off)

M100.5 0.0002441 4096 s (2048 s on/2048 s off)

M100.6 0.000122 8192 s (4096 s on/4096 s off)

M100.7 0.000061 16384 s (8192 s on/8192 s off)

Table B-6 lists the signal states of the bits of memory byte MB101.Figure B-8 shows the signal state of memory bit M101.1.

Table B-6 Signal States of the Bits of Memory Byte MB101

Scan Signal State of Bits of Memory Byte MB101 TimeValue

Cycle 7 6 5 4 3 2 1 0Valuein ms

0 0 0 0 0 0 0 0 0 250

1 0 0 0 0 0 0 0 1 250

2 0 0 0 0 0 0 1 0 250

3 0 0 0 0 0 0 1 1 250

4 0 0 0 0 0 1 0 0 250

5 0 0 0 0 0 1 0 1 250

6 0 0 0 0 0 1 1 0 250

7 0 0 0 0 0 1 1 1 250

8 0 0 0 0 1 0 0 0 250

9 0 0 0 0 1 0 0 1 250

10 0 0 0 0 1 0 1 0 250

11 0 0 0 0 1 0 1 1 250

12 0 0 0 0 1 1 0 0 250

M101.1

250 ms 0.5 s 0.75 s 1 s 1.25 s 1.5 s

T

Time01

Frequency� 1T�

11 s

� 1Hz

0

Figure B-8 Signal State of Bit 1 of MB101 (M101.1)



B.4 Counter and Comparison Instructions

Figure B-9 shows a system with two conveyor belts and a temporary storagearea in between them. Conveyor belt 1 delivers packages to the storage area.A photoelectric barrier at the end of conveyor belt 1 near the storage areadetects how many packages are delivered to the storage area. Conveyor belt 2transports packages from the temporary storage area to a loading dock wheretrucks take the packages away for delivery to customers. A photoelectricbarrier at the end of conveyor belt 2 near the storage area detects how manypackages leave the storage area to go to the loading dock.

A display panel with five lamps indicates the fill level of the temporarystorage area. Figure B-10 shows the FBD program that activates the indicatorlamps on the display panel.

Storage areaempty

Display panel

Storage areafilled to capacity

Storage area90% full

Storage area50% full

Storage areanot empty

Packages in Packages outI0.0 I0.1

Conveyor belt 2Conveyor belt 1

Photoelectric barrier 1 Photoelectric barrier 2

Temporarystorage for 100packages

(Q12.0) (Q12.1) (Q15.2) (Q15.3) (Q15.4)

Figure B-9 Storage Area with Counter and Comparator

Storage Area withCounter andComparator



C79000-G7076-C566-01

MW200

Network 2: Q12.0 indicates ”storage area not empty”.

Network 3: If 50 is less than or equal to the counter value (in other words if the current counter valueis greater than or equal to 50), the indicator lamp for “storage area 50% full” is lit.

CMP

IN150 Q15.2

IN2

Network 4: If the counter value is greater than or equal to 90, the indicator lamp for “storage area 90%full” is lit.

CMP

IN1

>= I

90

MW200 Q15.3

IN2

<= I

Network 5: If the counter value is greater than or equal to 100, the indicator lamp for “storage area full”is lit. Use output Q4.4 to interlock conveyor belt 1.

CMP

IN1

>= I

100

MW200 Q15.4

IN2

Q12.1

Q12.0

=

=

=

=

Network 1: Counter C1 counts up at each signal change from 0 to 1 at input CU and counts down ateach signal change from 0 to 1 at input CD. With a signal change from 0 to ”1” at input S, the countervalue is set to the value PV. A signal change from 0 to 1 at input R resets the counter value to 0.MW200 contains the current counter value of C1. Q12.1 indicates “storage area not empty”.

S_CUD

CD

Q

CU

S

PV

CV

R

CV_BCD

C1

MW210

MW200

=

Q12.1

I12.0

I12.1

I12.2

C#10

I12.3

&

Figure B-10 Function Block Diagram for Activating Indicator Lamps on a Display Panel



B.5 Integer Math Instructions

The following sample program shows you how to use three integer mathinstructions and the L and T instructions to produce the same result as thefollowing equation:

MW4�(IW0�DBW3)� 15

MW0

DB1

Network 1: Open Data Block DB1

Network 2: Input word IW0 is added to shared data word DBW3 (data block must be defined andopened) and the sum is loaded into memory word MW100. MW100 is then multiplied by 15 and theanswer stored in memory word MW102. MW102 is divided by MW0 with the result stored in MW4. Aslong as all results are in the permitted range of each instruction, the ENO passes a signal state of 1 tothe next box.

ADD_I

IN1

ENO

EN

IN2

OUT

DBW3

IW0 MW100MUL_I

IN1

ENO

EN

IN2

OUTMW100

15

MW102DIV_I

IN1

ENO

EN

IN2

OUTMW102

MW0

MW4

OPN

??.?

Figure B-11 Function Block Diagram for Integer Math Instructions

Solving a MathProblem



C79000-G7076-C566-01

B.6 Word Logic Instructions

The operator of the oven shown in Figure B-12 starts the oven heating bypushing the start push button. The operator can set the length of time forheating by using the thumbwheel switches shown in the figure. The valuethat the operator sets indicates seconds in binary coded decimal (BCD)format. Table B-7 lists the components of the heating system and theircorresponding absolute addresses used in the sample program shown inFigure B-12.

Table B-7 Heating System Components and Corresponding Absolute Addresses

System Component Absolute Address in FBD Program

Start button I0.7

Thumbwheel for ones I1.0 to I1.3

Thumbwheel for tens I1.4 to I1.7

Thumbwheel for hundreds I0.0 to I0.3

Start heating Q4.0

OvenÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

1 0 0 1 0 0 0 1X X X X 0 0 0 1

HeatQ4.0

Thumbwheels for setting BCD digits

IW0

4 4 4

Start button I0.7

7....

IB1IB0 Bytes

Bits7......0 ...0

Figure B-12 Using the Inputs and Outputs for a Time-Limited Heating Process

Heating an Oven



T1

Q4.0

Network 1: If the timer is running, then turn on the heater. If the timer is running, the Return instructionends the processing here.

Network 3: Mask input bits I0.4 through I0.7 (that is, reset them to 0). These bits of the thumbwheelinputs are not used. The 16 bits of the thumbwheel inputs are combined with W#16#0FFF accordingto the (Word) And Word instruction. The result is loaded into memory word MW1. In order to set thetime base of seconds, the preset value is combined with W#16#2000 according to the (Word) OrWord instruction, setting bit 13 to 1 and resetting bit 12 to 0.

Network 4: Start timer T1 as an extended pulse timer if the start push button is pressed, loading as apreset value memory word MW2 (derived from the logic above).

WAND_W

IN1

ENO

EN

IN2

OUT

W#16#FFF

IW0 MW1

WOR_W

IN1

ENO

EN

IN2

OUTMW1

W#16#2000

MW2

I0.7

MW2

Network 2: If the timer is running, the Return instruction ends the processing here.

=

T1 RET

T1

TV

SE

??.?

&

&

&

Figure B-13 Function Block Diagram for Heating an Oven



C79000-G7076-C566-01


C-1Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

References

/30/ Getting Started: Working with STEP 7 V5.0

/70/ Manual: S7-300 Programmable Controller, Hardware and Installation

/71/ Reference Manual: S7-300, M7-300 Programmable ControllersModule Specifications

/72/ Instruction List: S7-300 Programmable Controller

/100/ Manual: S7-400/M7-400 Programmable Controllers,Hardware and Installation

/101/ Reference Manual: S7-400/M7-400 Programmable ControllersModule Specifications

/102/ Instruction List: S7-400 Programmable Controller

/231/ Manual: Configuring Hardware and Communication Connections, STEP 7 V5.0

/232/ Reference Manual: Statement List (STL) for S7-300 and S7-400Programming

/233/ Reference Manual: Ladder Logic (LAD)for S7-300and S7-400,Programming

/234/ Manual: Programming with STEP 7 V5.0

/235/ Reference Manual: System Software for S7-300 and S7-400System and Standard Functions

/250/ Manual: Structured Control Language (SCL) for S7-300/S7-400, Programming

/251/ Manual: S7-GRAPH for S7-300 and S7-400, Programming Sequential Control Systems

/252/ Manual: S7-HiGraph for S7-300 and S7-400, Programming State Graphs

/253/ Manual: C Programming for S7-300 and S7-400, Writing C Programs

/254/ Manual: Continuous Function Charts (CFC) for S7 and M7, Programming Continuous Function Charts

/270/ Manual: S7-PDIAG for S7-300 and S7-400“Configuring Process Diagnostics for LAD, STL, and FBD”

/271/ Manual: NETPRO, “Configuring Networks”

C

C-2Function Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01

/800/ DOCPROCreating Wiring Diagrams (CD only)

/801/ TeleService for S7, C7 and M7Remote Maintenance for Automation Systems (CD only)

/802/ PLC Simulation for S7-300 and S7-400 (CD only)

/803/ Reference Manual: Standard Software for S7-300 and S7-400,STEP 7 Standard Functions, Part 2

References

Glossary-1Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

Glossary

A

In absolute addressing, the memory location of the address to be processed isgiven.

Accumulators are registers in the CPU which act as intermediate buffers forload, transfer, comparison, math, and conversion operations.

Actual parameters replace the formal parameters when function blocks (FBs)and functions (FCs) are called.

Example: The formal parameter “Start” is replaced by the actual parameter“I3.6”.

An address is part of a STEP 7 statement and specifies what the processorshould execute the instruction on. Addresses can be absolute or symbolic.

An address identifier is the part of the address which contains various data.The data can include elements such as a value itself (data object) or the sizeof a value with which the instruction can, for example, perform a logicoperation. In the instruction statement “L IB10” IB is the address identifier(“I” indicates the memory input area and “B” indicates a byte in that area).

An array is a complex data type which consists of data elements of the sametype. These data elements can be elementary or complex.

B

The bit result is the link between bit and word-oriented processing. This is anefficient method to allow the binary interpretation of the result of a wordinstruction and to include it in a series of logic operations.

AbsoluteAddressing

Accumulator

Actual Parameter

Address

Address Identifier

Array

Bit Result (BR)

Glossary-2Function Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01

C

All blocks must be called first before they can be processed. The sequenceand nesting of these calls within an organized block is called the callhierarchy.

The CC 1 and CC 0 bits (condition codes) provide information on thefollowing results or bits:

� Result of a math operation

� Result of a comparison

� Result of a digital operation

� Bits that have been shifted out by a shift or rotate command

Characteristic of the Ladder Logic programming language. Current pathscontain contacts and coils. Complex elements (for example, math functions)can also be inserted into current paths in the form of “boxes.” Current pathsare connected to power rails.

D

Data blocks (DBs) are areas in a user program which store user data. Thereare shared data blocks which can be accessed by all logic blocks and thereare instance data blocks which are associated with a certain function block(FB) call. In contrast to all other blocks, data blocks do not containinstructions.

Static data are local data of a function block which are stored in the instancedata block and, therefore, remain intact until the function block is processedagain.

A data type defines how the value of a variable or a constant should be usedin the user program.

In SIMATIC STEP 7 two data types are available to the user (IEC 1131–3):

� Elementary data types

� Complex data types

Complex data types are created by the user with the data type declaration.They do not have their own name and cannot, therefore, be used again. Theycan either be arrays or structures. The data types STRING and DATE ANDTIME are classed as complex data types.

Call Hierarchy

Condition CodesCC 1 and CC 0

Current Path

Data Block (DB)

Data, Static

Data Type

Data Type,Complex

Glossary


Elementary data types are preset data types according to IEC 1131–3.

Examples:

� Data type “BOOL” defines a binary variable (“Bit”)

� Data type “INT” defines a 16-bit fixed-point variable.

The declaration section is used for the declaration of the local data of a logicblock when programming in the Text Editor.

In direct addressing, the address contains the memory location of a valuewhich is to be used by the instruction.

Example:

The location Q4.0 defines bit 0 in byte 4 of the process-image output table.

F

First check of the result of logic operation.

Directory of the user interface of the SIMATIC Manager which can beopened and can hold other directories or objects.

A formal parameter is a placeholder for the actual parameter in logic blocks.In function blocks (FBs) and functions (FCs) the formal parameters aredeclared by the user, in system function blocks (SFBs) and system functions(SFCs) they are already available. When a block is called, formal parametersare assigned actual parameters, so the called block works with the currentvalues.The formal parameters are classed as local data. They can be input, output, orin/out parameters.

According to the International Electrotechnical Commission’s IEC 1131–3standard, functions are logic blocks without a ‘memory’ (meaning they donot have static data). A function allows you to transfer parameters in the userprogram, which means they are suitable for programming frequentlyrecurring, complex functions, such as calculations. Important: As a functionhas no memory, you must continue processing the calculated values directlyafter the function has been called.

Data Type,Elementary

Declaration

Direct Addressing

First Check Bit

Folder

Formal Parameter

Function (FC)

Glossary


C79000-G7076-C566-01

According to the International Electrotechnical Commission’s IEC 1131–3standard, function blocks are logic blocks with a ‘memory’ (meaning theyhave static data). A function block allows you to transfer parameters in theuser program, which means they are suitable for programming frequentlyrecurring, complex functions, such as closed-loop control and operatingmode selection. As a function block has a memory (instance data block), youcan access its parameters (for example, outputs) at any time and at any pointin the user program.

Function Block Diagram (FBD) is one of the programming languages inSTEP 5 and STEP 7. FBD represents logic in the boxes familiar fromBoolean algebra. In addition, complex functions (for example, mathfunctions) can be represented in direct connection with the logic box.Programs created with FBD can also be translated into other programminglanguages (for example, Ladder Logic).

I

In immediate addressing, the address contains the value with which theinstruction works.

Example: L.27 means load constant 27 into accumulator.

When a block is input incrementally, each line or element is checkedimmediately for errors (for example, syntax errors). If an error is detected, itis marked and must be corrected before programming is completed.Incremental input is possible in STL (Statement List), LAD (Ladder Logic),and FBD (Function Block Diagram).

An “instance” is the call of a function block. An instance data block isassigned to each call.

An instance data block stores the formal parameters and the static data offunction blocks. An instance data block can be assigned to one functionblock call or a call hierarchy of function blocks.

An instruction is part of a STEP 7 statement; it specifies what the processorshould do.

Function Block(FB)

Function BlockDiagram (FBD)

ImmediateAddressing

Input, Incremental

Instance

Instance DataBlock (DB)

Instruction

Glossary


K

Keywords are used when programming with source files to identify the startand end of a block and to select sections in the declaration section of blocks,the start of block comments and the start of titles.

L

Ladder Logic is a graphic programming language in STEP 5 and STEP 7. Itsrepresentation is standardized in compliance with DIN 19239 (internationalstandard IEC 1131-1). Ladder Logic representation corresponds to therepresentation of relay ladder logic diagrams. In contrast to Statement List(STL), LAD has a restricted set of instructions.

Logic blocks are blocks within SIMATIC S7 that contain a part of theSTEP 7 user program. In contrast, data blocks (DBs) only contain data. Thereare the following types of logic blocks: organization blocks (OBs), functionblocks (FBs), functions (FCs), system function blocks (SFBs), and systemfunctions (SFCs). Blocks are stored in the “Blocks” folder under the “S7Program” folder.

A logic string is that portion of a user program which begins with an FC bitthat has a signal state of 0 and which ends when an instruction or event resetsthe FC bit to 0. When the CPU executes the first instruction in a logic string,the FC bit is set to 1. Certain instructions such as output instructions (forexample, Set, Reset, or Assign) reset the FC bit to 0. See First Check Bitabove.

M

The Master Control Relay (MCR) is an American relay ladder logic masterswitch for energizing and de-energizing power flow (current path). Ade-energized current path corresponds to an instruction sequence that writes azero value instead of the calculated value, or, to an instruction sequence thatleaves the existing memory value unchanged.

In SIMATIC S7 a CPU has three memory areas:

� Load memory

� Work memory

� System memory

Keyword

Ladder Logic(LAD)

Logic Block

Logic String

Master ControlRelay

Memory Area

Glossary


C79000-G7076-C566-01

Mnemonic representation is an abbreviated form for displaying the names ofaddresses and programming instructions in the program (for example, “I”stands for “input”). STEP 7 supports the international representation (basedon the English language), and the SIMATIC representation (based on theGerman abbreviations of the instruction set and the SIMATIC addressingconventions).

N

Networks subdivide LAD and FBD blocks into complete current paths andStatement List (STL) blocks into clear units.

O

The status bit OV stands for overflow. An overflow can occur, for example,after a math operation.

P

You can use a pointer to identify the address of a variable. A pointer containsan identifier instead of a value. If you allocate an actual parameter type, youprovide the memory address. With STEP 7 you can either enter the pointer inpointer format or simply as an identifier (for example, M 50.0). In thefollowing example, the pointer format is shown with which data from M 50.0is accessed:

P#M50.0

A project is a folder for all objects in an automation task, irrespective of thenumber of stations, modules, and how they are connected in networks.

R

Reference data are used to check your S7 program and include thecross-reference list, the assignment lists, the program structure, the list ofunused addresses, and the list of addresses without symbols.

MnemonicRepresentation

Network

Overflow Bit

Pointer

Project

Reference Data

Glossary


The result of logic operation (RLO) is the result of the logic string which isused to process other binary signals. The execution of certain instructionsdepends entirely on their preceding RLO.

S

A folder for blocks, source files, and charts for S7 programmable controllers.The S7 program also includes the symbol table.

A shared data block is a DB whose address is loaded in the DB addressregister when it is opened. It provides storage and data for all logic blocks(FCs, FBs, or OBs) that are being executed.

In contrast, an instance DB is designed to be used as specific storage and datafor the FB with which it has been associated.

A source file (text file) is part of a program created either with a graphic or atext-oriented editor and is compiled into an executable S7 user program orthe machine code for M7.

An S7 source file is stored in the “Sources” folder under the “S7 program”folder.

Statement List (STL) is a textual representation of the STEP 7 programminglanguage, similar to machine code. STL is the assembler language of STEP 5and STEP 7. If you program in STL, the individual statements represent theactual steps in which the CPU executes the program.

A station is a device which can be connected to one or more subnets; forexample, the programmable controller, programming device, and operatorstation.

The status bit stores the value of a bit that is referenced. The status of a bitinstruction that has read access to the memory (A, AN, O, ON, X, XN) isalways the same as the value of the bit that this instruction checks (the bit onwhich it performs its logic operation). The status of a bit instruction that haswrite access to the memory (S, R, =) is the same as the value of the bit towhich the instruction writes or, if no writing takes place, the same as thevalue of the bit that the instruction references. The status bit has nosignificance for bit instructions that do not access the memory. Suchinstructions set the status bit to 1 (STA=1). The status bit is not checked byan instruction. It is interpreted during program test (program status) only.

Result of LogicOperation (RLO)

S7 Program

Shared Data Block(DB)

Source File

Statement List(STL)

Station

Status Bit

Glossary


C79000-G7076-C566-01

The status word is part of the register of the CPU. It contains statusinformation and error information which is displayed when specific STEP 7commands are executed. The status bits can be read and written on by theuser, the error bits can only be read.

The status bit OS stands for “stored overflow bit of the status word”. Anoverflow can take place, for example, after a math operation.

A symbol is a name which can be defined by the user subject to syntaxguidelines. After it has been declared (for example, as a variable, data type,jump label, block etc) the symbol can be used for programming and foroperator interface functions. Example: Address: I 5.0, data type: BOOL,Symbol: momentary contact switch / emergency stop.

A table in which the symbols of addresses for shared data and blocks areallocated. Examples: Emergency Stop (symbol) -I 1.7 (address) orclosed-loop control (symbol) - SFB24 (block).

In symbolic addressing, the address being processed is designated with asymbol (as opposed to an absolute address).

A system function is a function (without a memory) that is integrated in theS7 operating system and can, if necessary, be called from the STEP 7 userprogram like a function (FC).

A system function block (SFB) is a function (with a memory) that isintegrated in the S7 operating system and can, if necessary, be called fromthe STEP 7 user program like a function block (FB).

U

User data types are special data structures which you can create yourself anduse in the entire user program after they have been defined. They can be usedlike elementary or complex data types in the variable declaration of logicblocks (FCs, FBs, OBs) or as a template for creating data blocks with thesame data structure.

The user program contains all the statements and declarations and all the datafor signal processing which can be used to control a device or a process. It ispart of a programmable module (CPU, FM) and can be structured withsmaller units (blocks).

Status Word

Stored OverflowBit

Symbol

Symbol Table

SymbolicAddressing

System Function(SFC)

System FunctionBlock (SFB)

User Data Types(UDTs)

User Program

Glossary


The user program structure describes the call hierarchy of the blocks withinan S7 program and provides an overview of the blocks used and theirdependency.

V

The variable declaration table is used for declaring the local data of a logicblock, when programming takes place in the Incremental Editor.

The variable table is used to collect together the variables that you want tomonitor and modify and set their relevant formats.

User ProgramStructure

VariableDeclaration Table

Variable Table(VAT)

Glossary


C79000-G7076-C566-01

Glossary

Index-1Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01

Index

Symbols(Word) AND Double Word (WAND_DW)

instruction, 11-4–11-5(Word) AND Word (WAND_W) instruction,

11-3–11-4(Word) Exclusive OR Double Word

(WXOR_DW) instruction, 11-8–11-9(Word) Exclusive OR Word (WXOR_W)

instruction, 11-7–11-8(Word) OR Double Word (WOR_DW)

instruction, 11-6–11-7(Word) OR Word (WOR_W) instruction,

11-5–11-6#. See Connector=. See Assign

AAbsolute addressing, practical application, B-4Accumulators

count value, 6-2description, 2-9function, 2-9

ACOS. See Arc CosineAdd Double Integer (ADD_DI), 7-3Add Integer (ADD_I), 7-2Add Real (ADD_R), 8-3ADD_DI. See Add Double IntegerADD_I. See Add IntegerADD_R. See Add RealAddress

box with address, 2-2box with address and value, 2-2description, 3-4element, 3-2label of a jump instruction, 14-2types, 3-4

Address identifier, 3-4Address Negative Edge Detection (NEG), 4-31Address Positive Edge Detection (POS), 4-30

Address types, 3-4Addressing

absolute, B-4definition, 3-2direct, 3-2immediate, 3-2symbolic, B-3

AND, 4-3truth table, 2-6

AND-before-OR, 4-5Arc Cosine (ACOS), 8-13–8-15Arc Sine (ASIN), 8-13–8-14Arc Tangent (ATAN), 8-13ASIN. See Arc SineAssign Value (MOVE), 10-2Assignment, 4-9ATAN. See Arc TangentAUF. See Open Data Block, SIMATIC

mnemonic

BBCD Conversion Error (BCDF), 10-3, 10-6BCD to Double Integer (BCD_DI), 10-6BCD to Integer (BCD_I), 10-3BCD_DI. See BCD to Double IntegerBCD_I. See BCD to IntegerBCDF. See BCD Conversion ErrorBeginning of a logic string, 2-10BIE. See Exception Bit Binary Result,

SIMATIC mnemonicBinary input

inserting, 4-7negating, 4-8

Binary Result bit (BR), status bit, 2-13Binary result bit (BR)

Exception Bit Binary Result (BR), 15-3Exception Bit Unordered (UO), 15-6save RLO to BR memory, 4-11

Bit logic, practical applications, B-3–B-6

Index-2Function Block Diagram (FBD) for S7-300 and S7-400

C79000-G7076-C566-01

Bit logic instructionAddress Negative Edge Detection (NEG),

4-31Address Positive Edge Detection (POS),

4-30assignment (=), 4-9connector, 4-10down counter (CD), 4-17Extended Pulse Timer (SE), 4-20insert binary input, 4-7negate binary input, 4-8Negative RLO Edge Detection (N), 4-29Off-Delay Timer (SF), 4-26On-Delay Timer (SD), 4-22Positive RLO Edge Detection, 4-28Pulse Timer (SP), 4-18Reset output (R), 4-13Reset_Set Flip Flop, 4-33Retentive On-Delay Timer (SS), 4-24save RLO to BR memory, 4-11set counter value (SC), 4-14set output (S), 4-12Set_Reset Flip Flop, 4-32up counter (CU), 4-16

Bit logic instructions, 4-2See also Status bit instructionspractical application, B-3–B-6

Bit logic operationAND, 4-3AND-before-OR, 4-5EXCLUSIVE OR logic operation, 4-6OR, 4-4OR-before-AND, 4-5

Bits of the status word, changing, 2-9Blocks

calling, 16-2–16-3exiting, 16-7

Boolean (BOOL), range, 3-3Boolean logic, 2-6–2-8Box, instruction as box, 2-2BR. See Exception Bit Binary Result,

international mnemonicByte, range, 3-3

CCALL. See Call FC/SFC without Parameters

Call FC/SFC without Parameters (CALL),16-2–16-3

Calling function blocksas a box, 16-4–16-6effects of a call on the status bits, 16-4supplying parameters, 16-6

Calling functionsas a box, 16-4–16-6effects of a call on the status bits, 16-4supplying parameters, 16-6with the Call FC/SFC without Parameters

instruction, 16-2Calling system function blocks

as a box, 16-4–16-6effects of the call on the status bits, 16-4supplying parameters, 16-6

Calling system functionseffects of the call on the status bits, 16-4supplying parameters, 16-6with the Call FC/SFC without Parameters

instruction, 16-2CC1 and CC0. See Condition code bits (CC1

and CC0)CD. See Down Counter, international mnemonicCEIL. See CeilingCeiling (CEIL), 10-16Character (CHAR), range, 3-3Checking the condition code bits (CC1 and

CC0), 2-11CMP_D. See Compare Double IntegerCMP_I. See Compare IntegerCMP_R. See Compare RealCompare Double Integer (CMP_D), 9-3Compare Integer (CMP_I), 9-2Compare Real (CMP_R), 9-4Comparing the result of math instruction with

zero, 15-4Comparison instructions

Compare Double Integer, 9-3Compare Integer, 9-2Compare Real, 9-4practical applications, B-11–B-12

Condition code bits (CC1 and CC0), 2-11and Exception Bit Unordered, 15-6effects of math instructions, 7-11, 8-7relative to the result bit, 15-4–15-5status bits, 2-11

Index


Conditional Jump (JMP), 14-4Connector, 4-10Conversion instructions

BCD to Integer (BCD_I), 10-3BCD to Integer (BDC_I), 10-3Ceiling (CEIL), 10-16Double Integer to BCD (DI_BCD), 10-7Double Integer to Real (DI_R), 10-8Floor (FLOOR), 10-17Integer to BCD (I_BCD), 10-4Integer to Double Integer (I_DI), 10-5Negate Real Number (NEG_R), 10-13Ones Complement Double Integer

(INV_DI), 10-10Ones Complement Integer (INV_I), 10-9Round to Double Integer (ROUND), 10-14Truncate Double Integer Part (TRUNC),

10-15Twos Complement Double Integer

(NEG_DI), 10-12Twos Complement Integer (NEG_I), 10-11

Count, up/down, 6-3Count value

format, 6-2range, 6-2

Counter, instructions with countersdown counter (CD), 4-17set counter value (SC), 4-14up counter (CU), 4-16

Countersaddress range, 2-4, 2-5count instructions, Up Counter/Down

Counter (S_CUD), 6-3count value


instructions used with counters, practicalapplications, B-11–B-12

memory area, 6-2supported counters, 6-2

Countingdown, 4-17, 6-7–6-8up, 4-16, 6-5–6-6

CPU register, 2-9count value in a counter, 6-2status word, 2-9time value in timer cell, 5-3

CPU registers, function, 2-9CU. See Up Counter, international mnemonic

DData block (DB)

instance, 16-6memory areas, 2-5

Data block instructions, Open Data Block(OPN), 13-2

Data types, 3-3Boolean (BOOL), 3-3BYTE, 3-3character (CHAR), 3-3date (D), 3-3double integer (DINT), 3-3double word (DWORD), 3-3integer (INT), 3-3REAL, 3-3S5 TIME, 3-3time (T), 3-3time of day (TOD), 3-3WORD, 3-3

DI_BCD. See Double Integer to BCDDI_R. See Double Integer to RealDIV_DI. See Divide Double IntegerDIV_I. See Divide IntegerDIV_R. See Divide RealDivide Double Integer (DIV_DI), 7-9Divide Integer (DIV_I), 7-8Divide Real (DIV_R), 8-6Double integer (DINT), range, 3-3Double Integer to BCD (DI_BCD), 10-7Double Integer to Real (DI_R), 10-8Double word, as data object, 3-5Double word (DWORD), range, 3-3Down counter (CD), 4-17Down Counter (S_CD), 6-7–6-8

EEdge detection, 4-28Element, instruction as, 2-2Element assignment (=), 4-9EN. See Enable input (EN)EN / ENO, meaning, 2-14Enable input (EN), parameters, 2-3Enable output (ENO)

See also BR bitparameters, 2-3

ENO. See Enable output (ENO)

Index


C79000-G7076-C566-01

Examples, practical application of instructions,B-2

Exception Bit Binary Result (BR), 15-3Exception Bit Overflow (OV), 15-7Exception Bit Overflow Stored (OS),

15-8–15-10Exception Bit Unordered (UO), 15-6

and floating-point math, 15-6Exclusive OR, truth table, 2-8Extended Pulse S5 Timer (S_PEXT), 5-7–5-8Extended Pulse Timer (SE), 4-20

FFBD, explanation, 1-1First Check (FC), 2-10–2-14

result, 2-10status bit, 2-10

Flip flop, 4-32Reset_Set, 4-33Set_Reset, 4-32

Floating-point mathand exception bit unordered (UO), 15-6Subtract Double Integer (SUB_DI), 7-5

Floating-point math instructionsAdd Real (ADD_R), 8-3Divide Real (DIV_R), 8-6Multiply Real (MUL_R), 8-5Subtract Real (SUB_R), 8-4

Floating-point numbersCompare Real, 9-4data type for. See Real number, data type

Floating-point math, 8-2Arc Cosine (ACOS), 8-13–8-15Arc Sine (ASIN), 8-13–8-14Arc Tangent (ATAN), 8-13effects on the bits of the status word, 8-7result within the valid range, 8-7

Floor (FLOOR), 10-17Format

count value, 6-2time value, 5-2

Function Block Diagram, 1-1Function blocks (FBs)

calling FBs as a box, 16-4–16-6supplying parameters, 16-6

Functions (FCs)calling FCs as a box, 16-4–16-6calling FCs with the Call FC/SFC without

Parameters instruction, 16-2supplying parameters, 16-6

GGerman SIMATIC names and SIMATIC

mnemonics, alphabetical list, A-10

II/O external inputs and outputs, address range,

2-4, 2-5I_BCD. See Integer to BCDI_DI. See Integer to Double Integer

Index


Inputinserting, 4-7negating, 4-8

Input parameter, as part of a box, 2-3Instance data block (DI), 16-6Instruction

as box with address, 2-2as box with address and value, 2-2as box with parameters, 2-3as element, 2-2

Instructionsalphabetical list, A-10–A-24

German SIMATIC names and SIMATICmnemonics, A-10

international names and internationalmnemonics, A-2

international names and SIMATICequivalents, A-6

SIMATIC names and internationalequivalents, A-14

SIMATIC names with SIMATICmnemonics and internationalmnemonics, A-17

bit logic instructions, 4-2practical application, B-3

comparison, practical applications,B-11–B-12

counter, practical applications, B-11–B-12dependent on Master Control Relay (MCR),

16-8evaluating the condition code bits (CC1 and

CC0), 7-11, 8-7evaluating the OS bit, 7-11, 8-7evaluating the OV bit, 7-11, 8-7floating-point math, 8-7

effects on the bits of the status word, 8-7result within the valid range, 8-7

integer math instructions, 7-11effects on the bits of the status word,

7-11valid range for results, 7-11

jump instructions, 14-2math instructions with integers, practical

applications, B-13practical application, B-2result bits, 15-4–15-5rotate instructions, 12-10–12-12shift instructions, 12-2–12-10status bit instructions, 15-2–15-10timer, practical applications, B-7–B-10word logic, practical applications,

B-14–B-15word logic instructions, practical

applications, B-14–B-16Integer (INT), range, 3-3

Index


C79000-G7076-C566-01

Integer math instructionsAdd Double Integer (ADD_DI), 7-3Add Integer (ADD_I), 7-2Divide Double Integer (DIV_DI), 7-9Divide Integer (DIV_I), 7-8effects on the bits of the status word, 7-11Multiply Double Integer (MUL_DI), 7-7Multiply Integer (MUL_I), 7-6Return Fraction Double Integer (MOD_DI),

7-10Subtract Integer (SUB_I), 7-4valid range for results, 7-11

Integer to BCD (I_BCD), 10-4Integer to Double Integer (I_DI), 10-5Integers, comparing, 9-2, 9-3International names and German SIMATIC

equivalents, alphabetical list, A-6International names with international

mnemonics, alphabetical list, A-2International names with SIMATIC mnemonics

and international mnemonics, alphabeticallist, A-17

INV_DI. See Ones Complement Double IntegerINV_I. See Ones Complement Integer

JJMP. See Conditional Jump; Unconditional

JumpJump instruction, jump label as address, 14-2Jump instructions, 14-2

conditional Jump (JMP), 14-4unconditional jump, 14-3

Jump label, as address of the jump instruction,14-2

LLanguages, switching between LAD, FBD, and

STL, 1-1Loading a count value


Loading a time valueformat, 5-2range, 3-3

Local data, memory area, address range, 2-4,2-5

MMaster Control Relay (MCR)

effects on the instructions Set Output (S) andReset Output (R), 16-8

important notes, 16-9Master Control Relay (MCR) instructions,

16-8–16-9Master Control Relay Activate (MCRA),

16-10Master Control Relay Deactivate (MCRD),

16-10Master Control Relay Off (MCR>), 16-13Master Control Relay On (MCR<),

16-13–16-16nesting, 16-14

Master Control Relay Activate (MCRA),16-10–16-16

Master Control Relay Deactivate (MCRD),16-10–16-16

Master Control Relay Off (MCR), 16-13–16-16Master Control Relay On (MCR<), 16-13–16-16Math instructions, practical applications with

integers, B-13MCR Functions, important notes, 16-9MCR<. See Master Control Relay OnMCR>. See Master Control Relay OffMCRA. See Master Control Relay ActivateMCRD. See Master Control Relay DeactivateMemory area, process input image, 2-4Memory areas, 2-3

bit memory, 2-4counters, 2-4data block, 2-4I/Os (external inputs and outputs), 2-4inputs and outputs, 2-4local data, 2-4process input image, 2-4process output image, 2-4timers, 2-4

MOD_DI. See Return Fraction Double IntegerMOVE. See Assign ValueMove instructions, Assign Value, 10-2MUL_DI. See Multiply Double IntegerMUL_I. See Multiply IntegerMUL_R. See Multiply RealMultiple instances, calling, 16-6Multiply Double Integer (MUL_DI), 7-7Multiply Integer (MUL_I), 7-6

Index


Multiply Real (MUL_R), 8-5

NN. See Negative RLO Edge DetectionNEG. See Address Negative Edge DetectionNEG_DI. See Twos Complement Double

IntegerNEG_I. See Twos Complement IntegerNEG_R. See Negate Real NumberNegate Real Number (NEG_R), 10-13Negative RLO Edge Detection (N), 4-29Nesting, Master Control Relay (MCR), 16-14

OOff-Delay S5 Timer (S_OFFDT), 5-13–5-14On-Delay S5 Timer (S_ODT), 5-9–5-10Ones Complement Double Integer (INV_DI),

10-10Ones Complement Integer (INV_I), 10-9Open Data Block (OPN), instruction, 13-2OPN. See Open Data Block, international

mnemonicOR, 4-4

truth table, 2-7OR status bit, 2-11OR-before-AND, 4-5OS. See Exception Bit Overflow StoredOS bit (stored overflow)

Exception Bit Overflow Stored (OS),15-8–15-10

status bit, 2-11Output parameter, as part of the structure of a

box, 2-3OV. See Exception Bit OverflowOV bit (overflow)

Exception Bit Overflow (OV), 15-7status bit, 2-11

Overflow (OV), effects of math instructions,7-11, 8-7

PP. See Positive RLO Edge DetectionParameter

Enable input (EN), 2-3Enable output (ENO), 2-3inputs and outputs as part of a box, 2-3

Pointer, 3-5POS. See Address Positive Edge DetectionPositive RLO edge detection (P), 4-28Process input image, memory area, 2-4

address range, 2-5Process output image, memory area, 2-4

address range, 2-5Program control instructions

Call FC/SFC without Parameters (CALL),16-2–16-3

Master Control Relay Activate (MCRA),16-10–16-12

Master Control Relay Deactivate (MCRD),16-10

Master Control Relay Off (MCR>),16-13–16-16

Master Control Relay On (MCR<),16-13–16-16

Return (RET), 16-7Programming, practical applications, B-2Pulse S5 Timer (S_PULSE), 5-5–5-6Pulse Timer (SP), 4-18

RR. See Reset outputReal number

data type, 3-3range, 3-3

Register, CPU, 2-9–2-14Reset output (R), 4-13Resolution. See Time base for S5 TIMEResult bits

checking the condition code bits (CC1 andCC0), 2-11

instructions, 15-4–15-5Result of logic operation, description, 2-6Result of logic operation (RLO)

status bit, 2-6status word bit, 2-10–2-11

RET. See Return instructionRetentive On-Delay Timer (S_ODTS),

5-11–5-12Retentive on-delay timer (SS), 4-24Return Fraction Double Integer (MOD_DI),

7-10Return instruction (RET), 16-7RLO. See Result of Logic OperationROL_DW. See Rotate Left Double WordROR_DW. See Rotate Right Double Word

Index


C79000-G7076-C566-01

Rotate instructions, 12-10–12-12Rotate Left Double Word (ROL_DW),

12-10–12-12Rotate Right Double Word (ROR_DW),

12-11–12-12Rotate Left Double Word (ROL_DW),

12-10–12-12Rotate Right Double Word (ROR_DW),

12-11–12-12ROUND. See Round to Double IntegerRound to Double Integer (ROUND), 10-14RS. See Reset_Set Flip Flop

SS. See Set outputS_AVERZ. See Off-Delay S5 Timer, SIMATIC

mnemonicS_CD. See Down Counter, international

mnemonicS_CU. See Up Counter, international mnemonicS_CUD. See Up Counter/Down Counter,

international mnemonicS_EVERZ. See On-Delay S5 Timer, SIMATIC

mnemonicS_IMPULS, 5-5S_ODT. See On-Delay S5 Timer, international

mnemonicS_ODTS. See Retentive On-Delay S5 Timer,

international mnemonicS_OFFDT. See Off-Delay S5 Timer,

international mnemonicS_PEXT. See Extended Pulse S5 Timer,

international mnemonicS_PULSE. See Pulse S5 Timer instructionS_SEVERZ. See Retentive On-Delay S5 Timer,

SIMATIC mnemonicS_VIMP. See Extended Pulse S5 Timer,

SIMATIC mnemonicS5 TIME

range, 3-3time base, 5-2time value, 5-2

SA. See Off-Delay Timer, SIMATIC mnemonicSAVE. See Save RLO to BR MemorySave RLO to BR memory (SAVE), 4-11

SC. See Set counter value, internationalmnemonic

SD. See On-Delay Timer, internationalmnemonic

SE. See Extended Pulse Timer, internationalmnemonic; On-Delay Timer, SIMATICmnemonic

Set counter value, 4-14Set counter value (SC), 4-14Set output (S), 4-12SF, 4-26Shift instructions, 12-2–12-9

Shift Left Double Word (SHL_DW),12-4–12-9

Shift Left Word (SHL_W), 12-2–12-9Shift Right Double Integer (SHR_DI), 12-9Shift Right Double Word (SHR_DW),

12-6–12-9Shift Right Integer (SHR_I), 12-7–12-9Shift Right Word (SHR_W), 12-5–12-9

Shift Left Double Word (SHL_DW), 12-4–12-9Shift Left Word (SHL_W), 12-2–12-9Shift Right Double Integer (SHR_DI), 12-9Shift Right Double Word (SHR_DW),

12-6–12-9Shift Right Integer (SHR_I), 12-7–12-9Shift Right Word (SHR_W), 12-5–12-9SHL_DW. See Shift Left Double WordSHL_W. See Shift Left WordSHR_DI. See Shift Right Double IntegerSHR_DW. See Shift Right Double WordSHR_I. See Shift Right IntegerSHR_W. See Shift Right WordSI. See Pulse Timer, SIMATIC mnemonicSIMATIC names and international equivalents,

alphabetical list, A-14SP. See Pulse Timer, international mnemonicSR. See Set_Reset Flip FlopSS. See Retentive On-Delay TimerSTA. See Status bitStatus bit (STA), 2-11

Index


Status bit instructions, 15-2Exception Bit Binary Result (BR), 15-3Exception Bit Overflow (OV), 15-7Exception Bit Overflow Stored (OS), 15-8Exception Bit Unordered (UO), 15-6result bits, 15-4–15-5

Status wordbinary result bit (BR bit), 15-3Binary Result bit (BR), 2-13bits affected by math instructions, 7-11, 8-7changing the bits, 2-9condition code bits (CC1 and CC0), 2-11

and Exception Bit Unordered (UO), 15-6relative to the result bit instructions,

15-4–15-5description, 2-9effects of calling an FB, FC, SFB or SFC on

the status bits, 16-4EN = 0, 2-14EN = 1, 2-14Exception Bit Overflow, 15-7Exception Bit Overflow Stored, 15-8–15-10First Check (FC), 2-10OR bit, 2-11OS bit (stored overflow), 2-11OV bit (overflow), 2-11result of logic operation (RLO) bit,

2-10–2-11specifying the invalid range for integer math

instructions, 7-11specifying the valid range for integer math

instructions, 7-11Status bit (STA), 2-11status bit instructions, 15-2–15-10structure, 2-9, 15-2

Stored overflow (OS), effects of mathinstructions, 7-11, 8-7

String of logic operationsdefinition, 2-10end, 2-10

SUB_DI. See Subtract Double IntegerSUB_I. See Subtract IntegerSUB_R. See Subtract RealSubtract Double Integer (SUB_DI), 7-5Subtract Integer (SUB_I), 7-4Subtract Real (SUB_R), 8-4SV. See Extended Pulse Timer, SIMATIC

mnemonicSymbolic addressing, practical example, B-3System function blocks (SFBs)

calling SFBs as a box, 16-4–16-6supplying parameters, 16-6

System functions (SFCs)calling SFCs as a box, 16-4–16-6supplying parameters, 16-6

SZ. See Set counter value, SIMATIC mnemonic

TTime base, resolution, 5-3Time base for S5 TIME, 5-2–5-14Time of day (TOD), range, 3-3Time resolution. See Time base for S5 TIMETime value, 5-3

format in timer cell, 5-3range, 5-3–5-14reading, 5-3syntax, 5-2

Timer, instructions with timersExtended Pulse Timer (SE), 4-20Off-Delay Timer (SF), 4-26On-Delay Timer (SD), 4-22Pulse Timer (SP), 4-18Retentive On-Delay Timer (SS), 4-24

Timersaddress range, 2-5components, 5-2–5-3Extended Pulse S5 Timer (S_PEXT),

5-7–5-8instructions used with timers, practical

applications, B-7–B-10memory area, 5-2numbers supported, 5-2overview, 5-4Pulse S5 Timer (S_PULSE), 5-5–5-6reading the time and the time base, 5-3time value, 5-2

range, 5-2–5-14syntax, 5-2

timer instructionsOff-Delay S5 Timer (S_OFFDT), 5-13On-Delay S5 Timer (S_ODT), 5-9Retentive On-Delay S5 Timer

(S_ODTS), 5-11TRUNC. See Truncate Double Integer PartTruncate Double Integer Part (TRUNC), 10-15Truth table

AND, 2-6exclusive OR, 2-8OR, 2-7

Twos Complement Double Integer (NEG_DI),10-12

Twos Complement Integer (NEG_I), 10-11

Index


C79000-G7076-C566-01

UUnconditional Jump (JMP), 14-3UO. See Exception Bit UnorderedUp Counter, (S_CU), 6-5–6-6Up counter, CU, 4-16Up Counter/Down Counter (S_CUD), 6-3

WWAND_DW. See (Word) AND Double Word

instructionWAND_W. See (Word) AND Word instructionWOR_DW. See (Word) OR Double Word

instructionWOR_W. See (Word) OR Word instructionWORD, range, 3-3Word, as data object, 3-5Word logic instructions

(Word) AND Double Word (WAND_DW),11-4–11-5

(Word) AND Word (WAND_W), 11-3–11-4(Word) Exclusive OR Double Word

(WXOR_DW), 11-8–11-9(Word) Exclusive OR Word (WXOR_W),

11-7–11-8(Word) OR Double Word (WOR_DW),

11-6–11-7(Word) OR Word (WOR_W), 11-5–11-6practical applications, B-14–B-16

WXOR_DW. See (Word) Exclusive OR DoubleWord instruction

WXOR_W. See (Word) Exclusive OR Wordinstruction

XXOR, 4-6

ZZ_RUECK. See Down Counter, SIMATIC

mnemonicZ_VORW. See Up Counter, SIMATIC

mnemonicZAEHLER. See Up Counter/Down Counter,

SIMATIC mnemonicZR. See Down Counter, SIMATIC mnemonicZV. See Up Counter, SIMATIC mnemonic

Index

Function Block Diagram (FBD) for S7-300 and S7-400C79000-G7076-C566-01 1�

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C79000-G7076-C566-01

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