Implementation of Corrected Code by Improving the Speed of Detection and Decoding Process

Presents by

S.Rajeswari

PG Scholar

M.E VLSI Design

Under Guidance of

Mr.R.Ponnangan

AP/ECE

AbstractDetection and decoding performs sequentiallySoft error detection(Logical Errors)The corrected code has been produced as an output

Existing SystemMajority Logic decoder Correction depends on parity check equationsInduced bit-flips to the Low-Density Parity Check codesAfter the Nth cycle the result has been produced

Proposed SystemMajority Logic detector/decoderDifferent set cyclic codesPart of Low-Density Parity Check codesThe Majority Logic Detection/Decoding process has been done in 3 cyclesControl unit manages the detection process

Flow Chart

LITERATURE SURVEYSl.no TITLE TECHNOLOGY ITERATION AREA SPEED CODE

CORRECTION

1 EFFICIENT MAJORITY LOGICAL FAULT DETECTION WITH DIFFERENCE SET CODES FOR MEMORY APPLICATIONS

MAJORITY LOGICAL FAULT DETECTION

NO NO NO YES

2 RADIATION INDUCED SOFT ERRORS IN ADVANCED SEMICONDUCTOR TECHNOLOGY

SOFT ERROR RATE NO YES YES YES

3 MODELS AND ALGORITHMIC LIMITS FOR AN ECC-BASED APPROACH TO HARDENING SUB-100-nm SRAMs

BIT ERROR RATE NO YES NO NO

4 DEC ECC DESIGN TO IMPROVE MEMORY RELIABILITY IN SUB-100nm TECHNOLOGIES

DOUBLE ERROR CORRECTION NO YES YES NO

5 DIFFERENCE-SET CYCLIC CODES MAJORITY LOGIC DECODER YES NO NO YES

6 IMPLEMENTATION OF CORRECTED CODE BY IMPROVING THE SPEED OF DETECTION AND DECODING PROCESS

MAJORITY LOGIC DETECTION AND DECODING

YES YES YES YES

Block Diagram

MEMORY

N CYCLE PROCESS

PLAIN ML DECODER

SYNDROME FAULT

DETECTOR

MAJORITY LOGIC

DETECTOR/DECODER

ENCODER

WORD

WORD

3 CYCLE PROCESS

ModulesError detection upto N cyclePlain ML decoderSyndrome fault detectorMajority logic detector/decoderDetection and decoding in 3 cycles

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Cont………Shih-Fu Liu, Pedro Reviriego,” Efficient Majority Logic Fault Detection With

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Thank you