2001 ITRS Front End Process

November 29, 2001

Santa Clara , CA

FEP Chapter Scope

• The scope of the FEP Chapter of the ITRS is to define comprehensive future requirements and identify potential solutions for the key technology areas in front-end-of-line IC wafer fabrication processing

FEP Chapter Topics

• Starting Substrate Materials• Surface Preparation• Critical Dimension Etch• MOSFET Isolation, Gate Stack, Doping, and

Contact Requirements– High Performance Logic

– Low Operating Power Logic (new 2001 addition)

– Low Standby Power Logic (new 2001 addition)

• DRAM Trench and Stack Capacitor materials and processes

• Pre-Metal dielectric layers (new)• FLASH memory materials and processes (new)• FeRAM materials and processes (new) • Non-classical double gate CMOS materials and

processes (new)

FEP Chapter Topics

1999 vs 2001 ITRS Technology Nodes1999 vs 2001 ITRS Technology Nodes

2001 2002 2003 2004 20051999 ITRS DRAM 1/2 Pitch (nm) 150 130 120 110 1002001 ITRS DRAM 1/2 Pitch (nm) 130 115 100 90 80

1999 ITRS MPU Physical Gate Length (nm) 100 88 80 70 652001 ITRS MPU Physical Gate Length (nm) 65 53 45 37 32

45 nm gate length was forecasted for year 2008 in 1999 ITRS

32 nm gate length was forecasted for year 2011 in 1999 ITRS

•There has been an unprecedented acceleration in MOSFET gate length scaling! In many instances, FEP processes have not kept pace, resulting in compromised device performance expectations. This is reflected in the 2001 FEP & PIDS requirements and difficult challenges

FEP Near Term Difficult Challenges

For the years up to and including 2007, with DRAM 1/2 Pitch 65nm, and MPU

physical gate length 25nm

Near Term Difficult Challenges

1 New gate stack processes and materials for continued planar MOSFET scaling• Remains the number one FEP priority

2 Critical Dimension and MOSFET effective channel length (Leff ) Control

3 CMOS integration of new memory materials and processes

4 Surfaces and Interfaces; structure, composition, and contamination control

5 Scaled MOSFET dopant introduction and control

Challenge #1 New Gate Stack Processes- Issues

• Extend oxynitride gate dielectric materials to ~0.8-1nm EOT for high-performance MOSFETS

• Introduce and integrate high- gate stack dielectric materials for low operating power MOSFETS

• Control boron penetration from doped polysilicon gate electrodes

• Minimize depletion of dual-doped polysilicon electrodes

• Possible introduction of dual metal gate electrodes with appropriate work function (toward end of period)

• Metrology issues associated with gate stack electrical and materials characterization

Gate Stack Challenges

Direct tunneling currents limit allowable gate oxide thickness reduction, thereby limiting gate capacitance and gate control over channel charge

Electrical depletion of doped polysilicon results in unwanted parasitic capacitance that limits gate control of channel charge, ultimately requiring metal gates

“red wall” for low power results from lower allowed tunneling curents

Year of Production 2001 2002 2003 2004 2005 2006 2007Technology Node (nm) (also equals DRAM 1/2 Pitch) 130 115 100 90 80 70 65MPU/ASIC High Performance Gate Length (nm) 65 53 45 37 32 28 25Low Power Gate Length (nm) 90 80 65 53 45 37 32Equivalent Physical Oxide Thickness, EOT, (nm) 1.3-1.6 1.2-1.5 1.1-1.5 0.9-1.4 0.8-1.3 0.7-1.2 0.6-1.1Low Operating Power EOT (NM) 2.0-2.4 1.8-2.2 1.6-2.0 1.4-1.8 1.2-1.6 1.1-1.5 1.0-1.4Low Standby Power EOT (NM) 2.4-2.8 2.2-2.6 2.0-2.4 1.8-2.2 1.6-2.0 1.4-1.8 1.2-1.6High Performance Allowable Gate Leakage (A/cm2) 15 57 156 270 938 2500 4000Low Strandby Power Allowable Gate Leakage (A/cm2) 0.0011 0.0013 0.0015 0.0019 0.0022 0.0027 0.0031Active Gate Polysilicon Doping for 25% Depletion Allowance (cm-3) 9.2 E19 9.2 E19 1.14 E20 1.5 E20 1.66 E20 1.66 E20 1.87 E20

“red wall” for high performance results from reliability and thickness control

For reference, 1997 ITRS High Performance allowable gate leakage was 1 A/cm2

Challenge #2 CD & Leff Control:Issues

• Control of gate etch processes to yield a physical gate length that is smaller than the printed feature size, while maintaining 10% 3- control of the combined lithography and etch processes

• Control of profile shape, line and space width for isolated, as well as closely-spaced fine line patterns

• Control of self-aligned doping introduction process and thermal activation budgets to yield ~ 20% 3- Leff control

• Maintenance of CD and profile control throughout the transition to new gate stack materials and processes

• Metrology

Resist Trim Process Sequence

Photoresist

Hardmask

Gate Poly

Gate Oxide

Substrate

Example150nm

Example100nm

TrimResist

OpenHardmask

EtchGate Poly

Gate Etch Requirements and Challenges

Year of Production 2001 2002 2003 2004 2005 2006 2007Technology Node (nm) (also equals DRAM 1/2 Pitch) 130 115 100 90 80 70 65MPU/ASIC High Performance Gate Length (nm) 65 53 45 37 32 28 25

Total Maximum Allowable Gate Length 3 (nm) 6.31 5.30 4.46 3.75 3.15 2.81 2.50Maximum Allowable Printed Gate Length 3 (nm) for reference 5.15 4.33 3.64 3.06 2.57 2.29 2.04Maximum Allowable Resist Trim 3 (nm) 2.10 1.77 1.49 1.25 1.05 0.94 0.83Maximum Allowable Gate Etch 3 (nm) 2.50 2.10 1.77 1.48 1.32 1.18 1.05Maximum CD Bias between dense and isolated lines <15% <15% <15% <15% <15% <15% <15%

•The lithographic, resist trim, and gate etch processes are all assumed to be statistically independent and therefore that the variances (2) are additive

•The variances include all random errors, point to point on a wafer, wafer to wafer and lot to lot, but do not include systematic errors

Challenge #3 CMOS Integration of New Memory Materials: Issues

• Development & Introduction of very high- DRAM capacitor dielectric layers

• Migration of DRAM capacitor structures from Silicon-Insulator-Metal to Metal-Insulator-Metal

• Integration and scaling of ferroelectric materials for FeRAM

• Scaling of Flash inter-poly and tunnel dielectric layers may require high-

• Limited temperature stability of high- and ferroelectric materials challenges CMOS integration

Technology Migration of Stack Capacitor

130nm 100nm 80nm 65nm

MIS MIM MIM MIM

TiN

Ta2O5

Poly Si

Metal

Barrier MetalBST

Perovskite

epi-BST

Selection from DRAM Stack Capacitor Roadmap

Year of First Product ShipmentTechnology Node

2001130 nm

2002 20032004

90 nm2005 2006

200765 nm

Minimum feature size (nm) 130 115 100 90 80 70 65 DRAM Product (A) 4GCell size factor a (B) 8. 0 8. 0 6.0 6.0 6.0 6.0 6. 0Cell size [um2] (C) 0. 14 0. 11 0. 06 0.049 0.038 0.029 0. 03

=0. 26*0. 52 =0. 23*0. 46 =0. 2*0. 3 =0.18*0.27 =0.16*0.24 =0.14*0.21 =0. 13*0. 2Storage Node size [um2] (D) 0. 051 0. 040 0. 020 0.016 0.013 0.010 0. 008

=0. 13*0. 39 =0. 115*0. 35 =0. 1*0. 2 =0.09*0.18 =0.08*0.16 =0.07*0.14 =0. 065*0. 13

CapacitorStructure

Cyl i nderMI S

Ta2O5

Cyl i nderMI S

Ta2O5

PedestalMI M

Ta2O5 (Ref. U)

PedestalMI M

Ta2O5 (Ref. U)

PedestalMI MBST

PedestalMI MBST

PedestalMI MBST

Dielectric Constant 22 22 50 Ref. U 50 Ref. U 250 300 450SN Height H [um] 0.9 0.9 0.9 0.9 0.65 0.53 0.38

Cylinder Factor (E) 1. 5 1. 5 1. 5 1. 5 1. 0 1. 0 1. 0Roughness Factor 1. 0 1. 0 1. 0 1. 0 1. 0 1. 0 1. 0

Total Capacitor Area [um2] 1. 48 1. 30 0. 87 0. 72 0. 32 0. 23 0. 16Structural Coefficient (F) 10. 9 12. 3 14. 5 14. 8 8. 5 7. 9 6. 2

teq@25fF [nm] (G) 2. 0 1. 80 1. 20 1. 00 0. 45 0. 32 0. 22t phy.@25fF [nm] (H) 5. 9 4. 5 15. 3 12. 8 28. 7 24. 7 25. 0

512M 1G 2G

Challenge #4 Surfaces & Interfaces: Issues

• Contamination, composition and structure control of channel/gate dielectric interface

• Contamination, composition and structure control of gate dielectric/gate electrode interface

• Interface control of DRAM capacitor structures

• Maintenance of surface and interface integrity through full-flow CMOS process

• Statistically significant characterization of surfaces having extremely low defect concentrations– Starting materials

– Pre-gate cleans

Pre-Gate Clean Requirements

Year of First Product ShipmentTechnology Node

2001 130nm 2002 2003 2004 90nm

2005 2006 2007 65nm

Driver

DRAM 1/2 Pitch (nm) 130 115 100 90 80 70 65 D ½MPU/ASIC Physical Gate Length (nm) 75 65 55 50 45 40 35 M

Challenge #5 Scaled MOSFET Doping: Issues

• Doping and activation processes to achieve source/drain parasitic resistance that is less than ~16-20% of ideal channel resistance (=Vdd/Ion)

• Control of parasitic capacitance to achieve less than ~19-27% of gate capacitance with acceptable Ion and short channel effect

• Achievement of activated doping concentration greater than solid solubility levels in dual doped polysilicon gate electrodes

• Formation of continuous self-aligned silicon contacts over shallow source/drain regions

• Metrology issues associated with 2-D doping profiling

Scaled MOSFET Parasitic Resistance Elements

Accumulation and Spreading resistances

Extension Sheet Resistivity

Contact Junction Sheet Resistivity

Contact Resistivity

Ideal MOSFET Contact Scaling

1/2 x in 4 years

Silicide contact 1/2 of contact region depth

Drain Extension Depth Scales with Gate Length

Contact Region Depth Scales more slowly than Gate Length, depending on efficacy of halo

Halo Implant manages SCE from deeper contact

Silicon/Silicide interfacial resistivity is crucial to low contact area resistance

PIDS Forecasted High Performance MOSFET Parasitic Elements

YEAR 2001 2002 2003 2004 2005 2006 2007MPU Physical Gate Length (nm) 65 53 45 37 32 28 25Parasitic Capacitance % of Gate Cap. 19% 23% 24% 25% 27% 28% 27%Parasitic Resistance % of Channel Res. 16% 16% 17% 18% 19% 19% 20%Delay (Cgate*Vdd/Id-NMOS) Picoseconds 1.63 1.34 1.16 0.99 0.96 0.79 0.66Note: Cgate includes parasitic capacitance

MOSFET Contact Requirements

Year of Production 2001 2002 2003 2004 2005 2006 2007Technology Node (nm) (also equals DRAM 1/2 Pitch) 130 115 100 90 80 70 65MPU/ASIC High Performance Gate Length (nm) 65 53 45 37 32 28 25

Parasitic Series Resistance from PIDS, PMOS/NMOS (ohm-um) 407/190 386/180 386/180 386/180 386/180 364/170 300/140Drain Extension Sheet Resistance, PMOS/NMOS (ohm/square) 400/190 460/220 550/260 660/310 770/360 830/390 760/360Drain Extension Junction Depth (nm) 36 29 25 20 18 15 14Drain Extension Lateral Abruptness (nm/decade) 7.2 5.8 5.0 4.1 3.5 3.1 2.8Contact Junction Depth (nm) 72 58 50 41 35 31 28Contact Silicide Thickness (nm) 36 29 25 20 18 15 14Silicide/Silicon Maximum Contact Resistivity (ohm-cm2) 3.1E-07 2.6E-07 2.3E-07 2.1E-07 1.8E-07 1.5E-07 1.1E-07

•The concomitant achievement of drain extension junction depth and sheet resistance poses a major doping challenge

•Contact silicide thickness must scale with contact junction depth, making the achievement of a continuous, thin silicide film increasingly difficult to achieve

•The contact area is assumed to scale with the ASIC half pitch, resulting in a progressively smaller source/drain contact area. As a consequence the maximum allowable silicide/silicon contact resistivity must be progressively lowered.

FEP Long Term Difficult Challenges

For the years beyond 2007, with DRAM 1/2 Pitch < 65nm, and MPU

physical gate length <25nm

Long Term FEP Challenges

1 Continued scaling of planar CMOS devices

2 Introduction and CMOS integration of non-standard double-gate MOSFET devices• These devices may be needed as early as 2007• Increased allocation of long term research resources would be

highly desireable

3 Starting material alternatives beyond 300mm

4 New memory storage cells, storage devices and memory architectures

5 Surfaces and Interfaces; structure, composition, and contamination control

Challenge #3 Starting Material Alternatives Beyond 300mm: Issues

• Future productivity enhancement needs dictate the requirement for a next generation, large substrate material

• Historical trends suggest that the new starting material have nominally 2X present generation area, e.g. 450mm

• Cost-effective scaling of the incumbent Czochralzki crystal pulling and wafer slicing process is questionable

• Research is required for a cost-effective substrate alternative

FeRAM RoadmapHere’s a newcomer…

November 2001 FEP & PIDS ITWG

S. Kawamura (FEP)

FeRAM has the following outstanding features:

*Non-volatility*Low voltage (power) operation*High speed*High endurance *High integration (Cell structure is similar to DRAM.)

Why FeRAM?

Year of First Product Shipment 2001 2002 2003 2004 2005 2006 2007 2010 2013

Technology Node 130nm 115nm 100nm 90nm 80nm 70nm 65nm 45nm 32nm

1) Feature Size (um): F 0.5 0.35 0.25 0.18 0.18 0.18 0.13 0.1 0.07

2) FeRAM Generation (Mass Production)

Standard Memory (bit) 1Mb 4Mb 16Mb 64Mb 64Mb 128Mb 256Mb 1Gb 4Gb

Embedded Memory (Byte) 32KB (256Kb)128KB (1Mb)

512KB (4Mb)

2MB (16Mb) 2MB (16Mb) 4MB (32Mb) 8MB (64Mb) 32MB (256Mb) 128MB (1Gb)

3) Access time (ns) 80 65 55 40 30 30 20 10 8

4) Cycle time (ns) 130 100 80 70 50 50 32 16 12

5) Cell Area Factor a 60 40 24 16 10 10 10 8 8

6) Cell size (um2) 15.000 4.900 1.500 0.518 0.324 0.324 0.169 0.080 0.039

7) Total cell area (mm2) for Standard Memory

15.73 20.55 25.17 34.79 21.74 43.49 45.37 85.90 168.36

8) Total cell area (mm2) for Embedded Memory

3.93 5.14 6.29 8.70 5.44 10.87 11.34 21.47 42.09

9) Projected Capacitor size (um2) 2.00 0.98 0.50 0.26 0.13 0.13 0.07 0.03 0.015

10) Capacitor area (um2) 2.00 0.98 0.50 0.26 0.13 0.13 0.09 0.08 0.06

11) Cap area/Proj Cap size 1.00 1.00 1.00 1.00 1.00 1.00 1.34 2.53 4.06

12) Height of Bottom Electrode/F (for 3D Capacitor)

n/a n/a n/a n/a n/a n/a 0.17 0.57 1.15

13) Capacitor Structure planar planar stack stack stack stack 3D 3D 3D

14) 2T2C or 1T1C 2T2C 1T1C 1T1C 1T1C 1T1C 1T1C 1T1C 1T1C 1T1C

15) Vop (Volt) 3.0 3.0 2.5 1.8 1.5 1.5 1.2 1.0 0.7

16) Minimum Switching Charge Density (uC/cm2) @Vop

4.4 7.1 11.2 17.2 34.5 34.5 40 40 40

17) Minimum Switching Charge per cell (fC/cell) @Vop

88.5 69.8 55.8 44.8 44.8 44.8 36.1 30.3 23.9

18) Retention @85C (Years) 10 Years 10 Years 10 Years 10 Years 10 Years 10 Years 10 Years 10 Years 10 Years

19) Endurance 1.0E+12 1.0E+13 1.0E+14 1.0E+15 >1.0E16 >1.0E16 >1.0E16 >1.0E16 >1.0E16

FeRAM (FRAM) Ferroelectric Materials Potential Solutions PZT:Pb(Zr, Ti)O3, SBT:SrBi2Ta2O9, BLT:(Bi, La)4Ti3O12

Ferroelectric Materials PZT, SBT PZT, SBT*, New Materials (BLT, etc.)

Deposition Methods PVD, CSD# PVD, CSD, MOCVD MOCVD, New Methods

*) SBT at present gives less than adequate switching charge for 2005 and beyond.

#) Chemical Solution Deposition

Assumptions (1)

Feature Size: 0.35m expected to be available in early 2002, 0.25m in 2003. x0.7 every 1-3 years.Memory Capacity: Intend to be aggressive to establish FeRAM market. x4 every 1-3 years.

Year of First Product Shipment 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016

Technology Node 130nm 115nm 100nm 90nm 80nm 70nm 65nm 45nm 32nm 22nm

1) Feature Size (um): F 0.5 0.35 0.25 0.18 0.18 0.18 0.13 0.1 0.07 0.05

2) FeRAM Generation (MassProduction)

Standard Memory (bit) 1Mb 4Mb 16Mb 64Mb 64Mb 128Mb 256Mb 1Gb 4Gb 16Gb

Assumptions (2)

Cell Size: planar stack (x 0.6) 2T2C 1T1C (x 0.6)

Switching Charge Qsw: Constant Vbitline=140mV for sensingQsw=Cbitline x Vbitline

(Stack)

PlateFerro. FilmStorage Node

(Planar)

Storage NodeFerro. FilmPlate

Evolution in Cell Structure

Planar Cell 3D CapacitorBit Line

Word LineCapacitor

Al, Polycide, W, etc.Ferroelectic FilmPt, IrO2, etc.

Metal

Bit Line (Polycide, W, etc.)

Bit Line(Polycide, W, etc.)

Al

(Polycide, W, etc.)

Stack Cell (COB)

Stack Cell (CUB) Bit Line

1.00E-01

1.00E+00

1.00E+01

1.00E+02

1.00E+03

1.00E+04

1.00E+05

1.00E+06

2000 2005 2010 2015 2020

DRAMFeRAM

FeRAM vs. DRAM

Year

Cap

acit

y (M

b)

Giga scale integration will be available with a 3D capacitor

Plate

Ferro. Film

Storage Node

1T1C

3D

Year 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016DRAM 512M 512M 1G 1G 2G 2G 4G 8G 32G 64GFeRAM 1M 4M 16M 64M 64M 128M 256M 1G 4G 16G

(bit)

Qsw and Capacitor Structure

FeRAM Requirements

Feature Size (um): F 0.5 0.35 0.25 0.22 0.2 0.18 0.13 0.1 0.07 0.05

F^2/3 0.630 0.497 0.397 0.364 0.342 0.319 0.257 0.215 0.170 0.136

a) F^2/3 (Normalized) 1@ 0.18um 1.98 1.56 1.24 1.14 1.07 1.00 0.80 0.68 0.53 0.43

b) cf. F^2/3 (Normalized, ITRS1999) 1.98 1.56 1.24 n/a n/a 1 0.79 0.62 0.49 0.39

c) Cbitline [fF], 320fF@0.18um 632.3 498.5 398.3 365.8 343.3 320.0 257.6 216.3 170.5 136.2

d) deltaVbitline [mV]: Constant 140.0 140.0 140.0 140.0 140.0 140.0 140.0 140.0 140.0 140.0

e) minimum Qsw [fC]: c)*d) 88.5 69.8 55.8 51.2 48.1 44.8 36.1 30.3 23.9 19.1

Cap Area [um2] @2Pr=20uC/cm2 0.443 0.349 0.279 0.256 0.240 0.224 0.180 0.151 0.119 0.095

Cap Area [um2] @2Pr=30uC/cm2 0.295 0.233 0.186 0.171 0.160 0.149 0.120 0.101 0.080 0.064

Cap Area [um2] @2Pr=40uC/cm2 0.221 0.174 0.139 0.128 0.120 0.112 0.090 0.076 0.060 0.048

Projected Capacitor Size[um2]3.00 0.98 0.50 0.39 0.32 0.13 0.07 0.03 0.015 0.0075

b) Values from ITRS 1999. Not used for calculation here.c) 320*a)d) Constant.e) Qsw=Cbitline*deltaVbitline. 3D Capacitor

Qsw/2Pr=Required Capacitor Area> Projected Capacitor Size3D.

N.B. Conventional structures can be used for 0.18um if we have Ferroelectric materials with 2Pr=34.5uC/cm2.

In order to enjoy (Lambs)

“The Silence of the (other) RAM’s,”

reliability comes first to be focused on,

followed by application and cost.

Issues (1)

Issues (2)

*) SBT at present gives less than adequate switching charge for 2005 and beyond.#) Chemical Solution Deposition

Ferroelectric materials:Should be stable under thermal budgets.Usually being used with some dopants.

PZT:Pb(Zr,Ti)O3, SBT:SrBi2Ta2O9, BLT:(Bi,La)4Ti3O12

Year of First Product Shipment 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016

Technology Node 130nm 115nm 100nm 90nm 80nm 70nm 65nm 45nm 32nm 22nm

1) Feature Size (um): F 0.5 0.35 0.25 0.18 0.18 0.18 0.13 0.1 0.07 0.05

2) FeRAM Generation (MassProduction)

Standard Memory (bit) 1Mb 4Mb 16Mb 64Mb 64Mb 128Mb 256Mb 1Gb 4Gb 16Gb

FeRAM (FRAM) Ferroelectric Materials Potential Solutions PZT:Pb(Zr, Ti)O3, SBT:SrBi2Ta2O9, BLT:(Bi, La)4Ti3O12

Ferroelectric Materials PZT, SBT PZT, SBT*, New Materials (BLT, etc.)

Deposition Methods PVD, CSD# PVD, CSD, MOCVD MOCVD, New Methods

Fatigue:More than 1E+15 is required to compete with SRAM and DRAM. Practical testing is critical.

Issues (3)

Year of First Product Shipment 2001 2002 2003 2004 2005 2006 2007 2010 2013

Technology Node 130nm 115nm 100nm 90nm 80nm 70nm 65nm 45nm 32nm

1) Feature Size (um): F 0.5 0.35 0.25 0.18 0.18 0.18 0.13 0.1 0.07

2) FeRAM Generation (Mass Production)

Standard Memory (bit) 1Mb 4Mb 16Mb 64Mb 64Mb 128Mb 256Mb 1Gb 4Gb

19) Endurance 1.0E+12 1.0E+13 1.0E+14 1.0E+15 >1.0E16 >1.0E16 >1.0E16 >1.0E16 >1.0E16

Application:Limited to small capacity (embedded) memory for RFID, Smart Card, etc.Some “killer applications” should be needed to establish FeRAM market.

Cost:Not competitive due to large cell size. 1T1C and 3D capacitor are mandatory to reduce cost.

Issues (4)