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©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter in the book includes: Objectives Study Guide 10.1 VHDL Description of Combinational Circuits 10.2 VHDL Models for Multiplexers 10.3 VHDL Modules 10.4 Signals and Constants 10.5 Arrays 10.6 VHDL Operators 10.7 Packages and Libraries 10.8 IEEE Standard Logic 10.9 Compilation and Simulation of VHDL Code Problems

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Page 1: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

FIGURES FOR

CHAPTER 10

INTRODUCTION TO VHDL

Click the mouse to move to the next page.Use the ESC key to exit this chapter.

This chapter in the book includes:ObjectivesStudy Guide

10.1 VHDL Description of Combinational Circuits10.2 VHDL Models for Multiplexers10.3 VHDL Modules10.4 Signals and Constants10.5 Arrays10.6 VHDL Operators10.7 Packages and Libraries10.8 IEEE Standard Logic10.9 Compilation and Simulation of VHDL Code

Problems

Page 2: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-1: Gate Circuit

Page 3: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-2: Inverter with Feedback

Page 4: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-3: Three Gates with a Common Input and Different Delays

Page 5: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-4: Array of AND Gates

Page 6: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-5: 2-to-1 Multiplexer

Page 7: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-6: Cascaded 2-to-1 MUXes

Page 8: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-7: 4-to-1 Multiplexer

Page 9: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-8: VHDL Module with Two Gates

Page 10: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-9: VHDL Program Structure

Page 11: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-10: Full Adder Module

architecture Equations of FullAdder isbegin -- concurrent assignment statements

Sum <= X xor Y xor Cin after 10 ns; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 10 ns;

end Equations ;

entity FullAdder isport (X,Y,Cin: in bit; --Inputs

Cout, Sum: out bit); --Outputsend FullAdder;

Page 12: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-11: 4-Bit Binary Adder

Page 13: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-12: Structural Descriptionof a 4-Bit Adder

Page 14: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Section 10.3, p. 271

Page 15: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/ColeFigure 10-13: VHDL Description of a ROM

1 entity ROM9_17 is2 port (A, B, C: in bit; F: out bit_vector(0 to 3));3 end entity; 4 architecture ROM of ROM9_17 is5 type ROM8X4 is array (0 to 7) of bit_vector(0 to 3);6 constant ROM1: ROM8X4 := ("1010", "1010",

"0111","0101", "1100", "0001", "1111", "0101");7 signal index: Integer range 0 to 7;8 begin9 Index <= vec2int(A&B&C); -- A&B&C Is a 3-bit vector10 -- vec2int is a function that converts this vector to an

integer11 F <= ROM1 (index);12 -- this statement reads the output from the ROM13 end ROM;

Page 16: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-14: Comparator for Integers

Page 17: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-15: NOR-NOR Circuit and Structural VHDL Code Using Library Components

Page 18: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-16: Tri-State Buffer

Page 19: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-17: Tri-State Buffers Driving a Bus

Page 20: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-18: Resolution Function for Two Signals

Page 21: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-19: VHDL Code for Binary Adder

Page 22: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-20: VHDL Code for Bi-Directional I/O Pin

entity IC_pin isport(IO_pin: inout std_logic);

end entity;architecture bi_dir of IC_pin is

component ICport(input: in std_logic; output: out std_logic);

end component;signal input, output, en: std_logic;

begin -- connections to bi-directional I/O pinIO_pin <= output when en = '1' else 'Z';input <= IO_pin;IC1: IC port map (input, output);

end bi_dir;

Page 23: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-21: Compilation, Simulation, and Synthesis of VHDL Code

Page 24: ©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter

©2004 Brooks/Cole

Figure 10-22: Simulation of VHDL Code


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