VHDL

Overview

ECOM 4311

Digital System Design

2

Outline

• VHDL Design Styles

• Test bench

3

Required reading

• P. Chu, RTL Hardware Design using VHDL

Chapter 2.2. BASIC VHDL CONCEPT

VIA AN EXAMPLE

VHDL Design Styles

5

VHDL Design Styles

Components and interconnects

structural

VHDL Design

Styles

dataflow

Concurrent statements

behavioral

(sequential)

• Registers

• State machines

• Decoders

Sequential statements

Subset most suitable for synthesis

• Testbenches

6

VHDL Design Styles

• Commonly used modeling styles in

hardware description are:

• Structural: Circuit is described as a

network of interconnected components

• Behavioral: Circuit is described as an i/o

relationship using sequential statements

inside a process

• Dataflow: Circuit is described using

concurrent statements

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Example: 3 input XOR

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Entity xor3_gate

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY xor3_gate IS

PORT(

A : IN STD_LOGIC;

B : IN STD_LOGIC;

C : IN STD_LOGIC;

Result : OUT STD_LOGIC

);

end xor3_gate;

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Dataflow Architecture (xor3_gate)

ARCHITECTURE dataflow OF xor3_gate IS

SIGNAL U1_OUT: STD_LOGIC;

BEGIN

U1_OUT <= A XOR B;

Result <= U1_OUT XOR C;

END dataflow;

U1_OUT

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Dataflow Description

• Describes how data moves through the system and the various processing steps.

• Dataflow uses series of concurrent statements to realize logic.

• Dataflow is most useful style when series of Boolean equations can represent a logic used to implement simple combinational logic

• Dataflow code also called “concurrent” code

• Concurrent statements are evaluated at the same time; thus, the order of these statements doesn’t matter

• This is not true for sequential/behavioral statements

This order…

U1_out <= A XOR B;

Result <= U1_out XOR C;

Is the same as this order…

Result <= U1_out XOR C;

U1_out <= A XOR B;

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Structural Architecture

• A formal VHDL structural description is

done using the concept of ’component’

• First declared (make known)

• Then instantiated (used)

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Structural Architecture ARCHITECTURE structural OF xor3_gate IS

SIGNAL U1_OUT: STD_LOGIC;

COMPONENT xor2 -- declaration for xor gate

PORT(

I1 : IN STD_LOGIC;

I2 : IN STD_LOGIC;

Y : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

-- instantiation of the 1st xor instance

U1: xor2 PORT MAP (I1 => A,

I2 => B,

Y => U1_OUT);

-- instantiation of the 1st xor instance

U2: xor2 PORT MAP (I1 => U1_OUT,

I2 => C,

Y => Result);

END structural;

A

B

C

Result xor3_gate

I1

I2 Y I1

I2 Y

U1_OUT

PORT NAME

LOCAL WIRE NAME

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xor2

• The definition of the actual components are ’decoupled’

and ’hidden’ from the architecture and can be defined

(and later changed) in a library

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY xor2 IS

PORT(

I1 : IN STD_LOGIC;

I2 : IN STD_LOGIC;

Y : OUT STD_LOGIC);

END xor2;

ARCHITECTURE dataflow OF xor2 IS

BEGIN

Y <= I1 xor I2;

END dataflow;

xor2.vhd

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Structural Description

• Structural design is the simplest to understand.

This style is the closest to schematic capture and

utilizes simple building blocks to compose logic

functions.

• Components are interconnected in a hierarchical

manner.

• Structural descriptions may connect simple gates

or complex, abstract components.

• Structural style is useful when expressing a

design that is naturally composed of sub-blocks.

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Structural Description

Even-parity Detector Example

• Consider the even-parity detector again

• Assume there is a library of predesigned

parts, xor2 and not1:

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Structural Description

Even-parity Detector Example

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Somewhere in library

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Behavioral Architecture

• Human reasoning and algorithms resemble

a sequential process

• VHDL provides language constructs that

resemble sequential semantics

• The process: a language construct to

encapsulate “sequential semantics”

• The entire process statement is a

concurrent statement

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• Syntax:

process (sensitivity_list)

variable declaration;

begin

sequential statements;

end process;

• The process has a sensitivity list, which is a set of signals

• When a signal in the sensitivity list changes, the process

is activated

• Inside the process, the semantics are similar to that of a

PL, e.g., variables can be used and execution of the

statements is sequential

Behavioral Architecture

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• Unlike signal assignment in a concurrent statement, the variable and

loop constructs do NOT have a direct hardware counterpart

Behavioral Architecture

Even-parity Detector Example

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Behavioral Description

• The process should be treated as one indivisible part,

whose behavior is specified by sequential statements

• The code describes the behavior of the component, not

the structure.

• Conceptual interpretation:

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A second example:

23 ECE 448 – FPGA and ASIC Design with VHDL

Testbenches

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Testbench

• a “virtual” experiment table • Circuit to be tested

• Input stimuli (e.g., function generator)

• Output monitor (e.g., logic analyzer)

• e.g.,

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Example: Even_Parity_Detector

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