chapter 12 counter circuits and vhdl state machines 1

Chapter 12Chapter 12

Counter Circuits and VHDL Counter Circuits and VHDL State MachinesState Machines

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ObjectivesObjectives

You should be able to:You should be able to: Use timing diagrams for the analysis of Use timing diagrams for the analysis of

sequential logic circuits.sequential logic circuits. Design any modulus ripple counter and Design any modulus ripple counter and

frequency divider using J-K flip-flops.frequency divider using J-K flip-flops. Describe the difference between ripple Describe the difference between ripple

counters and synchronous counters.counters and synchronous counters.

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ObjectivesObjectives

(Continued)(Continued) Solve various counter design Solve various counter design

applications using 4-bit counter ICs and applications using 4-bit counter ICs and external gating.external gating.

Connect seven-segment LEDs and BCD Connect seven-segment LEDs and BCD decoders to form multidigit numeric decoders to form multidigit numeric displays.displays.

Cascade counter ICs to provide for Cascade counter ICs to provide for higher counting and frequency higher counting and frequency divisions.divisions.

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Sequential Logic CircuitsSequential Logic Circuits

Sequential logic circuits Sequential logic circuits A mix of combinational logic gates and A mix of combinational logic gates and

flip-flopsflip-flops Used to count events and time the Used to count events and time the

duration of processesduration of processes Sequential since they follow a Sequential since they follow a

predetermined sequence and are predetermined sequence and are triggered by a timing pulse or clocktriggered by a timing pulse or clock

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Sequential Logic CircuitsSequential Logic Circuits

Normally count in binary and can stop Normally count in binary and can stop

or recycleor recycle

The modulus (MOD) of a counter is The modulus (MOD) of a counter is

defined by the number of binary statesdefined by the number of binary states

A 0 – 7 counter is a MOD-8 counterA 0 – 7 counter is a MOD-8 counter

Sequential Logic CircuitsSequential Logic Circuits Counter outputs are usually flip-flops Counter outputs are usually flip-flops

as they can hold a binary state.as they can hold a binary state.

A MOD-8 Counter Truth Table and A MOD-8 Counter Truth Table and WaveformsWaveforms

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Analysis of Sequential Analysis of Sequential CircuitsCircuits

Example 12-1: Input and output Example 12-1: Input and output waveforms from this edge-triggered D waveforms from this edge-triggered D flip-flop based circuit.flip-flop based circuit.

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Example 12-2: Input and output Example 12-2: Input and output waveforms from this edge-triggered D waveforms from this edge-triggered D flip-flop based circuit.flip-flop based circuit.

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Example 12-3: This circuit uses negative Example 12-3: This circuit uses negative edge-triggered JK flip-flops.edge-triggered JK flip-flops.

Note that the clock input from the second Note that the clock input from the second FF comes from QFF comes from Q00..

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Example 12-3: Input and output Example 12-3: Input and output waveforms.waveforms.

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Example 12-4: Input and output Example 12-4: Input and output waveforms.waveforms.

Ripple CountersRipple Counters

Flip-flops can be used to form binary Flip-flops can be used to form binary counterscounters

Cascade - Q output of one to clock input of Cascade - Q output of one to clock input of the nextthe next

Three flip-flops for a 3-bit counterThree flip-flops for a 3-bit counter 2233 = 8 different combinations = 8 different combinations Binary 000 through 111Binary 000 through 111 Modulus is 8Modulus is 8 MOD8 counterMOD8 counter

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Ripple CountersRipple Counters Three J-K flip-flops used toggle mode Three J-K flip-flops used toggle mode

to form a MOD-8 (3-bit) ripple to form a MOD-8 (3-bit) ripple countercounter

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Ripple CountersRipple Counters Asynchronous due to propagation Asynchronous due to propagation

delay.delay. 3-bit counter waveform3-bit counter waveform

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Ripple CountersRipple Counters 3-bit counter state diagram3-bit counter state diagram

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Propagation delay skews the Propagation delay skews the waveformwaveform

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Maximum frequency is Maximum frequency is approximately equal to the approximately equal to the reciprocal of the combined reciprocal of the combined propagation delayspropagation delays

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) to( flop-flipeach ofdelay n propagatio average

flops-flip ofnumber

1max

QCt

N

tNf

pp

p

Ripple CountersRipple Counters 16 bit counter and waveforms16 bit counter and waveforms

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VHDL Description of Mod-16 VHDL Description of Mod-16 Up-CounterUp-Counter

VHDL listing and block symbol fileVHDL listing and block symbol file

VHDL Description of Mod-16 VHDL Description of Mod-16 Up-CounterUp-Counter

Simulation of MOD-16 up-counterSimulation of MOD-16 up-counter

Design of Divide-by-N Design of Divide-by-N CountersCounters

Reduce the frequency of periodic Reduce the frequency of periodic waveformswaveforms

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Divide-by-5 (MOD5) CounterDivide-by-5 (MOD5) Counter

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Divide-by-5 (MOD5) waveforms and state Divide-by-5 (MOD5) waveforms and state diagramdiagram

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MOD-6 Up-Counter with a manual push MOD-6 Up-Counter with a manual push button resetbutton reset

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Ripple Counter Ripple Counter Integrated CircuitsIntegrated Circuits

7493 4-bit binary ripple counter logic 7493 4-bit binary ripple counter logic diagram and pin configuration diagram and pin configuration

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7493 connected as a MOD-16 ripple counter7493 connected as a MOD-16 ripple counter

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7493 can form any modulus counter 7493 can form any modulus counter less than or equal to MOD-16less than or equal to MOD-16

7490 4 bit ripple counter7490 4 bit ripple counter Divide by 2 and divide by 5 sectionsDivide by 2 and divide by 5 sections Cascade together to form divide by 10 Cascade together to form divide by 10

(decade or BCD)(decade or BCD) Commonly used in decimal display Commonly used in decimal display

applicationsapplications

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7492 4 bit ripple counter7492 4 bit ripple counter Divide by 2 and divide by 6 sectionsDivide by 2 and divide by 6 sections Cascade together to form divide by 12 Cascade together to form divide by 12

(MOD-12) (MOD-12) Commonly used in divide by 6 or divide Commonly used in divide by 6 or divide

by 12 applications such as digital by 12 applications such as digital clocksclocks

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Logic diagram and pin configuration Logic diagram and pin configuration for the 7490for the 7490

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Logic diagram and pin configuration Logic diagram and pin configuration for the 7492for the 7492

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System Design System Design ApplicationsApplications

LED illuminate for 1 s once every 13 sLED illuminate for 1 s once every 13 s See Application 12-1See Application 12-1

Turn on LED for 20 ms once every Turn on LED for 20 ms once every 100 ms100 ms See Application 12-2See Application 12-2

Three digit decimal counter 000 - 999Three digit decimal counter 000 - 999 See Application 12-3See Application 12-3

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Figure 12-33b

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System Design System Design ApplicationsApplications

Digital clock capable of hours, min Digital clock capable of hours, min and secand sec See Application 12-4See Application 12-4

Egg timer circuitEgg timer circuit See Application 12-5See Application 12-5

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Figure 12-36

Seven-Segment LED Seven-Segment LED Display DecodersDisplay Decoders

Common-anode LED requires Common-anode LED requires active-LOW outputsactive-LOW outputs

Common-cathode LED requires Common-cathode LED requires active-HIGH output - not as active-HIGH output - not as popularpopular

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Figure 12-37


Counters must output BCDCounters must output BCD Common-Anode LED DisplayCommon-Anode LED Display

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7447 BCD-to-Seven-Segment 7447 BCD-to-Seven-Segment Decoder/Driver ICsDecoder/Driver ICs 4-bit BCD input4-bit BCD input Seven active-LOW outputsSeven active-LOW outputs Lamp test inputLamp test input Ripple blanking input and outputRipple blanking input and output

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A 7447 7-segment display driverA 7447 7-segment display driver

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Driving a Multiplexed Display with a Driving a Multiplexed Display with a MicrocontrollerMicrocontroller 2 ports can drive up to 8 digits2 ports can drive up to 8 digits

1 port determines which digit is active1 port determines which digit is active 1 port drives the segments1 port drives the segments

More efficientMore efficient Assembly language usedAssembly language used Not all displays are on at onceNot all displays are on at once

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Figure 12-44

Synchronous CountersSynchronous Counters

All clock inputs tied to common All clock inputs tied to common clock lineclock line

4-bit synchronous counter4-bit synchronous counter MOD16 counter MOD16 counter 4 flip-flops4 flip-flops

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Figure 12-45

Synchronous Up/Down Synchronous Up/Down Counter ICsCounter ICs

74192 and 7419374192 and 74193 74192 - decade counter74192 - decade counter 74193 - binary counter74193 - binary counter

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74192 and 7419374192 and 74193 Two clock inputs (up and down)Two clock inputs (up and down) Terminal count outputs - when max is Terminal count outputs - when max is

reachedreached Function TableFunction Table

See Table 12-2 in your textSee Table 12-2 in your text

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74190 and 7419174190 and 74191 74190 - BCD counter74190 - BCD counter 74191 - 4-bit counter74191 - 4-bit counter

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74190 and 7419174190 and 74191 Parallel load - preset counterParallel load - preset counter U/D - select up or down countingU/D - select up or down counting Terminal count output when max Terminal count output when max

reachedreached Ripple clock output for cascadingRipple clock output for cascading

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74160/61/62/6374160/61/62/63 Two count enable inputsTwo count enable inputs Terminal count outputTerminal count output

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Applications of Applications of Synchronous Counter Synchronous Counter

ICsICs Count 0 to 9, 9 to 0 and 0 to 9Count 0 to 9, 9 to 0 and 0 to 9

See Application 12-7See Application 12-7 Divide-by-9 frequency divider using 74193Divide-by-9 frequency divider using 74193

See Application 12-8See Application 12-8 Divide-by-200 using synchronous countersDivide-by-200 using synchronous counters

See Application 12-9See Application 12-9 MOD-7 synchronous up-counter using MOD-7 synchronous up-counter using

7416374163 See Application 12-10See Application 12-10

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CPLD Design CPLD Design ApplicationsApplications

Used to simulate combinations of Used to simulate combinations of inputs and observe the resulting inputs and observe the resulting output to check for proper design output to check for proper design operation.operation.

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Figure 12-62

Implementing State Implementing State Machines in VHDLMachines in VHDL

Digital processes often follow a Digital processes often follow a predefined sequence of steps initiated by predefined sequence of steps initiated by clock pulses.clock pulses.

A state machine is a logic system that A state machine is a logic system that can be used to implement a sequence of can be used to implement a sequence of events to control the state of the output.events to control the state of the output.

Outputs of a state machine are triggered Outputs of a state machine are triggered by a clock and other input stimulusby a clock and other input stimulus

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VHDL implementation of a state machineVHDL implementation of a state machine Define the sequence of output statesDefine the sequence of output states Step through the states in a numerical order, Step through the states in a numerical order,

oror Step through the states in an order Step through the states in an order

determined by one or more control determined by one or more control inputsImplementing State Machines in VHDLinputsImplementing State Machines in VHDL

A gray code sequencer in VHDL and the A gray code sequencer in VHDL and the simulationsimulation See Figures 12-63 and 12-64See Figures 12-63 and 12-64

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Figure 12-63

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Figure 12-64


State machine design are commonly State machine design are commonly used in stepper motor controlused in stepper motor control Stepper motor operationStepper motor operation Present state and next statePresent state and next state Stepper motor state diagramStepper motor state diagram

See Figure 12-65See Figure 12-65 4 bit stepper motor sequencer and 4 bit stepper motor sequencer and

simulationsimulation See Figures 12-66 and 12-67See Figures 12-66 and 12-67

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Figure 12-65

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Figure 12-66

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Figure 12-67


State machines with multiple control State machines with multiple control inputsinputs Control (handshake) signals between Control (handshake) signals between

peripherals and the microprocessorperipherals and the microprocessor Read, write, ready to receive, ready to Read, write, ready to receive, ready to

transmit, buffer full, end of transmit, and transmit, buffer full, end of transmit, and parity errorparity error

8 bit Analog to digital converter (ADC) 8 bit Analog to digital converter (ADC) operationoperation

The ADC in VHDLThe ADC in VHDL

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SummarySummary

Toggle flip-flops can be cascaded end to Toggle flip-flops can be cascaded end to end to form ripple counters.end to form ripple counters.

Ripple counters cannot be used in high-Ripple counters cannot be used in high-speed circuits because of the problem speed circuits because of the problem they have with the accumulation of they have with the accumulation of propagation delay through all the flip-propagation delay through all the flip-flops.flops.

A down counter can be built by taking A down counter can be built by taking the outputs from the not-Q’s of a ripple the outputs from the not-Q’s of a ripple counter.counter.

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SummarySummary

Any modulus (or divide-by) counter Any modulus (or divide-by) counter can be formed by resetting the basic can be formed by resetting the basic ripple counter when a specific count ripple counter when a specific count is reached.is reached.

A glitch is a short-duration pulse A glitch is a short-duration pulse that may appear on some of the that may appear on some of the output bits of a counter.output bits of a counter.

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SummarySummary

Ripple counter ICs such as the 7490, Ripple counter ICs such as the 7490, 7492, and 7493 have four flip-flops 7492, and 7493 have four flip-flops integrated into a single package integrated into a single package providing four-bit counter providing four-bit counter operations.operations.

Four-bit counter ICs can be Four-bit counter ICs can be cascaded end to end to form cascaded end to end to form counters with higher than MOD16 counters with higher than MOD16 capability.capability.

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SummarySummary

Seven-segment LED displays choose Seven-segment LED displays choose between seven separate LEDs (plus between seven separate LEDs (plus a decimal point LED) to form the 10 a decimal point LED) to form the 10 decimal digits. They are constructed decimal digits. They are constructed with either the anodes or the with either the anodes or the cathodes connected to a common cathodes connected to a common pin.pin.

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SummarySummary

LED displays require a decoder/driver IC LED displays require a decoder/driver IC such as the 7447 to decode BCD data such as the 7447 to decode BCD data into a seven-bit code to activate the into a seven-bit code to activate the appropriate segments to illuminate the appropriate segments to illuminate the correct digit.correct digit.

Synchronous counters eliminate the Synchronous counters eliminate the problem of accumulated propagation problem of accumulated propagation delay associated with ripple counters by delay associated with ripple counters by driving all four flip-flops with a common driving all four flip-flops with a common clock.clock.

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SummarySummary

The 74192 and 74193 are 4-bit The 74192 and 74193 are 4-bit synchronous counter ICs. They have a synchronous counter ICs. They have a count-up/count-down feature and can count-up/count-down feature and can accept a 4-bit parallel load of binary accept a 4-bit parallel load of binary data.data.

The 74190 and 74191 synchronous The 74190 and 74191 synchronous counter ICs are similar to the counter ICs are similar to the 74192/74193 except they are better for 74192/74193 except they are better for constructing multistage counters of constructing multistage counters of more than 4 bits.more than 4 bits.

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SummarySummary

The 74160 series goes one step The 74160 series goes one step further and allows for truly further and allows for truly synchronous high-speed multistage synchronous high-speed multistage counting.counting.

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chapter 12 counter circuits and vhdl state machines 1

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