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Design VisionUser GuideVersion U-2003.03, March 2003

ii

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Document Order Number: 37175-000 PADesign Vision User Guide, vU-2003.03

Contents

What’s New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii

About This User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii

Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi

1. Introduction to Design Vision

Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Supported Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Design Vision and Other Synopsys Products . . . . . . . . . . . . . . . . . 1-7

2. Before You Start

The Design Vision Documentation Set . . . . . . . . . . . . . . . . . . . . . . 2-2

Design Compiler Tutorial Using Design Vision. . . . . . . . . . . . . . 2-2

iii

Design Vision User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Design Vision Online Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Setup Files for Design Vision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Starting and Exiting the Graphical User Interface . . . . . . . . . . . . . . 2-7

Exploring the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . 2-9

Changing the Appearance of Schematics . . . . . . . . . . . . . . . . . . . . 2-13

Using Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

3. Performing Basic Tasks

Specifying Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Reading In Your Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Setting the Current Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Defining the Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Setting Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Setting Design Rule Constraints . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Setting Optimization Constraints . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Saving the Design Database. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Working With Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Generating Reports for Selected Objects . . . . . . . . . . . . . . . . . 3-10

Printing Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

iv

4. Solving Timing Problems

Before You Analyze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Creating a Timing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Choosing a Strategy for Timing Closure . . . . . . . . . . . . . . . . . . . . . 4-4

Assessing the Relative Size of Your Timing Violations . . . . . . . 4-4

When Timing Violations Are Small. . . . . . . . . . . . . . . . . . . . . . . 4-5Working Globally to Fix Small Violations . . . . . . . . . . . . . . . 4-6Working Locally to Fix Small Violations . . . . . . . . . . . . . . . . 4-6

When Timing Violations Are Medium Size. . . . . . . . . . . . . . . . . 4-8

When Timing Violations Are Large . . . . . . . . . . . . . . . . . . . . . . 4-11

Index

v

Figures

Figure 2-1 The Design Vision Window. . . . . . . . . . . . . . . . . . . . . . . 2-9

Figure 4-1 Endpoint Slack Histogram. . . . . . . . . . . . . . . . . . . . . . . . 4-3

Figure 4-2 Design With Small Timing Violations . . . . . . . . . . . . . . . 4-5

Figure 4-3 Design With Medium Timing Violations . . . . . . . . . . . . . 4-9

Figure 4-4 Design With Large Timing Violations . . . . . . . . . . . . . . . 4-12

vii

Tables

Table 1-1 Supported File Formats . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Table 1-2 Design Vision Supported Platforms . . . . . . . . . . . . . . . . 1-6

Table 2-1 Commands for Scripting . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

ix

Preface FIX ME!

This preface includes the following sections:

• What’s New in This Release

• About This User Guide

• Customer Support

xi

What’s New in This Release

Information about new features, enhancements, and changes;known problems and limitations; and resolved Synopsys TechnicalAction Requests (STARs) is available in the Design Vision ReleaseNotes in SolvNet.

To see the Design Vision Release Notes,

1. Go to the Synopsys Web page at http://www.synopsys.com andclick SolvNet.

2. If prompted, enter your user name and password. (If you do nothave a Synopsys user name and password, follow theinstructions to register with SolvNet.)

3. Click Release Notes in the Main Navigation section, find theU-2003.03 Release Notes, then open the Design Vision ReleaseNotes.

About This User Guide

This section contains information about the target audience of thisdocument, where to find other pertinent publications, anddocumentation conventions used in this manual.

xii

Preface

Audience

This user guide is for logic design engineers who have someexperience using Design Compiler and who want to use thevisualization features of Design Vision for synthesis and analysis. Touse this user guide, you should be familiar with

• Synthesis using Design Compiler

• VHDL or Verilog HDL

• The UNIX operating system

Related Publications

For additional information about Design Vision, see

• Synopsys Online Documentation (SOLD), which is included withthe software for CD users or is available to download through theSynopsys Electronic Software Transfer (EST) system

• Documentation on the Web, which is available through SolvNetat http://solvnet.synopsys.com

• The Synopsys MediaDocs Shop, from which you can orderprinted copies of Synopsys documents, athttp://mediadocs.synopsys.com

You might also want to refer to the documentation for the followingrelated Synopsys products:

• Design Compiler

• DFT Compiler

• BSD Compiler

xiii


• Power Compiler

xiv

Preface

Conventions

The following conventions are used in Synopsys documentation.

Convention Description

Courier Indicates command syntax.

Courier italic Indicates a user-defined value in Synopsyssyntax, such as object_name. (A user-definedvalue that is not Synopsys syntax, such as auser-defined value in a Verilog or VHDLstatement, is indicated by regular text fontitalic.)

Courier bold Indicates user input—text you type verbatim—in Synopsys syntax and examples. (User inputthat is not Synopsys syntax, such as a username or password you enter in a GUI, isindicated by regular text font bold.)

[ ] Denotes optional parameters, such aspin1 [pin2 ... pinN]

| Indicates a choice among alternatives, such aslow | medium | high(This example indicates that you can enter oneof three possible values for an option:low, medium, or high.)

_ Connects terms that are read as a single termby the system, such asset_annotated_delay

Control-c Indicates a keyboard combination, such asholding down the Control key and pressing c.

\ Indicates a continuation of a command line.

/ Indicates levels of directory structure.

Edit > Copy Indicates a path to a menu command, such asopening the Edit menu and choosing Copy.

xv


Customer Support

Customer support is available through SolvNet online customersupport and through contacting the Synopsys Technical SupportCenter.

Accessing SolvNet

SolvNet includes an electronic knowledge base of technical articlesand answers to frequently asked questions about Synopsys tools.SolvNet also gives you access to a wide range of Synopsys onlineservices including software downloads, documentation on the Web,and “Enter a Call to the Support Center.”

To access SolvNet,

1. Go to the SolvNet Web page at http://solvnet.synopsys.com.

2. If prompted, enter your user name and password. (If you do nothave a Synopsys user name and password, follow theinstructions to register with SolvNet.)

If you need help using SolvNet, click SolvNet Help in the SupportResources section.

xvi

Preface

Contacting the Synopsys Technical Support Center

If you have problems, questions, or suggestions, you can contact theSynopsys Technical Support Center in the following ways:

• Open a call to your local support center from the Web by going tohttp://solvnet.synopsys.com (Synopsys user name andpassword required), then clicking “Enter a Call to the SupportCenter.”

• Send an e-mail message to [email protected].

• Telephone your local support center.

- Call (800) 245-8005 from within the continental United States.

- Call (650) 584-4200 from Canada.

- Find other local support center telephone numbers athttp://www.synopsys.com/support/support_ctr.

xvii

Customer Support

xviii

Preface

1Introduction to Design Vision 1

Design Vision is a graphical user interface (GUI) to the Synopsyssynthesis environment and an analysis tool for viewing andanalyzing your design at the generic technology (GTECH) level andthe gate level.

This chapter contains the following sections:

• Features and Benefits

• User Interfaces

• Methodology

• Supported Formats

• Licensing

• Supported Platforms

• Design Vision and Other Synopsys Products

1-1

Features and Benefits

Design Vision has these features:

• Window- and menu-driven interface to Synopsys synthesis(Design Compiler)

• Analysis visualization capabilities that include

- A logic hierarchy view for easy visualization and navigation ofyour design hierarchy (including viewing area attributes)

- Design schematic generation for examining high-level andlow-level design connectivity

- Histograms for visualizing trends in various metrics, forexample slack and capacitance

- Path schematic generation for visual examination of any pathsor selected logic you choose

• Command-line interface integrated in the GUI

• Scripting support for all Design Compiler shell (dcsh) commandsand Design Compiler tool command language (dctcl) commands

Using the features of Design Vision, you can

• Invoke Design Compiler synthesis and reporting

• Explore design structure

• Perform timing analysis for blocks you are synthesizing

• Visualize overall timing with Design Vision graphical analysis

• Perform detailed visual analysis of timing paths

1-2

Chapter 1: Introduction to Design Vision

• Insert scan cells and logic into a design, with or without testpoints

User Interfaces

Design Vision offers menus and dialog boxes for important DesignCompiler functions. Menus also offer visual analysis features andother design viewing features that are not Design Compilerfunctions.

Design Vision includes a command-line interface that providesaccess to all the capabilities of Synopsys synthesis tools.

The Design Vision GUI and command-line interface operate in bothTcl (dctcl) mode, the default, and dc_shell (dcsh) mode.

Methodology

Design Vision allows you to use the same design methodology andscripts you currently use and to extend your methodology withDesign Vision visual analysis.

Many of the Design Compiler functions are available through DesignVision menus. All Design Compiler functions are available throughthe Design Vision command-line interface.

1-3

User Interfaces

Supported Formats

With Design Vision you can access all the files supported by DesignCompiler. Table 1-1 shows the supported design file formats.

Table 1-1 Supported File Formats

Data Formats

Netlist EDIF

LSI Logic Corporation netlist format (LSI)

Mentor Intermediate Format (MIF)

Programmable logic array (PLA)

Synopsys equation

Synopsys state table

Synopsys database format (.db)

Tegas Design Language (TDL)

Verilog

VHDL

Xilinx Netlist Format (XNF)

Timing Standard Delay Format (SDF)

CommandScript

dcsh, Tcl

Cell Clustering Physical Design Exchange Format (PDEF)

Library Synopsys internal library format (.lib)

Synopsys database format (.db)

Parasitics dc_shell command scripts

1-4


Licensing

To use Design Vision, you need the Design-Vision license.

Synopsys licensing software and the documentation describing it arenow separate from the tools that use it. You install, configure, anduse a single copy of Synopsys Common Licensing (SCL) for allSynopsys tools. Because it provides a single, common licensingbase for all Synopsys tools, SCL reduces licensing administrationcomplexity, minimizing the effort you expend in installing,maintaining, and managing licensing software for Synopsys tools.

For complete Synopsys licensing information, see the followingdocuments:

• Licensing Quick Start

This booklet provides instructions on how to obtain an electroniccopy of your license key file and how to install and configure SCLon UNIX and Windows NT operating systems.

• Licensing Installation and Administration Guide

This guide provides detailed information on SCL installation andconfiguration, including examples of license key files andtroubleshooting guidelines.

1-5

Licensing

Supported Platforms

Design Vision runs on the platforms listed in Table 1-2.

All UNIX platforms support the default window manager supplied bythe manufacturer as well as Motif Window Manager v1.2.1 throughv1.2.5, and eXceed versions 6.2 and 7.0 native window managermultiple window mode. Design Vision does not support theschematic interface (SGE) to Mentor Graphics tools.

Note:OpenWindows is not a supported window manager for DesignVision. Sun Microsystems no longer supports or maintainsOpenWindows and recommends that you move to the CDEWindows environment.

Table 1-2 Design Vision Supported Platforms

Platform Operating system Default window manager

HP9000 HP-UX 11.0, 11.11 (11i) CDE

IBM RS/6000 AIX 4.3.31

1. Not available on CD, but will be available for download by EST at a later date. For availability, checkwith your Synopsys sales representative.

CDE

Sun SPARC Solaris 8 CDE

Intel IA-32 Red Hat Linux 7.22

2. Runs only in 32-bit mode; limited to 4 GB memory space.

GNOME

1-6


Your hardware and operating system vendor has required patchesavailable for your system. For more information about the supportedplatforms and the operating system patches necessary to runSynopsys software on supported platforms, go to

http://www.synopsys.com/products/sw_platform.html

From this Web page you can navigate to the Supported PlatformsGuide for your release.

Design Vision and Other Synopsys Products

As a visual analysis tool and GUI for Synopsys synthesis, DesignVision works with Design Compiler to synthesize and analyze yourdesign.

The Design Vision and Synopsys PrimeTime tools have similartiming visualization features; however, the tools have different timingengines and differ in their application to analysis. Design Vision hasthe same static timing engine as Design Compiler. Use DesignVision to perform timing analysis and modification of blocks you aresynthesizing. Use PrimeTime for static timing sign-off or foranalyzing the timing of a chip or of large portions of a chip.

1-7

Design Vision and Other Synopsys Products

1-8


2Before You Start 2

This chapter contains general and specific information you need toknow before you use Design Vision for the first time. In this chapteryou can find the following sections:

• The Design Vision Documentation Set

• Setup Files for Design Vision

• Starting and Exiting the Graphical User Interface

• Exploring the Graphical User Interface

• Changing the Appearance of Schematics

• Using Scripts

2-1

The Design Vision Documentation Set

You can find most of what you need to know to run Design Vision inthe Design Vision documentation set.

The Design Vision documentation set is divided into these parts:

• Design Compiler Tutorial Using Design Vision

• Design Vision User Guide

• Design Vision online Help

Other sources of information include man pages, the SolvNetknowledge base, and the Customer Support Center. For informationabout accessing these sources of information, see “CustomerSupport” on page xvi.

Design Compiler Tutorial Using Design Vision

The Design Compiler Tutorial Using Design Vision is an introductionto ASIC design using Synopsys Design Compiler and Design Vision.

The tutorial is a group of guided exercises in which you use DesignCompiler to synthesize and analyze a simple design. The tutorialintroduces Design Vision as the GUI for synthesis and providessome post-synthesis analysis that takes advantage of the DesignVision visual representation of analysis results.

Use the Design Compiler Tutorial Using Design Vision if you are newto Design Compiler. However, even if you are an experienced DesignCompiler user, the tutorial is a useful introduction to the features ofDesign Vision.

2-2

Chapter 2: Before You Start

In the tutorial, you can read about and perform exercises for basicsynthesis and analysis. For example, you

• Read a design from disk into the tool’s workspace

• Define design constraints to direct synthesis results

• Compile the design to gates

• View analysis results

• Modify the design

• Resynthesize the design

• Reanalyze the design

Design Vision User Guide

The Design Vision User Guide assumes you are familiar with basicDesign Compiler concepts.

The user guide provides guidance in solving particular problems. Forexample, it presents short procedures that use the analysisvisualization features of Design Vision to locate and solve timingproblems.

Sometimes steps in a procedure refer to actions without furtherexplanation: for example, “Create a histogram” or “Create a pathschematic.” Such steps refer to features of Design Vision that areexplained in the Design Vision online Help.

The Design Vision User Guide does not contain specific informationabout individual menu items or dialog boxes. For such information,see the Design Vision online Help.

2-3

The Design Vision Documentation Set

In Chapter 3, “Performing Basic Tasks,” experienced DesignCompiler users can learn how to do certain familiar synthesis tasksusing Design Vision. However, the user guide explains such topicsonly briefly.

Design Vision Online Help

The Design Vision online Help is integrated in the Design Vision GUI.You access the Help system from the Help menu in the main DesignVision window.

Design Vision online Help explains the details of features andprocedures. For example, if you need help performing a step in aprocedure presented in the user guide, you can find the informationyou need in the online Help system.

Information in online Help is grouped in the following categories:

• Feature topics

Provide overviews of Design Vision window components andtools.

• How to topics

Provide procedures for accomplishing general synthesis andanalysis tasks.

• Reference topics

Provide explanations for views, toolbar buttons, menucommands, and dialog box options.

2-4


To access the Design Vision online Help system,

• Choose Help > Online Help.

Design Vision online Help is a browser-based HTML Help system.For optimal viewing, you should use Netscape Navigator version4.78. Design Vision Help is not supported in Netscape version 6 orlater.

The online Help system makes extensive use of Java, JavaScript,and style sheets. To configure your browser for viewing online Help,make sure the advanced preferences are set as follows:

• Enable Java, JavaScript, and style sheets

• Disable Java plug-ins

If you reset preferences while the Help system is open, click theReload button on the browser's navigation toolbar after you reset thepreferences.

Setup Files for Design Vision

When you start Design Vision, it executes the standard Synopsyssetup file, .synopsys_dc.setup, and the GUI setup file, .dv_setup.tcl.Design Vision also executes the GUI setup file when you open orreopen the GUI from the Design Vision shell. These setup files havethe same names in each of their three locations: the installation,home, and design directories.

2-5

Setup Files for Design Vision

The files contain commands that initialize parameters and variables,declare design libraries, and so forth. Besides defining settings forsynthesis, these files can

• Change the default appearance of Design Vision schematics

• Define scripts that you can run by using the source command(for dctcl scripts) or the include command (for dcsh scripts)

These topics are covered in detail in “Exploring the Graphical UserInterface” on page 2-9 and “Using Scripts” on page 2-14respectively.

For more information about the locations of setup files andinitialization settings for synthesis, see the Design Compiler UserGuide.

2-6


Starting and Exiting the Graphical User Interface

You can invoke the Design Vision GUI in either of the two dc_shellmodes:

• dctcl mode

This is the default.

• dcsh mode

You must start in this mode to use dcsh scripts.

To start Design Vision in dctcl mode,

• At the UNIX shell prompt, enter

% design_vision

To start Design Vision in dcsh mode,


% design_vision -dcsh_mode

You cannot switch from mode to mode in the same session. Tooperate in either mode, Design Vision must start up and initialize inthat mode. For example, to change from the default dctcl mode todcsh mode, exit Design Vision and start Design Vision in dcsh mode.

When you start Design Vision, the Design Vision window appears bydefault. In addition, the design_vision-t prompt (in dctcl mode) or thedesign_vision prompt (in dcsh mode) appears in the shell where youstarted Design Vision.

2-7

Starting and Exiting the Graphical User Interface

You can close and reopen the Design Vision GUI without exiting theDesign Vision shell. In addition, you can start the Design Vision shellwithout opening the GUI.

To close the GUI without exiting Design Vision,

• Choose File > Close.

Or you can enter gui_stop on the command line.

To open or reopen the GUI from the Design Vision shell,

• Enter the following on the design_vision-t (or design_vision)command line.

design_vision-t> gui_start

To start Design Vision in dctcl mode without opening the GUI,


% design_vision -no_gui

To start Design Vision in dcsh mode without opening the GUI,


% design_vision -dcsh_mode -no_gui

To set Design Vision to start without the GUI by default,

• Set the following variable in your .synopsys_dc.setup file:

set gui_auto_start 0

To exit Design Vision,

• Choose File > Exit.

2-8


Exploring the Graphical User Interface

Design Vision has the look and feel of the Microsoft Windows GUI.Figure 2-1 shows the window you see when you start Design Vision,read in a design, and a design schematic for the top-level design.

Figure 2-1 The Design Vision Window

Menus Toolbars Schematic view

Tabs ConsoleCommand lineStatus bar

Logic hierarchy view

2-9


The window consists of a title bar, a menu bar, and several toolbarsat the top of the window and a status bar at the bottom of the window.You use the workspace between the toolbars and the status bar todisplay view windows containing graphical and textual designinformation. When you start a Design Vision session, the followingview windows appear in the workspace:

• Logic hierarchy View

The logic hierarchy view helps you navigate your design andgather information. The view is divided into the following twopanes:

- Instance tree

- Objects list

The instance tree lets you quickly navigate the design hierarchyand see the relationships among its levels. If you select theinstance name of a hierarchical cell (an instance that containssubblocks), information about that instance appears in the objecttable. You can Shift-click or Control-click instance names toselect combinations of instances.

By default, the object table displays information abouthierarchical cells belonging to the selected instance in theinstance tree. To display information about other types of objects,select the object types in the list above the table. You can displayinformation about hierarchical cells, all cells, pins and ports, pinsof child cells, and nets.

If some of the text in a column is missing because the column istoo narrow, you can hold the pointer over it to display theinformation in an InfoTip. You can also adjust the width of acolumn by dragging its right edge left or right.

2-10


• Console

The console provides a command-line interface and displaysinformation about the commands you use during the session inthe following three views:

- Log view

- History view

- Errors and warnings view

You can enter dc_shell commands on the command line at thebottom of the console. Enter these commands just as you wouldenter them at the dc_shell prompt in a standard UNIX or Linuxshell. Design Vision echoes the dc_shell command output(including processing messages and any warnings or errormessages) in the console log view.

The log view provides the session transcript. The history viewprovides a list of the commands that you have used during thesession. The errors and warnings view displays error andwarning messages.

To select a view, click the tab at the bottom of the console. Thelog view is displayed by default when you start Design Vision. Formore details about the console, see the “Using dc_shellCommands” topic in online Help.

In addition to the logic hierarchy view and the console, you candisplay design information in the following views:

• Schematic views (design schematics, path schematics, andsymbol views)

• Histogram views (endpoint slack, path slack, net capacitance,and user-defined)

2-11


• Report view

• List views (cells, ports, pins, nets, and designs)

Design Vision displays a tab in the workspace for each undockedview you open.

You can adjust the sizes of view windows for viewing purposes, andyou can move them to different locations within the Design Visionwindow. When you click anywhere within a view window, DesignVision highlights its title bar to indicate that it has the focus (that is, itis the active view) and can receive keyboard and mouse input. Formore details, see the “Design Vision Window” topic in online Help.

To learn more about the functions of menu commands and toolbarbuttons, see the “Menu Bar” and “Toolbars” topics in online Help.

The status bar, at the bottom of the window, displays currentinformation about the session, such as the number and type ofselected objects. If you hold the pointer over a menu command, atoolbar button, or a tab in the workspace, the status bar displays abrief message about the action that the command, button, or tabperforms. To quickly display the list of selected objects in theSelection List dialog box, you can click the button at the right end ofthe status bar.

You can open additional Design Vision windows and use them tocompare views, or different design information within a view, side byside. All open Design Vision windows share the same designs inmemory and the same current timing information. However, you canconfigure the views independently for each window. To learn more,see the “Opening New Design Vision Windows” topic in online Help.

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Changing the Appearance of Schematics

For display purposes only, when Design Vision generates aschematic, it applies the same display characteristics (color, fillpattern, line width, line style, text color, and font) to all the objects ofa given object type: cell, port, pin, net, bus, bus ripper, or hierarchycrossing. This convention allows you to define how similar objectsare displayed in a schematic or whether they appear at all.

You can change schematic settings in either of the following ways:

• Choose View > Preferences to open the Application Preferencesdialog box, select the Schematic Settings category, set thedesired options, and click OK.

• Edit the .synopsys_dv_prefs.tcl file and run it as a Tcl script.

2-13

Changing the Appearance of Schematics

Using Scripts

Designers often use scripts to accomplish routine repetitive taskssuch as setting constraints or defining other design attributes.Because Design Vision can run in either dctcl mode or dcsh mode,you can use your existing scripts in Design Vision.

To run dctcl scripts, start Design Vision in dctcl mode. To run dcshscripts, start Design Vision in dcsh mode. For information aboutstarting Design Vision in either mode, see “Starting and Exiting theGraphical User Interface” on page 2-7.

To run scripts in Design Vision,

• Choose File > Execute Scripts.

The Execute File dialog box opens. Use the dialog box tonavigate to the appropriate directory and run your script.

Alternatively, you can run scripts from the design_vision-t commandline by using the source command in dctcl mode or from thedesign_vision command line by using the include command indcsh mode.

To learn more about adding scripts to the Tools menu, see the “UsingScripts” topic in online Help.

2-14


Table 2-1 is a short list of some commands that are useful when youare writing scripts for use with Design Vision.

For detailed descriptions of commands and options, see the manpage for each command.

Table 2-1 Commands for Scripting

Command Mode Description

get_selection dctcl Returns a collection that iscurrently selected in the GUI

change_selection dctcl Changes the selection in theGUI to the collection passed to itas a parameter

2-15

Using Scripts

2-16


3Performing Basic Tasks 3

This chapter describes how to perform basic presynthesis andsynthesis tasks using Design Vision menus. This chapter is useful forexperienced users of Design Compiler who need to accomplishfamiliar basic tasks in Design Compiler using Design Vision windowsand menus.

If you are new to Synopsys synthesis tools, see the Design CompilerTutorial Using Design Vision to learn about basic tasks by performingthem on a simple design.


• Specifying Libraries

• Reading In Your Design

• Setting the Current Design

• Defining the Design Environment

3-1

• Setting Design Constraints

• Compiling the Design

• Saving the Design Database

• Working With Reports

• Printing Schematics

3-2

Chapter 3: Performing Basic Tasks

Specifying Libraries

Before you start work on a design, specify the location of yourlibraries. You can define your library locations directly in the.synopsys_dc.setup file or indirectly by entering the locations in theApplication Setup dialog box. Either method is acceptable—theyboth accomplish the same thing.

The link and target libraries are technology libraries that define thesemiconductor vendor’s set of cells and related information, such ascell names, cell pin names, delay arcs, pin loading, design rules, andoperating conditions.

The symbol library defines the symbols for schematic viewing of thedesign.

You must specify any additional, specially licensed, DesignWarelibraries with the synthetic_library variable (you do not need tospecify the standard DesignWare library).

To define libraries in the .synopsys_dc.setup file, see the DesignCompiler User Guide.

To specify the library location in the Application Setup dialog box,

1. Select File > Setup.

The Application Setup dialog box opens.

2. Select the Defaults category if the Defaults page is not displayed.

3. Enter the library file names for link library, target library, andsymbol library.

4. Make sure you enter the appropriate path in the Search Path box.

3-3

Specifying Libraries

5. Click OK.

For more information about the options on the Defaults page, see the“Setting Library Locations” topic in the online Help. For informationabout the options on the Variables page, see the “Setting Variables”topic.

To understand more about the function of link libraries, targetlibraries, and symbol libraries, see the Design Compiler User Guide.

Reading In Your Design

To begin working on your design, read the design from disk into thetool’s active memory. This is where all changes in the design takeplace before you save the design by writing it back to disk.

The File menu contains the commands for reading in a design:

• Analyze and Elaborate

Use Analyze and Elaborate to read HDL designs and convertthem to Synopsys database (.db) format.

• Read

Use Read (read_file is the command-line equivalent) to readdesigns that are already in .db format.

The Analyze command checks the HDL designs for proper syntaxand synthesizable logic, translates the design files into anintermediate format, and stores the intermediate files in the directoryyou specify.

3-4


The Elaborate command first checks the intermediate format filesbefore building a.db design. During this process, Elaboratedetermines whether it has the necessary synthetic operators toreplace the HDL operators, and it also determines correct bus size.

If you use Read to read in HDL files, the Analyze and Elaborate readfunctions are combined; however, Read does not do certain designchecks that Analyze and Elaborate do.

Setting the Current Design

When you start a Design Vision session and read a design, thecurrent design is automatically set to the top-level design. Somecommands require you to set the current design to a subdesignbefore you issue them (the man pages provide such information).

To set the current design,

1. Click the drop-down list on the Design List toolbar to display thedesign names.

2. Select a design name.

Alternatively, you can open a designs list view (by choosing List >Designs View) and double-click a design name.

The command-line equivalent is set current_design.

3-5

Setting the Current Design

Defining the Design Environment

Design Compiler requires that you model the environment of thedesign to be synthesized. This model comprises the externaloperating conditions (manufacturing process, temperature, andvoltage), loads, drives, fanout, and wire load models. It directlyinfluences design synthesis and optimization results.

Defining the design environment can involve invoking a large numberof commands. Many designers find it convenient to define the designenvironment by using the default target technology library settingsand by running scripts to define differences or additions.

To define the design environment by using Design Vision menus,explore the Operating Environment submenu on the Attributesmenu. The online Help has more information about particularcommands and submenus in the Attributes menu.

Setting Design Constraints

Setting design constraints can involve invoking a large number ofcommands. Most designers find it convenient to use scripts to setdesign constraints.

Design Compiler uses design rule and optimization constraints tocontrol the synthesis of the design.

3-6


Setting Design Rule Constraints

Design rules are provided in the vendor technology library to ensurethat the product meets specifications and works as intended. Typicaldesign rules constrain transition times, fanout loads, andcapacitances. These rules specify technology requirements that youcannot violate. (You can, however, specify stricter constraints.)

To set design rule constraints by using the GUI,

• Choose Attributes > Optimization Constraints >Design Constraints, set options as needed, and click OK.

Setting Optimization Constraints

Optimization constraints define the design goals for timing (clocks,clock skews, input delays, and output delays) and area (maximumarea). During optimization, Design Compiler attempts to meet thesegoals; however, it does not violate your design rules. To optimize adesign correctly, you must set realistic optimization constraints.

To set optimization constraints by using the GUI,

• Click Attributes in the menu bar to open the Attributes menu.

Use Specify Clock to set clock constraints. Other optimizationconstraints and settings are in the submenus under the Attributesmenu: Operating Environment, Optimization Constraints, andOptimization Directives. Explore these submenus to find thesettings you need.

For more information about menu items in the Attributes menu, seethe “Attributes Menu” topic in the online Help.

3-7

Setting Design Constraints

Compiling the Design

Use Design Vision to invoke Design Compiler synthesis andoptimization, thus compiling your high-level design description toyour target technology.

Design Vision supports standard synthesis methodology: either atop-down compile or a bottom-up compile. For more informationabout compile methodologies, see the Design Compiler User Guide.

To compile the current design,

1. Choose Design > Compile Design.

The Compile Design dialog box opens.

2. Select or deselect options as you require.

Use the default settings for your first-pass compile. For mostdesigns, the default settings provide good initial results. For moreinformation about compile options, see the Design Compiler UserGuide and the Design Compiler Reference Manual: Optimizationand Timing Analysis.

3. Click OK to begin compiling.

After compiling the design, save the design as described in the nextsection.

3-8


The command log file records your Design Vision session. This logfile is a record of all commands invoked. It includes commands youenter on the command line, commands initiated by your menu anddialog box selections, and tool commands (such as initializationcommands and commands needed to execute user-enteredcommands).

You can use the command.log file to create a script file. Copy the fileand use a text editor to add or remove commands as necessary.

Saving the Design Database

Design Vision does not automatically save designs before exiting.

To save the current design and each of its subdesigns in separateSynopsys database (.db) format files named design_name.db,where design_name is the name of the design,

• Choose File > Save.

To save the current design and all of its subdesigns in a single filewith a different file name or file format,

• Choose File > Save As, enter or select a file name, select a fileformat, and click OK.

Working With Reports

Textual reports are available from the Design menu and the Timingmenu. Use commands in the Design menu to generate designinformation and design object reports. Use commands in the Timing

3-9

Saving the Design Database

menu to generate timing and constraint reports. If these menus donot have the report you need, you can generate any Design Compilerby issuing dc_shell report commands on the command line.

You can generate reports and display them in the report view (thedefault), save them in text files, or both. When you display a report inthe report view, you can select object names in the report. You canalso save or print the report. For more information, see the “ViewingReports” topic in online Help.

Generating Reports for Selected Objects

You can generate reports for selected objects.

To generate a report for a particular design object or group of designobjects,

1. Select an object.

2. Choose a report command in the Design menu to open theassociated dialog box.

You can generate reports for cells, ports, and nets.

3. Click Selection in the report dialog box.

The names of the selected objects appear.

4. Set other options as needed.

5. Click OK.

3-10


Printing Schematics

You can print the path schematic, design schematic, or symbol viewdisplayed in the active schematic view. Be sure that a default printeris set in your .cshrc file.

To print the active schematic view,

1. Generate a path schematic, design schematic, or symbol view.

2. Make sure the view you want to print is the active view.

Click the corresponding tab at the bottom of the workspace if youneed to make the view active.

3. Choose File > Print Schematic.

The Select Printer Settings dialog box opens.

4. Select the print options you require and click OK.

For details about the options in the Print dialog box, see the “Printinga Schematic View” topic in online Help.

3-11

Printing Schematics

3-12


4Solving Timing Problems 4

This chapter presents procedures and suggestions for solving timingproblems by using the features of Design Vision. The chapter doesnot provide details about exercising particular features of DesignVision, such as how to create a histogram or how to create a pathschematic. For detailed information about Design Vision features,see the Design Vision online Help system.


• Before You Analyze

• Creating a Timing Overview

• Choosing a Strategy for Timing Closure

4-1

Before You Analyze

Before you analyze your design with Design Vision, follow yournormal compile methodology to create a constrained gate-leveldesign. A constrained gate-level design is a prerequisite to anytiming analysis.

For more information about using Design Vision to create agate-level design, see Chapter 3, “Performing Basic Tasks.”

Creating a Timing Overview

Creating an overview of the timing of your design is a valuable wayto start any analysis of your design’s timing problems. A timingoverview can help you decide what strategy to follow in gainingtiming closure.

For example, a timing overview can help answer such questions as

• Do I have many failing paths or just a few?

• Can I apply a local strategy for gaining timing closure?

• Do I need a global strategy for gaining timing closure?

To create a timing overview of your design,

1. Start with a constrained gate-level design.

2. Generate an endpoint slack histogram.

Figure 4-1 is a typical endpoint slack histogram for a design with a4-ns clock cycle.

4-2

Chapter 4: Solving Timing Problems

Figure 4-1 Endpoint Slack Histogram

Using information such as that in Figure 4-1, you might decide on alocal strategy if just a few paths are failing by a small margin (failingpath endpoints are in one or more red bins to the left of 0 on thehorizontal axis). Conversely, if you find that many paths are failing, orthat the design is failing your timing goals by a large margin, youmight choose a higher-level, or global, strategy for problem solving.

Endpoints of Selected bin (yellow)

Endpoint names forselected bin

failing paths (red)

4-3

Creating a Timing Overview

Choosing a Strategy for Timing Closure

There is no single strategy that ensures quick and easy timingclosure; however, a strategy based on the size and number of timingviolations can be useful.

Assessing the Relative Size of Your Timing Violations

This section suggests guidelines for describing the relative size oftiming violations in your design. After you create an endpoint slackhistogram, you can use these size guidelines to help you judge whatstrategy to use for timing closure.

What you consider to be small or large violations depends on therequirements of your design and your design process; however,assessing violation size as a percentage of clock cycle can be useful.

• Small violations

Some designers consider small violations to be about 10 percentof the clock cycle or less.

• Large violations

Some designers consider large violations to be about 20 percentof the clock cycle or greater.

• Medium violations

Medium-size timing failures fall between the limits you set forlarge and small failures in your design or design process.

Whether your design is failing timing goals by large or small margins,the best strategy for timing closure is one that uses the least amountof runtime or number of design iterations to achieve timing goals.

4-4


This principle underlies the methodology suggestions in this chapter.For more information about creating a timing overview, see “Creatinga Timing Overview” on page 4-2.

When Timing Violations Are Small

Figure 4-2 is a histogram of a design that is failing timing goals by asmall margin. For example, no path is failing by more than 0.14 ns—that is, less than 10 percent of the 4-ns clock cycle (ignoring inputand output delay). You can click any bin to see the endpoint namesfor the paths in the bin.

Figure 4-2 Design With Small Timing Violations

Clock cycle: 4 ns

Endpoints of

failing paths (red)

4-5


Designs that fail by a small margin can have many failing paths orjust a few. The endpoint slack histogram helps you to recognizequickly which case you have. Whether you have just a few failingpaths or many, you can follow a global or local strategy in fixing theviolations.

If suggestions for fixing small violations (either globally or locally)don’t meet your timing goals, try applying the suggestions in “WhenTiming Violations Are Medium Size” on page 4-8 or “When TimingViolations Are Large” on page 4-11.

Working Globally to Fix Small Violations

To apply a global methodology for fixing small violations, considerrecompiling your design using the incremental option and a highermap effort. The incremental option saves runtime by using thecurrent netlist as the startpoint for design improvements.

The incremental compile with higher map effort has the advantageof simplicity—that is, it requires little or no time spent in analyzing thesource of timing problems. However, this method can change muchof the logic in the design.

Working Locally to Fix Small Violations

If you have a small number of paths with small violations, or if yourviolations seem to come from a limited set of problems on a fewpaths, a local strategy can be effective.

To use a local strategy for fixing small violations,

• Check hierarchy on failing paths

4-6


Design Compiler does not optimize across hierarchicalboundaries. Thus, snake paths limit Design Compiler’s ability tosolve timing problems on such paths.

• Look for excessive fanout on failing paths

Because higher fanout causes higher transition times, excessivefanout can worsen negative slack on failing paths.

To check for hierarchy problems on failing paths (dctcl mode only),


2. Click a bin that contains a failing path.

A list of endpoints for failing paths is displayed.

3. Select the endpoint for the path you are interested in.

4. Generate a path schematic to see which leaf cells are in whichlevels of hierarchy.

If your critical path, for example, crosses multiple subblocks of alevel of hierarchy, consider ungrouping these subblocks. DesignCompiler does not optimize across hierarchy boundaries. Thus,a subsequent compile has further opportunity to optimize thecritical path when you ungroup such blocks.

To look for excessive fanout on failing paths,


2. Select the endpoints for failing paths.

Select the failing bin to see the endpoints.

4-7


3. Generate a timing report with the following options:

- net

- trans

Send the report output to the report view. For more informationon report generation, see “Working With Reports” on page 3-9and the “Viewing Reports” topic in online Help.

4. Examine the report for pins with high transition times and netswith high fanout.

Such paths are candidates for buffering or drive-cell resizing.

5. Create path schematics of any paths you would like to see.

A path schematic provides contextual information and detailsabout the path and its components. Such information is often aprerequisite to understanding problems on the path.

6. View fanin and fanout for path schematics.

This step can provide useful information about the logic thatdrives, or is driven by, the problem path. For example, afterviewing fanin or fanout, you might choose to resize cells in thoselogic cones.

When Timing Violations Are Medium Size

Figure 4-3 is a histogram of a design that is failing timing goals bymargins that are between the large and small limits that areappropriate to your design methodology (for example, between 10and 20 percent of the clock cycle). You can click a bin to see theendpoint names for paths the bin contains. A bin is yellow whenselected. In Figure 4-3, one of the four bins containing endpoints offailing paths is selected.

4-8


Figure 4-3 Design With Medium Timing Violations

When negative slack values are medium, you can use Design Visionto investigate further and focus your recompile on a critical range ofnegative slack values for path groups. Focusing your compile efforton a critical range can improve worst negative slack and totalnegative slack. For more information about calculating worstnegative slack and total negative slack, see the SolvNet articleSynthesis-238.html.

Defining a critical range for path groups offers the advantage ofconcentrating compile effort and runtime on those areas that mostneed it.

Clock cycle: 4 ns

Endpoints of failing paths

4-9


To investigate and focus a recompile by defining a critical negativeslack range for path groups,

1. Create a path slack histogram for each path group in your design.

Start with an arbitrary value of 1000 for the number of paths toinclude in each histogram. Raise or lower this value dependingon the number of failing paths. The goal is to choose a value thatshows you all or nearly all of the failing paths.

2. Decide on a critical range for each path group (note the values foruse in step 3).

When deciding on a critical range, choose a range that allows DesignCompiler to focus on the worst endpoint violations without too largean increase in runtime. For example, some designers apply one ofthe following guidelines to decide on a critical range:

- Use a range that includes the worst 50 paths in a group.

- Use a range equal to one generic cell delay in your technology.

These are rough guidelines; for subsequent compiles you canadjust your critical range as necessary.

3. Set a critical range for each path group.

Using the values you decided on in step 2, set the critical rangesfor each path group with the group_path command. Forexample,

design_vision-t> group_path -name my_clock -critical_range 0.25

4-10


4. Recompile the design.

With a critical range defined, the compile effort is now focused.However, you can also choose to increase the compile effort overyour previous compile. In the Compile Design dialog box, selectmedium or high effort. Select the “Incremental mapping” optionto direct Design Compiler to use the current netlist as a startingpoint for design improvements. An incremental compile can saveruntime when your design does not require fundamentalchanges.

For more information about defining critical ranges for synthesis, seethe SolvNet article Methodology-10.html.

If suggestions in this section don’t meet your timing goals, tryapplying the suggestions in “When Timing Violations Are Large” onpage 4-11.

When Timing Violations Are Large

Figure 4-4 shows a design that is failing timing goals by a largemargin. You can click a bin to see the endpoint names for the pathsit contains.

4-11


Figure 4-4 Design With Large Timing Violations

Fixing large violations can require a high-level strategy to improveyour design’s performance. To fix large timing problems, considerany of the following changes:

• Modify your constraints.

For example, increase the clock cycle or adjust time budgeting forthe block or chip.

• Change the target technology.

For example, target a higher performance technology.

Clock cycle: 4 ns

Endpoints of failing paths

4-12


• Modify the RTL.

For example, you can move late-arriving signals such that youminimize their path length.

4-13


4-14


Index

Aappearance, changing for schematics 2-13Attributes menu 3-7

Ccell clustering data, supported formats 1-4change_selection command 2-15closure, timing, strategy for 4-4command.log 3-9commands for scripting 2-15compiling

focusing on timing range 4-10starting, how to 3-8

conditions, operating 3-6Console, description 2-11constraints, setting 3-6critical timing range

choosing for compile 4-10current design, setting 3-5current instance, setting 3-5

D.db file, saving 3-9

dcsh mode, starting 2-7dcsh mode, starting without GUI 2-8dcsh scripts 2-14dctcl mode, starting 2-7dctcl mode, starting without the GUI 2-8dctcl scripts 2-14design

current, setting 3-5writing to disk 3-9

design constraints, setting 3-6design files, supported formats 1-4design schematics 2-11Design Vision

documentation set 2-2features of 1-2formats, input and output 1-4graphical window components 2-9introduction to 1-1licensing for 1-5supported platforms 1-6Synopsys products, relationship to other 1-7user interfaces 1-3

design, reading in a 3-4documentation, Design Vision 2-2drive strength, setting 3-6

IN-1

Eenvironment, setting operating 3-6errors/warnings view 2-11excessive fanout, finding 4-7, 4-8

Ffanout, excessive, finding 4-7, 4-8fanout, setting maximum 3-6features, Design Vision 1-2files

log files 3-9setup files 2-5

finding reported objects in schematic 3-9focusing compile 4-10formats

cell clustering 1-4design data 1-4input and output 1-4library 1-4netlist 1-4parasitics 1-4script file 1-4timing data 1-4

Ggenerating reports 3-9get_selection command 2-15global approach, timing closure

large violations 4-12small violations 4-6

group_path command 4-10GUI (see window, Design Vision)

HHelp, online 2-4hierarchy, finding excessive 4-7histogram views 2-11

histogramsendpoint slack 4-2script commands for 2-15

history view 2-11

Iinitialization (see setup files)instance tree 2-10instance, setting current 3-5interfaces, Design Vision 1-3

Llarge timing violations

defined 4-4global approach 4-12

layers, changing appearance 2-13libraries

specifying 3-3supported formats 1-4synthetic libraries 3-3

licensing 1-5list views 2-12loads, setting 3-6log files

naming 3-9scripts, creating from 3-9

log view 2-11logic hierarchy view, description 2-10

Mmanufacturing process, setting 3-6medium-size timing violations

defining 4-4fixing 4-8

methodologychoosing for timing closure 4-4large violations, for 4-11medium-size violations, for 4-8

IN-2

small violations, for 4-5, 4-6

Oobjects, locating reported 3-9objects, reports for selected 3-10online Help, description of 2-4OpenWindows, support for 1-6operating conditions, setting 3-6operating systems

patches for 1-7supported platforms 1-6

optimizationconstraints, setting 3-6initiating 3-8

overview, creating for timing 4-2

Pparasitics, supported formats 1-4patches, operating system 1-7path schematics 2-11preferences, schematic appearance 2-13printing

schematics 3-11

Rreading a design 3-4reports

for selected objects 3-10generating 3-9

Ssaving to disk 3-9schematic views 2-11schematics

appearance, changing 2-13printing 3-11

SCL (Synopys Common Licensing) 1-5scripts

command-line interface, running from 2-14commands 2-15creating from log file 3-9histogram, generating 2-15menu access to 2-14mode, Tcl and dsch 2-14supported formats 1-4

setup files 2-5slack types, SolvNet article about 4-9small timing violations

defining 4-4global approach to solving 4-6local approach to solving 4-6

snake paths, finding 4-7SolvNet articles

slack types, calculating 4-9specifying libraries 3-3status bar 2-9, 2-12supported

operating systems 1-6window managers 1-6

Synopsys Common Licensing 1-5synthesis, initiating 3-8synthetic libraries 3-3

TTcl mode, starting 2-7timing closure, methodology

for large violations 4-11for medium-size violations 4-8for small violations

high-level approach 4-6introduction 4-5low-level approach 4-6

timing data, supported formats for 1-4timing problems, solving

histogram, endpoint slack 4-2judging violation size 4-4

IN-3

strategy for closure, choosing 4-4timing overview, creating 4-2

toolbar 2-9tutorial, overview of 2-2

Uusing scripts 2-14

Vviolations, timing

fixing large 4-11fixing medium size 4-8fixing small 4-5judging relative size of 4-4

Wwindow managers, supported 1-6window, Design Vision

components of 2-9modes of initialization 2-7schematics, setting appearance 2-13starting and exiting 2-7

wire load models, setting 3-6workspace 2-9writing to disk 3-9

IN-4

36186641 design vision timing analysis

Documents