IC Lab

OPERATIONAL AMPLIFIER

IC Lab

REAL OP AMP SPECIFICATION

è Low-Frequency Voltage Gain AVO & Power Dissipation

è 3-dB Frequency f3dB & Unity-Gain Frequency f0

è Slew Rate & Settling Time

è Input / Output Range & Output Impedance

è Offset Voltage & Noise

è PSRR (Power Supply Rejection Ratio)

è CMRR (Common-Mode Rejection Ratio)

+ -

VIC

CMRR+ -

∆Vsupply

PSRR+ -

Voffset

+ -

Vn2

+

-

vin gmvin

V1

ouputbuffer

CO RO

V2

vO

IC Lab

2-STAGE MILLER OP AMP

M4 M3

M2 M1

M5

M6

M7

CC RC

VDD

VSS

vin+vin

-vout

M8

IB

CL

+-vin

-

vin+

CC RC

vout

-AV1 -AV2

differentialamplifier

CSamplifier

IC Lab

2-STAGE MILLER OP AMP : AVO

l DC Voltage Gain

l Power Dissipation

M2 M1

M3

M4

M5

M6

M7

CC RC

VDD

VSS

vin+vin

-vout

M8

IB

CL

+

−⋅

+

−=⋅=−

≡ −+7o6o

6m

3o1o

1m2V1V

inin

outVO gg

ggg

gAA

vv

vA

( ) ( )75SSDD IIVVPower +⋅−=

IC Lab

2-STAGE MILLER OP AMP : OPERTING POINT

l

l

l

l

l

M2 M1

M3M4

M5

M6

M7

CC RC

VDD

VSS

vin+vin

-vout

M8

IB

CL

A B

C

D E

F

G

) GND Analog ( 0VV BA ==

( )( ) ( )22IV

2IV

V0V

151TH

111TH

1SGC

β+=

β+=

+=

( )( ) ( )22IV

2IV

VVVV

353TH

333TH

3GSSSED

β+=

β+=

+==

) GND Analog ( 0VF ⇒

( )[ ]2IVVDD

VVV

8B8TH

8SGDDG

β+−=

−=

Make Sure All Transistorsin Saturation !

IC Lab

2-STAGE MILLER OP AMP : INPUT COMMON MODE RANGE

l Upper Range : M5 in Saturation

l Lower Range : M1(2) in SaturationM2 M1

M3M4

M5

VDD

VSS

VICVIC

1TH1DICL

1THICL1D1G1D1DG

VVV

VVVVVV

−>

<−=−=

( )( ) ( )22IVVV

2IVVV

VVVV

151TH)sat(5SDDD

111TH)sat(5SDDD

1SG)sat(5SDDDICU

β+−−=

β+−−=

−−=

( )( ) ( )22IVV

2IVV

VVVVV

353THSS

333THSS

3GSSS4D3D1D

β++=

β++=

+===

( ) ( ) TH353THSSICL V22IVVV −β++=

IC Lab

FEEDBACK & STABILITY

ü Unstable Condition : F AV(s) = -1

Av(s)+

F

+

-Vin(s) Vout(s)

( ) ( )( )

( )( )sAF1

sA

sV

sVsA

v

v

in

out⋅+

=≡

|Av(s)| [dB]

ω

ω

-180o

|Av(0)|

<Av(s)

1/F

-90o

phasemargin

0

( ) ( ) °−=∠= 180sA & F

1sA vv

IC Lab

SMALL-SIGNAL 2-STAGE MILLER OP MODEL

M2 M1

M3M4

M5

M6

M7

CC RC

VDD

VSS

vin+vin

-vout

M8

IB

CL

gmIvin RI CIvin

+

-

vx

+

-

gmII vx RII CII vout

+

-

RC CC

IC Lab

2-STAGE MILLER OP AMP : UNCOMPENSATED

( ) ( )

−⋅

−

=

III

vv

p

s1

p

s1

0AsA

III CR

1p −=

gmIvin RI CIvin

+

-

vx

+

-

gmII vx RII CII vout

+

-

|Av(s)| [dB]

ω

ω

-180o

|Av(0)|

<Av(s)

-90o

phase margin

0ω0

|p I| |p II|

IIIIII CR

1p −=

IC Lab

2-STAGE MILLER OP AMP : COMPENSATED

è pole splitting

gmIvin RI CIvin

+

-

vx

+

-

gmII vx RII CII vout

+

-

CC

|Av(s)| [dB]

ω

ω

-180o

|Av(0)|

<Av(s)

-90o

phasemargin

0ω0|p I|

|p II| z'

-270o

IIIImIII CRRg

1p −≅′

II

mII

ICCIIIII

CmIIII C

g

CCCCCC

Cgp −≈

++−≅′

1C

C

Rg

1

p

p

C

I

IImIII

I <<=′

1CCCC1

Rg

p

p

IIICI

IImII

II

II >>++

=′

IC Lab

2-STAGE MILLER OP AMP : TO GET PHASE MARGIN 1

l For frequency > |p’I|

l Phase of Av(s) @ ω0 > |p’I|

l For Phase Margin ΦM

l Unity-Gain Frequency

l 2nd pole Frequency

( ) ( ) )ps1()ps1(

sAsA

III

vv ′+⋅′+

=

( ) ( ) )ps1()ps(

sAsA

III

vv ′+⋅′

≅

( ) ( )II01

v ptan90sA ′ω−°−=∠ −

( ) ( ) IIM0MII01 p90tan90ptan ′⋅Φ−°=ω⇒Φ−°=′ω−

( ) CmICIIImII

IImIIImIIv0 Cg

CRRg

RgRgp0A ==′⋅=ω

IImIIII Cgp =′

( ) mIC

II

MmII g

C

C

90tan

1g ⋅⋅

Φ−°=∴

IC Lab

2-STAGE MILLER OP AMP : ZERO-PROBLEM

l Parasitic Zero

l Role of RC

l Remove Zero

|Av(s)| [dB]

ω

ω

-180 o

|Av(0)|

<Av(s)

-90 o

phase

margin

0ω

0

|pI| |p

II|z'

-270 o

C

mII

C

gz =′

( ) CCmII CRg1

1z

−=′′

mIIC g1R z =⇒∞→′′

+≅⇒′=′′

C

II

mIICII

C

C1

g

1R pz

IC Lab

2-STAGE MILLER OP AMP : RC IMPLEMENTATION

M13

M12

M6

M7

CC

VDD

VSS

vout

M14

VB

VX

M11

( )THn11GS11C VV

1R

−β=

( )THn6GS66mmII VVgg −β==

11GS6GS14GS13GSx VVVVV +=+=

( )THn6GSTHn11GSTHn13GS6GS14GS VVkVVVV VV −=−=−⇒=

kVV

VV

g1

RTHn11GS

THn6GS

mIIC =

−−

⇒∝

7

12

13

6

7

12

13

6

6

13

13

6

6

6

13

13

THn6GS

THn13GSI

I

I

I

I2

I2

VV

VVk

ββ

ββ

=ββ

=ββ

=β

β=

−−

=

7

12

7

12

6

14

6

14

6

6

14

146GS14GS I

I

I

I

II VV

ββ

===ββ

⇒β

=β

⇒=

13

14kββ

=∴

IC Lab

2-STAGE MILLER OP AMP : WELL COMPENSATED

|Av(s)| [dB]

ω

ω

-180o

|Av(0)|

<Av(s)

-90o

phasemargin

0 ω0|p I|

|p II|

( ) ( )

I

vv

ps

1

0AsA

′−

=

( )C

mIIIv0 C

gp0A =′⋅=ω

IC Lab

OP AMP : TRANSIENT RESPONSE

l t0 < t < t1 è Slewing : Large Signal Behavior

l t1 < t < t2 è Settling : Small Signal Behavior

+

-vout(t)

CL

vin(t)

t

vout(t)vin(t)

0

t0 t1 t2

imummax

outdt

dV rateslew =

osettle t t ε<ε=

IC Lab

2-STAGE MILLER OP AMP : LARGE-SIGNAL TRANSIENT

l When Vin goes to rise initially, M2 off & All I5 flows in M1M3M4

l Vout goes up linearly with the rate of

M5

VDD

M1 M2

M3 M4

VSS

vin

VBP

vout

CL

CC

-A2

I5

I5

C

5outC

I

dt

dV=

IC Lab

OP AMP : SMALL-SIGNAL TRANSIENT – 1st Order

l Closed-Loop Transfer Function

l Output Waveform

l Time Constant

l Settling Error

l Settling Time

( )( )

( )[ ]0FA1p

s1

1

0FA1

0A)s(A

v1

v

v

+++

=

( )( ) ( )τ−−⋅⋅

+= t

stepv

vout e1V

0FA10A

)t(V

( )[ ] ( ) 0v1v1 F

1

0ApF

1

0FA1p

1

ω⋅=

⋅≅

+≡τ

( ) ( )( )

τ−=−

≡ε t

out

outin etV

tVtV

ε

⋅τ≡o

settle1

lnt

IC Lab

OP AMP : SMALL-SIGNAL TRANSIENT – 2nd Order

l Closed-Loop Transfer Function

l Oscillation Frequency

l Q Factor

l Q < 1/2

l Q = 1/2

l Q > 1/2

( )[ ] ( ) 202v1v21N pFp0ApF0FA1pp ω=≅+≡ω

( )[ ] ( )21

20

21

2v1

21

v21

pp

pF

pp

p0ApF

pp

0FA1ppQ

+

ω=

+≅

+

+≡

( )( ) 2

NN2

2N

v

v

sQ

s0FA1

0A)s(A

ω+

ω+

ω

+=

( ) ( )

γ−

γ−

ω+⋅⋅=

γγ

2

t2

1

t1

2N

stepoutee

4Q11V0AtV

( ) ( ) ( )tNNtNstepout tee1V0AtV ω−ω− ω−−⋅⋅=

( ) ( )

ω−+

−

ω−

−⋅⋅=

ω−

tQ2

1Q4cos1Q4

tQ2

1Q4sin

e1V0AtV N22

N2t

Q2N

stepout

IC Lab

OP AMP : SMALL-SIGNAL TRANSIENT – 2nd Order (cont’d)

0 2 4 6 8 100

0.2

0.4

0.6

0.8

1

1.2

normalized time

no

rmal

ized

ou

tpu

t Q=0.1Q=0.5

Q=1.0

IC Lab

2-STAGE MILLER OP AMP : SMALL-SIGNAL TRANSIENT

l By Substitution of p’I & p’II

l For Phase Margin ΦM

( ) F

g

g

Cg

CFgg

CgC0Ag

CFggQ

mII

mI

IImII

IImIImI

IImIIIIvmI

IImIImI =≅+

=

II

mIImIN C

Fgg=ω

( ) mImIC

II

MmII gg

CC

90tan1

g ⋅α≡⋅⋅Φ−°

=

0II

C

II

mIN C

CF

C

gFω⋅⋅⋅α=

⋅⋅α=ω

α== F

Q

IC Lab

2-STAGE MILLER OP AMP : SMALL-SIGNAL TRANSIENT (cont’d)

CC=CL, F=2

ΦM 80º 40º

α 5.67 0.84

ωN 1.68 ω0 0.65 ω0

Q 0.30 0.77

0 5 10 15 20-0.5

0

0.5

1

1.5

0 5 10 15 2010

-6

10-4

10-2

100

normalized time

no

rmal

ized

ou

tpu

t PM=80o

rela

tive

erro

r

PM=40o

PM=80o

PM=40o

+

-vout(t)

CL

vin(t)

R2 = 100kΩ

R1 = 100kΩ

IC Lab

OP AMP : OFFSET VOLTAGE

l Definition

l For Non-Ideal Differential Pair

è BJT :

è CMOS :

l Random Offset Component Due to Process

l Systematic Offset Component Due to Circuit Design

0outVinOFFSET VV ⇒∆≡

mOFFSET g

IV

∆∝

etemperatur room@ mV26q

kT

g

I

m==

100mV several 2

VV

g

I THGS

m≈

−=

IC Lab

2-STAGE MILLER OP AMP : RANDOM OFFSET VOLTAGE

l Random Characteristics l 1st Stage Random Offset

Voffset

#

0

VOFFSET M1 M2

ISS

RL1 RL2

VDD

VO1 VO2

∆−

∆−−+∆=

LW

LW

R

R

2

VVVV

L

LTHGSTHOFFSET

IC Lab

2-STAGE MILLER OP AMP : SYSTEMATIC OFFSET VOLTAGE

M2 M1

M3M4

M5

M6

M7

VDD

VSS

Vout=0V

VDS3

+

-

+

-

VGS6

VBP

4

5THn

4

4THn4GS4DS3DS

IV

I2VVVV

β+=

β+===

6

7THn

6

6THn6GS

I2V

I2VV

β+=

β+=

4

7

5

76II

2II

4==

ββ

∴

IC Lab

MOSFET NOISE MODEL

l 1-f Noise

l Thermal Noise

l MOSFET Noise Model

( )f

1

WLC

KfV

ox

2f1 ⋅=

( ) ( )m

2thrmlm

2thrml g

132

kT4fV g32

kT4fI ⋅⋅=⇔⋅⋅=

V1/f2(f)

Ithrml2(f)

V1/f2(f)

Vthrml2(f)

IC Lab

2-STAGE MILLER OP AMP : INPUT-REFERRED NOISE

M2 M1

M3M4

M5

M6

M7

VDD

VSS

Vout

VBP

Vn,52

Vn,72

Vn,22Vn,1

2

Vn,32 Vn,4

2

Vn,62

M2 M1

M3M4

M5

M6

M7

VDD

VSS

Vout

VBP

Vn,eq2

( )24,n

23,n

2

3m

1m22,n

21,n

2eq,n VV

g

gVVV +

++=

( )f

1

L

L

K

K1

WLC

K2fV

23

21

pp

nn

ox

p2eq,f/1 ⋅

µµ

+⋅=

( )( )

( )( )

µµ

+⋅µ

⋅=1p

3n

11oxp

2thrml LW

LW1

ILWC2

4kT4fV

IC Lab

OP AMP : CMRR

l Definition

l Modeling & Simulation

( )c

dinincinindout A

ACMRR

2

VVAVVAV ≡⇒

+⋅+−⋅=

−+−+

+

-vout

+

+

-

-

vcm

vcm

v+

v-

vout

+

+

-

-

vcm

vcm

v+

v-

Ad(v+-v-)

+

-

Ac(v++v-)/2

+

-

CMRR1

AA

2A

A1

AVV

d

c

cd

c

cm

out =≅−+

=

IC Lab

OP AMP : PSRR

l Definition

l Modeling & Simulation

( )−

−+

+

−+−+

≡≡⇒

∆⋅+∆⋅+−⋅=

p

d

p

d

SSpDDpinindout

A

ARRSP ,

A

ARRSP

VAVAVVAV

+

+=≅

∆ PSRR

1

A

A

V

V

d

p

DD

out

+

-vout

v+

v-

vout

+

-

-VDD

v+

v-

Ad(v+-v-)

+

-

Ap+∆VDD

+

-

+

∆VDD

IC Lab

2-STAGE MILLER OP AMP : PSRR

M6

M2 M1

M3M4

M5

M6

M7

CC

VDD

VSS

vin+vin

- vout

VBB

vout

M7

VDD

VSS

ro7

1/gm6

IC Lab

2-STAGE MILLER OP AMP : NUMERICAL DESIGN

DC Gain Av(0) [dB] ≥66

Unity-Gain Frequency f0 [MHz] 25 CL=10pF

Phase Margin [ ° ] 60

Slew Rate [V/µsec] 25

Power Dissipation [mW] ≤2.5 ±2.5V

SNR @ 1kHz [dB] ≥90 VIN=0.5VRMS

è

è

è

è

è

è

( ) [pF] 0.5C21C LC =⋅=

[A/V] 10785.0CgCg 3C01mC1m0

−×=⋅ω≅⇒≅ω

[A] 10125CSRICISR 6C5C5

−×=⋅=⇒=

( ) ( ) 85.140LWILWCII2g 151oxp51111m =⇒µ=β=β=

( )[ ] ( ) [A/V] 10719.2gCC90tang 31mCL

1M6m

−− ×=⋅⋅Φ−°=

( ) ( ) [A] 10375IVVII Power 67SSDD75

−×=⇒−⋅+=

IC Lab

2-STAGE MILLER OP AMP : NUMERICAL DESIGN (cont’d)

è

è

è

è

è

( ) ( ) 43.246LWILWCI2I2g 676oxn76666m =⇒µ=β=β=

( )( ) ( ) 07.41LW6

II

I

I

LW

LW3

1

7

3

6

3

6 =⇒===

( ) ( )[ ] ( )[ ] [dB] 1.672276rrgrrg0A 7o6o6m3o1o1mv →=⋅=

[ ] [ ] ( )[ ] ][ 1067.1062IIgr 315p

11p

11o1o Ω×=λ=λ== −−−

[ ] [ ] ( )[ ] ][ 1000.3202IIgr 315n

13n

13o3o Ω×=λ=λ== −−−

[ ] [ ] [ ] ][ 1033.53IIgr 317n

16n

16o6o Ω×=λ=λ== −−−

[ ] [ ] ][ 1078.17Igr 317p

17o7o Ω×=λ== −−

( )( )( ) ][V 10183f

LW

LW1

ILWC2

4kT4V 215

1p

3n

11oxp

2eq,thermal

−×=∆⋅

µµ

+⋅µ

⋅=

[dB] 4.107V

Vlog10SNR

2eq,thermal

2rmsIN, =

=

IC Lab

FOLDED-CASCODE OP AMP : CONSTRUCTION

l Single Stage Amplifier

l Compensation w/ Load Capacitance è Suitable for SC Circuits

M0

VDD

CL

M1 M2

M3 M4

M6

M8

M5

M7

VSS

vin-vin

+

VBN1

VBN2

vout

M0

VDD

M1 M2

M6

M8

M5

M7

VSS

vin-vin

+

VBN1

VBP2

vout

M9 M10

M3 M4

VBP1

IC Lab

FOLDED-CASCODE OP AMP : AC CHARACTERISTICS

l Voltage Gain

l Frequency Response

l Unity-Gain Frequency

( ) ( )

+⋅=⋅=

10o2o4o

4m

8o6o

6m1mout1mv

ggg

g

gg

ggrg0A

( ) ( ) ( )( )Lout

v

I

vv Crs1

0A

ps1

0AsA

+=

−=

|Av(s)| [dB]

ω

ω

-180o

|Av(0)|

<Av(s)

-90o

phasemargin

0ω0|p I|

|p II|

( )L

1mIIv0 C

gp0A =⋅=ω

gsoutgs

1m

gsernalintII Cr

1Cg

Cr1

p >>→=

IC Lab

FOLDED-CASCODE OP AMP : NUMERICAL DESIGN

DC Gain Av(0) [dB] ≥60

Unity-Gain Frequency f0 [MHz] 20 CL=10pF

Phase Margin [ ° ] 60

Slew Rate [V/µsec] 10

Power Dissipation [mW] ≤2.5 ±2.5V

Output Range [V] -1.0 ~ +1.0

è

è

è

è

è

è

[A/V] 10256.1CgCg 3L01mL1m0

−×=⋅ω≅⇒≅ω

[A] 10100CSRICISR 6L0L0

−×=⋅=⇒=

( ) ( ) 19.197LWILWCII2g 101oxn01111m =⇒µ=β=β=

( ) ( ) ( ) [A] 10250IVVI2VVII Power 69SSDD9SSDD109

−×=⇒−⋅=−⋅+=

[A] 10200IIIII [A] 10502II 619753

601

−− ×=−===×==

[A] 10200IIIII [A] 10502II 6210864

602

−− ×=−===×==

IC Lab

FOLDED-CASCODE OP AMP : NUMERICAL DESIGN (cont’d)

è M5-8

è M5-8

è M5-8

è M3-4,M9-10

è M3-4

è M5-8

è

è

[V] 425.0VV--1.02VV DSn(sat)SSDSn(sat)THn =⇒=+

( )( ) ( ) [A/V] 10215.2V2VV2I 385

2DSn(sat)8-5

2THnGSn8-58-5

−− ×=β⇒β=−β=

( ) ( ) 68.27LWLWC 8585oxn85 =⇒µ=β −−−

( ) ( ) 98.126LW [A/V], 10444.4V2I 433

432

SDp(sat)4-34-3 =×=β⇒β= −−

−

[V] 300.0V1.0-V2VV SDp(sat)DDSDp(sat)THp =⇒=+

( ) ( ) 73.158LW [A/V], 10556.5V2I 1093

1092

SDp(sat)10-910-9 =×=β⇒β= −−

−

( ) ( ) [dB] 611122ggg

ggg

ggrg0A

10o2o4o

4m

8o6o

6m1mout1mv →=

+

⋅=⋅=

[A/V] 10941.0I2g 3666m

−×=β= [A/V] 1010Igg 66n8o6o

−×=λ==

[A/V] 10333.1I2g 3444m

−×=β= [A/V] 1030Ig 64p4o

−×=λ=

[A/V] 105.7Ig 62p2o

−×=λ= [A/V] 105.37Ig 610p10o

−×=λ=

0ernalint4GS

2o10o4o4m

minGS

omernalint f [GHz] 4.1f

C

gggg

C

ggp >>=⇒

+++=∑+

=

IC Lab

FOLDED-CASCODE OP AMP : FULLY-DIFFERENTIAL

l Voltage Gain

l Common-Mode Noise Can Be

Removed

l Common-Mode Feedback

(CMFB) Circuit Needed

CLM0

VDD

M1 M2

M6

M8

M5

M7

VSS

vin-vin

+

VBN1

VBN1

vout+

M9 M10

M3 M4

VBP1

VCMFB

CL

vout-

VBP2

VSS

−+

−+

−

−≡

inin

outoutv

VV

VVA

IC Lab

FOLDED-CASCODE OP AMP : FULLY-DIFFERENTIAL (IMPROVED)

CLM0

VDD

M1 M2

M6

M8

M5

M7

VSS

vin-vin

+

VBN1

VBN1

vout+

M9

M10

M3 M4VBP1

VCMFB

CL

vout-

VBP2

VSS

+-

+-

VBN1

+-

+-

VBP1

( ) ( )

+⋅⋅

⋅=⋅=10o2o4o

4m

8o6o

6m1mout1mv

ggg

gA

gg

gAgrg0A

IC Lab

CMFB EXAMPLE (CONTINUOUS-TIME)

l Using Averaging Resistors l Using 2 Differential Pairs

M1

VREF

VSS

M6M5

VDD

vout+ vout

-

M3

M2

M4

RP RM

CP CM

M7 M8

M9

VCNTL

VCM

VBP

VBN

VREF

VSS

M2M1

VDD

vout+ vout

-

M3

VCNTL

VBPIB

M4M5

M6

M7 M9M8

IB

IC Lab

CMFB EXAMPLE (DISCRETE-TIME)

l For Φ1

l For Φ2

vout+ vout

-

CC

VCNTL

VB

CS CC CS

VB

φ1

φ1

φ2

φ2 φ1φ2

φ1φ2

( )BS1 VC2Q −⋅⋅=∑

( )( ) ( )( )CNTLoutCSCNTLoutCS2 VVCCVVCCQ −++−+=∑ −+

BCS

SoutoutCNTL V

CC

C

2

VVV

++

+=∴

−+

IC Lab

RAIL-TO-RAIL INPUT STAGE : SINGLE DIFFERENTIAL PAIR

l Single-Polarity Differential Pair Limits Input Range

l nMOS Differential Pair

l pMOS Differential Pair

M2 M1

M3

vin-

VBN

VSS

vin+

VDS3(sat)

VGS1

VSS

operatinginput range

M5 M4

M6

vin-

VBP

VDD

vin+

VSD6(sat)

VSG4

VDD

operatinginput range

( ) DDINPUTGSsatDSSS VVVVV ≤≤++

( )( )GSsatDSDDINPUTSS VVVVV +−≤≤

IC Lab

RAIL-TO-RAIL INPUT STAGE : DOUBLE DIFFERENTIAL PAIR

l For Input ~ VSS

è nMOS off & pMOS on

è gmIN = gmp

l For Input ~ VDD

è nMOS on & pMOS off

è gmIN = gmn

l For Input ~ 0

è nMOS on & pMOS of

è gmIN = gmp +gmn

CL

M3

VDD

M1 M2

M12

M14

M11

M13

VSS

vin-vin

+

VBN0

VBN1

vout+

M9 M10

M7 M8

VBP1

VCMFB

vout-

VBP2

VSS

M5M4

VDD

vin+ vin

-

VBP0 M6

CL

IC Lab

RAIL-TO-RAIL INPUT STAGE : CONSTANT Gm APPROACH

l For nMOS Differential Pair Off : gmp è 2gmp by Providing ISSP+3ISSP

l For pMOS Differential Pair Off : gmn è 2gmn by Providing ISSN+3ISSN

l For Both Differential Pair On : No Additional Current

M1N M2N

VSS

vin-vin

+

M2PM1P

VDD

vin+ vin

-

ISS

M3

VREFN

ISS

VREFP

M4 M5

M6

M7M8

IC Lab

CLASS-AB OUTPUT STAGE : CD

l Small Output Impedance Preferable

l Output Range Limited By 2VGS+VDS(sat) Each

l Quiescent Point

l Distortion Possible Due to Full-Off of M1 or M2

M1

M2

M3

M4

voutvin

VDD

VSS

I1

I2

IREF

IREF

IOUT

IOUT=I1-I2

0 4IQ-4IQ

4IQ4IQ

IQIQ

I2 I1

I1I2

QREF3

121 I2I2II =

ββ

=+

IC Lab

CLASS-AB OUTPUT STAGE : CS

l Output Range Limited By VDS(sat) Each

l Quiescent Point

l Negligible Distortion Due to

M1

M2

vout

vin1

VDD

VSS

I1

I2

IOUT=I1-I2

0 4IQ-4IQ

IQIQ

I2 I1

I1I2

M3M4

M5

M7

M6

M8

IB

2IB IB

2IB

vin2

IminImin

75B

2

3

11Q

111 where ,II

β+

β=

α⋅

ββ

−αβ

=

B

2

3

11min I2I ⋅

ββ

−αβ

=

IC Lab

CLASS-AB OUTPUT STAGE : CS (EXACT CONTROL)

l Exact Control By Feedback Amplifier

l Quiescent Point

l Minimum Current

M1

M2

vout

vin1

VDD

VSS

I1

I2

M3

M4M5M7

M6

M8

IB1

2IB1

2IB2

vin2

IB1 IB1 2IB2

M9

M10 M11

M12

1B12

62BQ II2I

ββ

−=

( ) 1B

2

9

12

12

82Bmin I121I2I ⋅

ββ

−+ββ

−=

IC Lab

VARIOUS OP AMP EXAMPLE (MULTI-LOOP, MULTI-PATH)

l Multi-Stage For Large Gain w/o Using Cascode Stage

l Multi-Loop & Multi-Path Compensation

l Combined High-Freq. Path (A4-A1) & High-Freq. Path (A3-A2-A1)

to Achieve Pole-Zero Cancellation when

1 IEEE JSSC pp. 1709-1717, 1992.

A1

VSS

VDD

vout

A2A3A4

p1p2p3

vin

Cm1

Cm2

gm4

gm3

gm2

gm1

|Av(s)| [dB]

ω

|Av(0)|

0p'2 p'3

p'1

ω0dB

1m4m2m3m CgCg =

IC Lab

VARIOUS OP AMP EXAMPLE (REPLICA AMP)

l w/o Replica Amp

l w/ Replica Amp

1 IEEE ISSCC pp. 116-117, 1993.

vout

Ro

vin

ZF

+

-ZS

v'out

Ro

ZF

+

-ZS

+

-

vx

vy

gm

gm

gm

mainamp

replicaamp

( ) oin

outA11

1

V

V

β++β−=

( )( ) o

o1 A11

A1

β++β+

=ε

( ) o

o

in

outA11

A1

11

V

V

β+++β+β+

+β−=

( )( )( ) ( )β+

ε≅

β+++β+

β+

=ε1AA11

A1A

1

o

1

o

oo

2

2

IC Lab

VARIOUS OP AMP EXAMPLE (SWITCHED)

l Replace the Switch on Signal Path

l Power Saving When Not Used

1 IEEE JSSC pp. 936-942, 1994.

M2 M1

M3M4

M5

M6

M7

CC RC

VDD

VSS

vin+vin

-vout

M8

IB

CL

MCP

MCN φ

φ