op amp characteristics

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SINGLE STAGE OPERATIONAL AMPLIFER

SIMULATIONS AND TEST BENCHES FOR VARIOUS

SPECIFICATIONS

SAMI UR [email protected]

mailto:[email protected]

mailto:[email protected]



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Table of Contents:

OVERVIEW…………………………………………………………………………………………………………

SLEW RATE SIMULATIONS AND CALCULATIONS (WITH LOAD)………………………….

SLEW RATE SIMULATIONS AND CALCULATIONS (WITHOUT LOAD)……………………

SETTLING TIME SIMULATIONS AND CALCULATIONS (WITH LOAD)……………………

SETTLING TIME SIMULATIONS AND CALCULATIONS (WITHOUT LOAD)……………..

INPUT OFFSET VOLTAGE SIMULATIONS AND CALCULATIONS (WITH LOAD)……...

INPUT OFFSET VOLTAGE SIMULATIONS AND CALCULATIONS (WITHOUT LOAD).



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OVERVIEW:

Single Stage Open Loop operational amplifier I designed previously is now tested for the followi

specifications for both its schematic and layout formats.

Figure 1A: Schematic made for creating symbol.



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SLEW RATE SIMULATIONS AND

CALCULATIONS (WITH LOAD)

SLEW RATE CALCULATION WITH SCHEMATIC OF OPEN LOOP

SINGLE STAGE OP AM

For the single stage open loop operational amplifier which I designed, I now calculate it’s slew rate

for both the schematic and the layout. Following is the test bench I made to work out the slew rat

Figure 2: Test Bench for measuring the slew rate.



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RESULTS:

FIGURE 3

Description:

Slew rate measures the rate at which output of system changes with respect to input. It actually is

the slope of the output curve as it rises from it’s 10% of final value to 90%.

Slope can be given by the following mathematical formulae:

m=(y2 – y1)/(x2 – x1).

In figure 3 point A is (y2,x2)= (1.95,669nano). Similarly point B represents (y1,x1)=(210mili,51nano).

being voltage and x being time.

Plugging these values in the aforementioned formulae slew rate turns out to be 2.815V/mic

second. Ideally the slew rate should be as high as possible.



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SLEW RATE CALCULATION WITH LAYOUT OF OPEN LOOP SINGLE

STAGE OP AM

RESULTS:

Figure 4

Description:

In figure 4 point A is (y2, x2) = (1.786,351 nano. Similarly point B represents (y1, x1)

=(264mili,28nano). Y being voltage and x being time.

Plugging these values in the aforementioned formulae slew rate turns out to be 4.70V/micro

second. Ideally the slew rate should be as high as possible. This rate is a little slower than the slew

rate with schematic, possibly because the layout I made is not fully optimized in terms of

connections and wiring. See figure 1B.



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SLEW RATE SIMULATIONS AND

CALCULATIONS (WITHOUT LOAD)

SLEW RATE CALCULATION WITH SCHEMATIC OF OPEN LOOP

SINGLE STAGE OP AMP

RESULTS:

Figure 5

Description:

In figure 5 point A is (y2,x2)= (2.073,965pico). Similarly point B represents (y1,x1)=(118mili,646pico)


Plugging these values in the aforementioned formulae slew rate turns out to be 6.13V/ nano

seconds or 6130V/micro second. Ideally the slew rate should be as high as possible.

Since these calculations are for a single stage amplifier the value is close to ideal.



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SLEW RATE CALCULATION WITH LAYOUT OF OPEN LOOP SINGLE

STAGE OP AMP

RESULTS

Figure 6

Description:

In figure 12 point A is (y2,x2)= (1.8,975pico). Similarly point B represents (y1,x1)=(494mili,685pico).


Plugging these values in the aforementioned formulae slew rate turns out to be 4.53/ nano

seconds or 4530V/micro second. Ideally the slew rate should be as high as possible. Sin

these calculations are for a single stage amplifier the value is close to ideal.



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SETTLING TIME SIMULATIONS AND

CALCULATIONS (WITH LOAD)

SETTLING TIME CALCULATION WITH SCHEMATIC OF OPEN LOOP

SINGLE STAGE OP AMRESULTS:

The settling time is the time required to settle the output within a given range of the final value.

With a few minor modifications in the above test bench following results were obtained.

Figure 7

Description:

The output of the op amp with a pulsed input rises to its maximum value with at the maximum of

1micro second.



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SETTLING TIME CALCULATION WITH LAYOUT OF OPEN LOOP

SINGLE STAGE OP AM

RESULTS:

Figure 8

Description:


0.6micro seconds when checked for layout. Ideally the settling time should be as small as

possible. System stability plays an important role in reducing the settling time, more stable system

have less settling time.



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SETTLING TIME SIMULATIONS AND

CALCULATIONS (WITHOUT LOAD)

SETTLING TIME CALCULATION WITH SCHEMATIC OF OPEN LOOP

SINGLE STAGE OP AM

RESULTS:

Figure 9

Description:


1.45 nano seconds. This is very small as compared to with load configuration.



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SETTLING TIME CALCULATION WITH LAYOUT OF OPEN LOOP

SINGLE STAGE OP AM

RESULTS:

Figure 10

Description:


1.273 nano seconds.



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Dependence of settling time

Settling time of any electronic system depends on how stable the system is and stability is related

phase margin. Phase Margin is given by the following formulae:

Phase Margin = (180 degree – phase at unity gain frequency).

With the op amp under discussion the phase at unity gain was -110 degrees:

Figure 11

So the phase margin turns out to be 70 degrees.

“With a 30-degree phase margin, the circuit is likely to ring for a few cycles before reaching t

final point. (Also, component variations may lower the actual phase margin.) A phase margin

90 degrees is generally over-damped (takes too long to reach the set point). Phase margins

45 to 75 degrees often provide a snappy response without much ringing.”

Source: http://www.eetimes.com/electronics-news/4169957/Tips-on-enhancing-the-stability-of-op-amp-circu

This means the single stage op amp I am talking about has a good steady state response.

http://www.eetimes.com/electronics-news/4169957/Tips-on-enhancing-the-stability-of-op-amp-circuits





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INPUT OFFSET VOLTAGE SIMULATIONS

AND CALCULATIONS (WITH LOAD)

The test bench used with load to calculate input offset voltage is:

Figure 12

Load cap= 500p

Load res=100K

CALCULATING INPUT OFFSET VOLTAGE:

Here R3(10K) serves as the feed back resistance which is shorted to ground with R2(1K). Similarly tother input terminal is also shorted to ground with parallel resistive network.

In the above schematic Vout=(1+(R3/R2))*Voffset

Voffset = Vout/1001



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INPUT OFFSET VOLTAGE CALCULATION WITH SCHEMATIC OF OPE

LOOP SINGLE STAGE OP AM

RESULTS:

Figure 13

Description:

The output voltage turns out to be 74nV which when plugged into the above formulae yields V offse

be 74pico Volts.



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INPUT OFFSET VOLTAGE CALCULATION WITH LAYOUT OF OPEN


RESULTS:

Figure 14

Description:

With Vout

=61nV, Voffset

=

61 pico Volts



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INPUT OFFSET VOLTAGE SIMULATIONS

AND CALCULATIONS (WITHOUT LOAD)

INPUT OFFSET VOLTAGE CALCULATION WITH SCHEMATIC OF OPE


Figure 15: test bench for measuring input offset voltage without load

Results:

Now calculating Vout results in the following:



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Figure 16

Description:

With 86nano Volt at the output, Voffset turns out to be 86 pico Volts. It means if we apply thi

much voltage at the input the output should be zero



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INPUT OFFSET VOLTAGE CALCULATION WITH LAYOUT OF OPEN


Results:

Figure 17

Description:

Using 67 nano Volt as output voltage in above formulae the input offset voltage turns out to be 7

pico Volts.

op amp characteristics

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