90 db, 90 mhz, 30 mw cmos ota for a high capacitive load

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)

90 dB, 90 MHz, 30 mW CMOS OTA FOR A HIGH CAPACITIVE LOADs

MARKUS HELFENSTEIN1,*, QIUTING HUANG2 AND GEORGE S. MOSCHYTZ1

1Signal and Information Processing Laboratory, Swiss Federal Institute of Technology Zurich, ETH Zentrum,Zurich CH-8092, Switzerland

2Integrated Systems Laboratory, Swiss Federal Institute of Technology Zurich, ETH Zentrum, Zurich CH-8092, Switzerland

SUMMARY

The design of simple gain-enhancement con"gurations for cascode transistors is presented. Applying one- or two-stagedi!erential ampli"ers or an improved regulated cascode con"guration in the feedback loop of a cascode, allowshigh-speed and high-gain super-transistors at low voltage to be designed. These concepts were implemented ina symmetrical OTA resulting in a measured 90 dB, 90 MHz, 30 mW ampli"er performance for a 14 pF load. Settlingmeasurements to 0)1% error for a unity-gain con"guration are presented. Copyright ( 1999 John Wiley & Sons, Ltd.

KEY WORDS: cascode transistors; CMOS; OTA

1. INTRODUCTION

Improvements in CMOS technology, operating at ever-increasing frequencies and lower supply voltages, andthe scaling down of the minimum size of transistors tend to reduce the available voltage swing of analoguecircuits. One way of overcoming this problem is to use low threshold technologies, another is to "ndimproved and simple circuit techniques permitting the dynamic range of analogue circuits to be increased.The latter will be the subject of this paper.

Trends towards high-speed, high-dynamic range and low-voltage applications on the one hand, andaccuracy, high DC-gain and low power consumption on the other, lead to con#icting requirements. InCMOS circuits, high speed at a small supply voltage usually necessitates short channels at high currents,which in turn require wide devices for a good dynamic range, while high accuracy and high gain with lowpower consumption demand long and wide channels. Cascoding transistor is a well-known technique toimprove the gain of a single transistor by the intrinsic gain of the cascode transistor (g

m2r$s2

in Figure 1(a)).However, stacking transistors in series has the drawback of losing voltage swing and is limited by parasiticpaths, such as the resistance of the substrate leakage.1 Our proposed gain-enhancement circuits enabletransistors at minimum channel length to be used, thereby largely avoiding the DC-gain/bandwidth con#ict.

Although many elaborate and complex circuits using gain-enhancement techniques have been discussed inrecent papers,3,4 and the basic concepts go back at least as far as 1979,5 there has been no mention ofgain-enhancement circuits in widely used op amp implementations. The complexity of the implementationsproposed in recent literature has varied widely. The regulated cascode or &RGC' (Figure 1(b)),6 involving onlyfour transistors, is the simplest one, and the super-MOST4 is the most complex, not only in terms oftransistor count, but also in terms of design. The regulated cascode is the preferred structure and is widelyused where high output impedances are needed, such as in op amp or switched current (SI)7 circuits. It needs

*Correspondence to: Markus Helfenstein, Signal and Information Processing Laboratory, Swiss Federal Institute of TechnologyZurich, ETH Zentrum, Zurich CH-8092, SwitzerlandsPart of this work has previously appeared in Reference 2.

Contract/grant sponsor: KFW Jessi Project.Contract/grant number: 23021 Eureka EU 127.

CCC 0098}9886/99/050473}11$17.50 Received 22 October 1996Copyright ( 1999 John Wiley & Sons, Ltd. Revised 9 November 1998

Figure 1. Gain enhancement techniques for CMOS transistors: (a) cascode with di!erential feedback ampli"er, (b) regulated cascode,(c) regulated cascode with improved minimum output voltage

only the feedback loop implemented by M2

and M3

and a current source formed by M4. Because it entails

a voltage-swing loss of at least one threshold and one saturation voltage, the designs for high swing cascodesusing the RGC are necessarily bounded. Applying the RGC to SI circuits leads to design formulas that aredi$cult to satisfy (Reference 7, Chapter 6) and, in low-voltage designs, limits the allowable signal range dueto the minimum output voltage of the stacked transistors. The super-MOST, on the other hand, o!ers veryhigh-output impedances, low minimum output voltage, and wide bandwidth operation, but at the penalty ofcomplicated design.

In this paper we examine, in terms of complexity, level-shifting, input common-mode, and frequencyrequirements, some simple ampli"er structures with respect to their suitability in a gain-boosting feedback-loop. These include an improved version of the regulated cascode, a single-stage OTA, and a Miller ampli"er.We present experimental results of two high gain, wide bandwidth, and low-power OTAs for a highcapacitive load using gain-enhancement techniques. The methods used to measure these ampli"ers will alsobe discussed.

2. SIMPLE GAIN-ENHANCEMENT STAGES

The basic and well-known idea of the gain-enhancement technique is shown in Figure 1(a). Using a localfeedback network to stabilize the drain-source voltage of the main transistor (M

1in Figure 1) the additional

gain fb is approximately the gain of the feedback loop. As shown in Reference 3 the output resistance ofa cascoded transistor can be calculated as

r065

"r2#r

1(1#g

m2r2(1#fb)) (1)

where riis the small signal output resistance and g

mithe transconductance of transistor M

i(i"1, 2). The

additional term (1#fb) is the gain-boosting factor due to the local feedback loop. Using high fb, transistorswhose e!ective output characteristics are very #at can be produced.

An often used implementation of the feedback circuit is the regulated cascode. Using the RGC, <3%&

has tobe at least larger than one threshold voltage. Thus, the minimum allowable output voltage to keep alltransistors in saturation can be a limiting factor in low-voltage designs. In Reference 8 a gain-boosting stageconsisting of cascoded transistors has been designed. Although very untroublesome in terms of design andtransistor count, the minimum output voltage is equally large than in the RGC case. Utilizing only few moretransistors, the regulated cascode can be redesigned with a lower minimum output voltage (Figure 1(c),Reference 9). In Figure 2, the feedback circuits are simple di!erential-input one- or two-stage ampli"ers withhigh gain. Compared to the circuits in References 3 and 4, where either a folded cascode or a super-MOST

474 M. HELFENSTEIN, Q. HUANG AND G. S. MOSCHYTZ

Copyright ( 1999 John Wiley & Sons, Ltd. Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)

Figure 2. Simple feedback ampli"ers: (a) CMOS one-stage ampli"er, (b) two-stage Miller ampli"er

structure was used, the proposed designs are either more power e$cient or more straightforward, due to theabsence of additional local loops in the feedback ampli"er.

In what follows, we will examine the output level-shifting, the common-mode range, and the frequencyrequirements of the improved version of the regulated cascode and of two simple classical di!erentialfeedback structures.

2.1. Output level-shifting and input common-mode requirements

For low-voltage battery operation and maximum swing requirements, the RGC can be altered bychanging the n-channel transistor M

3of the RGC-structure into a p-channel device which is M

7(Figure 1(c)).

An additional current mirror and an output stage feeds the input signal back to the cascode transistor. Bychoosing the appropriate reference voltage <

3%&the drain-source voltage <

$s1can now be as low as one

saturation voltage. Thus <3%&

sums up to

<3%&"<

$4!51#<

'47(2)

In theory M6

can even be diode-connected but at the penalty of a worse common-mode rejection ratio. Theoutput voltage of the improved RGC becomes <

$41#<

$4!52, where <

$41can be as small as the saturation

voltage of the main transistor M1

in Figure 1(c).Using a one-stage di!erential input ampli"er in the local feedback path (Figure 2(a)), the bias-source

implemented with M8

calls for careful design. Generally, the reference voltage <3%&

has to be slightly largerthan the saturation voltage of the main transistor M

1. To maintain all transistors in saturation, (3) and (4)

have to hold.

D<$4!53

D)<3%&#<

'42"<

3%&#<

$4!52#<

5)2(3)

<$4!58

)<3%&#<

$4!52!D<

$4!53D#<

5)2!D<

5)3D (4)

Equation (3) can be readily ful"lled. For transistor M8, it is not di$cult to satisfy (4) even for low reference

voltages. Owing to the di!erences between n- and p-threshold voltages, the minimum saturation voltage forthe p-super-transistor is slightly larger than for its n-equivalent.

Referring to Figure 2(b), where a two-stage ampli"er (with Miller compensation) is shown, the inputcommon-mode range of the PMOS di!erential pair is limited on the ground terminal side by the saturationvoltage of M

6. For correct operation (5) has to hold, namely:

D<$46

D"<$41

#D<'46

D!<'48

*D<$4!56

D (5)

90 dB, 90 MHz, 30 mW CMOS OTA FOR A HIGH CAPACITIVE LOAD 475


Table I. Comparison of MOS super transistors

MOS super Feedback factors fb Dominant pole u$

of the <065.*/

Additionaltransistor feedback circuit transistors, bias

Simple * * <$44!51

0

Cascode 0g$4,.!*/C

'4, #!4

<$44!51

#<$44!52

1 FET

1 bias

Regulatedcascode(RGC)

gm3

r3

g$43

#g$44

C$43

#C-0!$

<5)1

#<$44!52

3 FETs

1 bias

Modi"edRGC

r3gm4

(gm3

#gm5

)

gm6

gm7

(gm6

#gm7

)

gm5

C'44

#C'45

<$44!51

#<$44!52

6 FETs

2 bias

Cascode withfeedback OTA,Figure 2(a)

gm7

(g$47

#2g$48

)

g$47

#2g$48

2Cc

<3%&#<

$44!52<3%&'<

$44!51

7 FETs

2 bias

Cascode withtwo-stage feed-back OTA,Figure 2(b)

gm7

(g$49

#g$47

)

gm3

(g$43

#g$44

)

(g$47

#g$49

) (g$43

#g$44

)

gm3

Cc

<3%&#<

$44!52<3%&'<

$44!51

8 FETs

2 bias

Cascode withfolded cascode3

g., */g065

g., #!4 065

C'4, #!4 065

<3%&#<

$44!52<3%&'<

$44!51

10 FETs

4 bias

On the other hand, <$41

*<$4!51

in order for M1

to stay in saturation. This leads to (6) as a design constraintfor M

6to stay in saturation, which is not di$cult to meet

<$4!51

#D<'46

D*<'48

#D<$4!56

D (6)

The output of the ampli"er in Figure 1(a) is required to bias the gate of M2, which is above ground, by

<$4!51

#<'42

. Neither the modi"ed regulated cascode circuit in Figure 1(b) nor the two di!erential feedbackampli"ers in Figure 2 have any di$culty providing the level shifting from the input to the output. Thecommon-mode range of both types of di!erential input stage ampli"ers is suitable for the gain-enhancingapplication.

Table I gives an overview of di!erent, relatively simple, feedback circuits with their gain-boosting factorsfb (1), the dominant pole u

$, the minimum possible output voltage <

065.*/and the complexity of the addi-

tional circuit in terms of transistor count and additional bias lines. As can be seen, the improved RGCo!ers medium feedback factors at low complexity, whereas the two-stage ampli"er gives very high gainwith medium design overhead. Apart from the RGC, all proposed structures can be designed at mini-mum output voltages, close to <

$4!51#<

$4!52, which makes them ideally suited for a modern low-

voltage process that operates on a single 3)3 V supply voltage. Especially in switched current circuits, where,for high-speed and low-voltage applications high gain is needed without restricting output swing, thesesimple feedback ampli"ers improve the dynamic range considerably when compared to, for example,a regulated cascode circuit. The basic design calculation is simpli"ed as well. Using the circuit proposed inFigure 1(c) a switched current bandpass "lter operating on a single 3 V supply voltage was presented inReference 10. Utilizing cascoded transistors with local feedback circuits for the memory transistor and for the



Figure 3. Output characteristics of di!erent super-transistors: simple transistor, normal cascode, regulated cascode, modi"ed regulatedcascode, cascode with one-stage feedback ampli"er, cascode with Miller feedback ampli"er

bias cell, it is possible to maintain accuracy in switched current designs with battery voltages as low as twothreshold voltages <

5).

The circuits shown in Figures 1 and 2 have been simulated with HSPICE, using the 1 lm SACMOSprocess11 and the transistor models BSIM2. Figure 3 shows the output characteristics for several super-transistors using cascodes with feedback loops. The saturation current for all con"gurations is in themA-range as needed in the OTA-implementation discussed below. To minimize<

$4!5and to maximize speed,

the size for both transistors M1

and M2

was chosen to be 300 lm by 1 lm. As can be seen in Figure 4, forboth the modi"ed regulated cascode and the cascode with the one-stage feedback ampli"er, the outputresistance of the circuits starts to increase drastically for a <

$4round 0)5 V. Due to the relatively large

threshold voltages of the SACMOS process (<5)/

"0)7 V, <5)1

"!0)8 V), the regulated cascode starts tooperate properly only at 0)9 V resulting in a dynamic range loss of about 1 V for an n- and p-type cell. Thus,the proposed feedback structures enhance dynamic range signi"cantly.

2.2. Requirements for fast settling

The e!ects of a closely spaced pole-zero doublet due to a feedback loop have been studied extensively inReferences 4 and 12. It is known that doublets can degrade the settling performance of an amplifying elementdrastically while causing only minor changes in the frequency behaviour in the local feedback circuit. Inorder to achieve the required phase margin, the unity-gain bandwidth of the additional gain stage must belower than the second pole by a factor two. However, because the doublet is present near the unity-gain



Figure 4. Output resistance of di!erent super-transistors: normal cascode, modi"ed regulated cascode, cascode with one-stage feedbackampli"er, cascode with Miller feedback ampli"er

Figure 5. Symmetrical CMOS OTA using gain-enhancement techniques and output bu!er



bandwidth of the gain-enhancement stage, the unity-gain bandwidth of the main ampli"er must, in fact, belower than the second pole by a factor substantially greater than two. This can easily be ful"lled because theload capacitor of the additional ampli"er, which determines the unity-gain bandwidth of the gain-enhance-ment stage, is much smaller than the load capacitor of the output stage of the OTA, which determines theunity-gain bandwidth of the main ampli"er.

Figure 6. Die photograph of the op amp with two-stage Miller OTAs as gain enhancing ampli"ers

Figure 7. Measured open-loop gain characteristic for OTA-1 (lower trace) and for OTA-2 (upper trace)



3. OTA-IMPLEMENTATION AND MEASUREMENTS

In this section, the implementation, measurement methods, and results of two symmetrical CMOS OTAs,integrated on one chip, are discussed. The test chip was intended as a vehicle to study the concepts mentionedin Section 2. A simple design, in terms of implementation and analysis, for a high-gain, high-bandwidth, andlow power consuming OTA, even for high capacitive loads, was the objective. Furthermore, high slew rateand large output swing were also required.

The CMOS OTAs were implemented and tested using the 1 lm SACMOS process. We chose thesymmetrical OTA con"guration because of the high slew rate capabilities. All cascodes and the maincurrent source were realized with either simple one-stage, case (a), or two-stage ampli"ers, case (b)(Figures 2(a) and (b)). In order to maintain circuit symmetry, the proposed concepts were also appliedto the diode connected transistors in the current mirrors. Each OTA was integrated both in unity-gainand open-loop con"gurations. To measure the full output swing and settling behaviour under theunity-gain condition, a load capacitance of 14 pF was integrated, and a fast bu!er in a separate well wasused to decouple the high-impedance output of the OTA from the measurement setup. The circuit, withthe length and width of the main transistors given, is shown in Figure 5, and the die photograph inFigure 6.

Measuring high gain with good resolution and having circuits with large bandwidth usually leads tocontradictory requirements. Thus, the basic idea is to split the transfer function into three parts in order todecouple high-gain and high-frequency measurement problems. To perform DC or very low-frequencymeasurements, we used a method proposed by Analog Devices,13 where the device under test (DUT)operates in a simple loop together with an integrator. To measure the "rst pole of the OTA, we used the

Figure 8. Measured open-loop phase characteristic of OTA-1 (upper trace) and for OTA-2 (lower trace)



method proposed in Reference 14. The OTA operates as an inverting ampli"er and bu!ers reduce thein#uence of the output impedance of the OTA and of the measurement setup. Additional calibrationmeasurements are needed for compensation purposes. The unity-gain bandwidth measurement of theinverting ampli"er con"guration delivered the same results as extrapolating the curve of the unity-gaincon"guration around 0 dB. The DC-gain of (a) and (b) was measured to be 80 and 90 dB, respectively.This is close to the results obtained by simulations and calculations using the feedback factors given inTable I where the gain was larger by 10 and 12%, respectively. Both OTAs have a unity-gain frequencyof 92 MHz (110 MHz in simulations). The plots are shown in Figures 7 and 8. The phase margin forboth circuits was measured to be 553 (623 in simulations). The di!erences between simulations andmeasurements compare well with the ones given in Reference 8 and are explainable due to di$culties inthe modelling of the transistors' transition region and in the sensitivity of the circuit with respect to the biascurrent.

For slew rate measurements, the DUT operates in a unity-gain con"guration. To compensate for the levelshifter at the output and to subtract the input step from the circuit response, some additional circuitry had tobe built. To achieve high resolution and to have fast settling of the o!-chip components, the AD811 highperformance video ampli"er was chosen for measurement purposes. In doing so, the appropriate feedbackresistors had to be chosen to trade o! between fast settling time with overshoots and slow but accuratesettling.

Figure 9 shows the settling performance for a feedback factor of 1, case (b), by applying a step *<i"1 V at

the input. The measured settling time for a 0)1% tolerance at the output is 40)8 ns which corresponds to an

Figure 9. Measured settling results for OTA-2. The output signal (upper trace) and the error signal (lower trace) with *<*/"1 V



Figure 10. Measured settling results for OTA-2. The output signal (upper trace) and the error signal (lower trace) with *<*/"4 V

Table II. Measured OTA performance

OTA-1, (a) OTA-2, (b)

DC-gain 80 dB 90 dBUnity-gain frequency 92 MHz 92 MHzLoad capacitance 14 pF 14 pFPhase margin '553 '553CMRR 70 dB at DC 70 dB at DCSettling to 0.1% 41 ns for *<

*/"1 V 40)8 ns for *<

*/"1 V

Power supply $2)5 V $2)5 VPower dissipation 24 mW 29 mWOutput swing $2)1 V $2)1 V

error of 1 mV. In Figure 10, *<iis 4 V, causing normal slewing behaviour and showing a large output swing.

The main measured characteristics are summarized in Table II.

4. CONCLUSIONS

Moving towards high-frequency and low-voltage applications will cause circuits based on standard designtechniques, such as switched capacitors and switched currents, to su!er due to reduced dynamic range.



Handling large currents and high-output impedances at low-output voltages requires new design strategiesand gives rise to one of the key problems in analogue design. This is the reason for our investigation ofgain-boosting techniques with medium area overheads.

It has been shown that by using simple one- and two-stage feedback ampli"ers for the gain-enhancementtechnique, the design of a super-MOST can be simpli"ed considerably. Several feedback con"gurations havebeen examined and were shown to be useful especially in applications requiring high dynamic range atlow-battery voltage. Even at currents in the mA-range, a high-output resistance at a low-saturation voltage isachievable.

With this technique, a symmetrical OTA was realized using the 1 lm SACMOS process. For the two-stagegain-enhancement implementation, a DC-gain of 90 dB with a unity-gain frequency of 92 MHz with a14 pFload was measured. Fast settling behaviour and an output swing of $2)1 V with an increase in chip area ofonly 25% were achieved. The power dissipation for both OTA and biasing networks was only 30 mW, ofwhich 15% comprised of overheads for the boosting ampli"ers.

ACKNOWLEDGEMENTS

This work was "nancially supported by the KWF Jessi-Project, 2302. 1. Eureka EU 127.

REFERENCES

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90 db, 90 mhz, 30 mw cmos ota for a high capacitive load

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