a 600ms/s 30mw 0.13µm cmos adc array achieving over 60db sfdr with adaptive digital equalization
DESCRIPTION
A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving over 60dB SFDR with Adaptive Digital Equalization. Time-interleaved ADC array High sampling rate, low power Channel mismatch errors Offset, gain, linearity and skew Approaches Correlation, statistics, and Chopping - PowerPoint PPT PresentationTRANSCRIPT
A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving over 60dB SFDR with
Adaptive Digital Equalization
• Time-interleaved ADC array– High sampling rate, low power – Channel mismatch errors
• Offset, gain, linearity and skew
• Approaches– Correlation, statistics, and Chopping
• Slow convergence, involved analog path, ad-hoc solutions
– Equalization• Fast convergence, digital post-processing, systematic
solution
Equalization-Based Conversion Architecture
C0C1CN-1
SAR Logic
-VR
d0d1dN-1
D+VR
X
C0
Vin
Q Vos
N-1
jinjin os
j=0R tot
CV2d -1D = = +D +QN
V C
Channel mismatch errorsautomatically eliminated w/equalization !
ADC1
T/H
Ref.ADC
ADC10
ADF1
ADF10
D1
DLL
Ф1(60MHz)Vin
...
1X
1X
D10
Dr
Ф10(60MHz)
Ф1
Ф10
Фr(599.4KHz)
Ф (600MHz)
Analog Chip
Software
0 100 200 300 400 500 600 700 80020
30
40
50
60
70
input frequency [MHz]
SN
DR
/ S
FD
R [dB
]
SNDR w/o calibrationSNDR w/ calibrationSFDR w/o calibrationSFDR w/ calibration
Performance Summary
fs = 600 MS/s, Ain = 0.9 FS
Process(µm)
fs(MS/s)
SFDR(dB)
SNDR(dB)
Power(mW)
FOM(pJ)
Ours 0.130 600 65.2 47.3 23.6 0.21ISSCC 06 0.130 600 43 33.1 5.3 0.22ISSCC 08 0.065 250 48 28 1.2 0.24VLSI 08 0.065 800 58 47.8 30 0.28
ADC1-10
THAs
REF ADC
REF CLK
BIAS
DLL
1.1 mm
1.0 mm