a d m for cmos radio frequency integrated circuits

ADVANCED DOWNCONVERSION MIXERS

FOR CMOS RADIO FREQUENCY INTEGRATED CIRCUITS

by

HAO LI

A thesis submitted to the

Department of Electrical and Computer Engineering

in conformity with the requirements for

the degree of Doctor of Philosophy

Queen’s University

Kingston, Ontario, Canada

December 2017

Copyright c© Hao Li, 2017

Abstract

This thesis explores the design of advanced downconversion mixers in CMOS RF inte-

grated circuits. First, a novel switched transconductor mixer with low power, low noise

and ultra-wide bandwidth is proposed. The transconductor stage with fixed DC operating

point is switched by the ac-coupled local oscillator (LO) signal to realize the mixing, so

that a decade bandwidth is achieved with power-efficient LO buffer. The proposed mixer

topology is investigated thoroughly with its bandwidth analysis, design process and a per-

formance comparison to the traditional switched transconductor mixer is provided. The

measurement results of the mixer demonstrate a 15.5 – 17.5 dB gain and a 4 –5.2 dB noise

figure over 1 – 10 GHz, and the power consumption is only 8.3 mW from a 1.2 V supply.

Since a wideband mixer usually requires exceptional linearity to resist large in/out-of-

band blockers, a novel feedforward linearization technique for active mixer is presented. As

it generates the low-frequency IM3 for the cancellation fully in the IF band, the technique

can bring third-order input intercept point (IIP3) of the mixer that is robust against parasitic

parameters and process variations. Furthermore, this method can be applied to any active

mixers regardless of its circuit topology. The measurement results of a Gilbert cell mixer

with this method applied has shown a 12.5 dB IIP3 improvement at cost of 4-mA current

from 1.2 V supply. The adoption of this method does not introduce noticeable noise and

gain degradation to the mixer.

i

Last, but not the least, a low-power, wideband, Gilbert-cell-based mixer with an on-

chip balun is also presented. The mixer adopts a folded structure with its transconductor

and the switching stages coupled with an on-chip, multifilament-transformer-based balun.

With this balun integrated, the single-ended-to-differential conversion is realized within

the mixer block. For the first time, the double tuned resonator is utilized to expand the

bandwidth of the mixer. The measurement results demonstrate a gain of 13.5 dB over 4

to 10 GHz, with amplitude and phase imbalances limited to only 0.9 dB and ±2 over the

whole band.

ii

Acknowledgments

There are many people that I would like to thank for their generous support and encourage-

ment throughout my Ph.D. studies. First, I would like to thank my supervisor, Dr. Carlos

E. Saavedra, for his guidance over the past five years. He has continually provided me

with advice, encouragement and the opportunities to improve my research and engineering

skills.

I would like to thank several people for their generous assistance with my research-

related problems. First, and foremost I would like to thank Ahmed El-Gabaly for his

never-ending willingness to give his time to discuss with me about the circuit design and

measurement. Much assistance and a lot of useful discussions regarding the designs in this

thesis were also provided by Xiao Yang.

The chip design, fabrication and measurement cannot be accomplished without the sup-

port provided by CMC and Queen’s ECE technician group. I would specifically like to

thank Greg Mcleod for perpetually fixing our server problem in a prompt manner. Further-

more, many of the measurements performed in this thesis made use of Dr. Brian Frank and

Dr. John Cartledge’s equipment that they generously shared.

Thanks are also given to my friends and labmates, Justin Po, Jeremy Ng, Jonathan John-

stone, Wen Li, Fan Jiang, Jeet Mondal, David Stewart, Mahdi Mohsenpour, Sean Whitehall,

Arcesio Arbelaez, Yinfei Meng, Lin Wang and many other guys for their accompanies and

iii

kindly support during my studies.

In the end, I would like to thank my wife, Yang Liu, and my parents for their support.

Yang quit her job in China and came to Canada with me five years ago. Starting all from a

scratch, she picked up English, finished a college program with highest GPA in the class,

then worked hard to take on most of the family duties. She said she tried so hard because

she did not want to distract me from school with her things. Actually she is the strongest

motivation for me. My parents, although without much words, showed their deep love to

me through their tremendous patience and understanding. They have also been a constant

source of motivation for me to complete this degree, and for that I will always be grateful.

iv

Contents

Abstract i

Acknowledgments iii

Contents v

List of Tables vii

List of Figures viii

List of Abbreviations xiii

Chapter 1: Introduction 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Challenges in CMOS RFIC . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.4 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 2: Literature review 92.1 Mixer Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2 Mixer Circuits Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.1 Passive Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2.2 Active Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3 Gilbert Cell Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.4 Low Noise Mixer Review . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.4.1 Flicker Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . 362.4.2 White Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . 38

2.5 Linear Mixer Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.6 Wideband Mixer Review . . . . . . . . . . . . . . . . . . . . . . . . . . . 442.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Chapter 3: A Low-Power, Low-Noise, Decade-Bandwidth Mixer 49

v

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493.2 Proposed Method to Increase the Bandwidth of the STM . . . . . . . . . . 51

3.2.1 Bandwidth considerations in the baseline STM . . . . . . . . . . . 513.2.2 The proposed MSTM concept . . . . . . . . . . . . . . . . . . . . 543.2.3 Simulation verification . . . . . . . . . . . . . . . . . . . . . . . . 59

3.3 IC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663.3.1 Input inductive peaking . . . . . . . . . . . . . . . . . . . . . . . . 673.3.2 Quantitative analysis and simulation results . . . . . . . . . . . . . 693.3.3 IF buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Chapter 4: A Highly Linear Gilbert Cell Mixer 844.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844.2 Proposed Linearization Technique . . . . . . . . . . . . . . . . . . . . . . 86

4.2.1 Proposed Feedforward Linearization . . . . . . . . . . . . . . . . . 884.2.2 Discussions on cancellation condition . . . . . . . . . . . . . . . . 924.2.3 Effects on Gain and IIP5 . . . . . . . . . . . . . . . . . . . . . . . 93

4.3 Key Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954.3.1 IM2 Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964.3.2 Baseband Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . 994.3.3 Signal Combiner . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.4 Chip Design Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044.4.1 Mixer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044.4.2 Linearization Path Design . . . . . . . . . . . . . . . . . . . . . . 1064.4.3 Simulated IIP3 Improvement on PVT Variation . . . . . . . . . . . 112

4.5 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Chapter 5: A Wideband Transformer-Coupled Mixer 1215.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215.2 Mixer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Chapter 6: Summary and Conclusions 1346.1 Thesis Summary and Contributions . . . . . . . . . . . . . . . . . . . . . . 1346.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Bibliography 138

vi

List of Tables

2.1 Output components of three types of mixers . . . . . . . . . . . . . . . . . 15

2.2 Nonlinearity sources and linearization techniques . . . . . . . . . . . . . . 41

3.1 Overview of the Simulation Parameters Used for STM and MSTM mixers

of Fig. 3.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.2 Simulated performance of the STM and MSTM mixers of Fig. 3.4 for a

fixed IF = 250 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.3 Component Values for the IF Buffer . . . . . . . . . . . . . . . . . . . . . 74

3.4 Selected Simulation Results for Mixer Core & IF Buffer . . . . . . . . . . . 75

3.5 Summary of the mixer’s performance in comparison with other work . . . . 82

4.1 IIP3 Improvement versus Process Corners . . . . . . . . . . . . . . . . . . 113

4.2 IIP3 Improvement versus Temperature . . . . . . . . . . . . . . . . . . . . 114

4.3 Performance Summary and Comparison Table . . . . . . . . . . . . . . . . 119

5.1 Specifications with different feedback resistors . . . . . . . . . . . . . . . . 128

5.2 Performance comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

vii

List of Figures

2.1 Spurious response: frequency translation by ωLO, its third and fifth harmonics. 13

2.2 (a) Unbalanced, (b) Single-balanced, (c) Double-balanced mixer imple-

mented with switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Diode mixers in (a) unbalanced, (b) single-balanced and (c) double-balanced

structure [9] with permission c©2006 IEEE. . . . . . . . . . . . . . . . . . 16

2.4 A wideband receiver without RF filtering saturated by a large out-of-band

blocker [28] with permission c©2012 IEEE. . . . . . . . . . . . . . . . . . 19

2.5 Receiver architecture: LNTA, passive mixer, transimpedance filter [29]

with permission c©2013 IEEE. . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6 25% duty cycle LO waveforms at mixer gates (single-ended) [21] with per-

mission c©2009 IEEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.7 N-path filtering in the passive mixer-based receiver architecture: (a) Re-

ceiver topology (b) N-path filtering [28] with permission c©2012 IEEE. . . 21

2.8 Circuit schematic of the resistive FET ring mixer (double-balanced mixer)

[31] with permission c©2012 IEEE. . . . . . . . . . . . . . . . . . . . . . . 22

2.9 Single FET mixers: (a) gate-pumped and (b) drain-pumped. . . . . . . . . . 24

2.10 Current steering mixer: (a) circuit schematic and (b) mixer operation. . . . . 25

2.11 Gilbert cell mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

viii

2.12 Waveform of VLO(t), sgn(VLO(t)) and p(t) from [36] with permission c©2000

IEEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.13 Single-balanced mixer with switch noise referred to the gate from [38] with

permission c©2000 IEEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.14 Mixer output current with noise: (a) ideal output current and noise impulse

and (b) impulse sampling train and flicker noise from [38] with permission

c©2000 IEEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.15 Frequency translation of white noise originating in RF input transconductor

from [38] with permission c©2000 IEEE. . . . . . . . . . . . . . . . . . . . 32

2.16 Gilbert cell mixer with current bleeding. . . . . . . . . . . . . . . . . . . . 38

2.17 Low noise current bleeding mixers with (a) source degeneration transcon-

ductor from [47] with permission c©2011 IEEE and (b) common gate tran-

conductor from [48] with permission c©2010 IEEE. . . . . . . . . . . . . . 39

2.18 General adaptive feedforward receiver concept [83] with permission c©2008

IEEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.19 UMTS receiver architecture with adaptive linearization in [83] with per-

mission c©2008 IEEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.20 Inductive peaking in Gilbert mixers (a) series (b) shunt. . . . . . . . . . . . 45

2.21 Wideband Gilbert mixer in (a) [87] with permission c©2009 IEEE and (b)

[88] with permission c©2014 IEEE. . . . . . . . . . . . . . . . . . . . . . . 46

3.1 Bandwidth study of the baseline STM: (a) schematic of the baseline STM

[95]; (b) schematic of the inverter-based LO buffer [95]; (c) waveform of

VA with the increase of LO frequency; (d) schematic of the “push-pull” LO

buffer [96]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

ix

3.2 Bandwidth analysis of the modified STM (MSTM) (a) schematic of the

MSTM; (b) waveforms of VA, current through the transconductors I1,2 and

their transconductance gm1,2. . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.3 Frequency response of the modified STM (a) with VA as an intermediate

variable; (b) direct relation between conversion gain and frequency. . . . . . 58

3.4 (a) Double-balanced modified switched transconductor mixer (MSTM). (b)

Double-balanced switched transconductor mixer (STM) with current-reuse

amplifiers as LO buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.5 Waveforms of VA and I1,2 with LO input power at -1 dBm (solid line) and

-13 dBm (dashed line) when LO frequency is (a) 1 GHz, (b) 10 GHz. . . . . 61

3.6 Output power of LO buffer and voltage conversion gain of the MSTM. . . . 62

3.7 Circuit schematic of the proposed mixer. . . . . . . . . . . . . . . . . . . . 67

3.8 Small signal half-circuit model of M1−4 with LG under test. . . . . . . . . . 68

3.9 Simulated gain and NF of the mixer core with and without LG. . . . . . . . 71

3.10 Circuit schematic of the proposed IF output buffer. . . . . . . . . . . . . . 73

3.11 Photograph of Broadband Mixer IC. . . . . . . . . . . . . . . . . . . . . . 75

3.12 Measured mixer performance over LO frequency: (a) gain and (b) NF . . . 77

3.13 Measured mixer gain (a) and NF (b) versus IF frequency at LO frequencies

of 4 GHz and 7 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.14 P1dB and IIP3 versus LO frequency. . . . . . . . . . . . . . . . . . . . . . . 79

3.15 Sensitivities of IIP3 to (a) IF frequency (b) two-tone spacing at LO frequen-

cies of 4 GHz and 7 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.16 Measured LO-to-RF isolation of the mixer. . . . . . . . . . . . . . . . . . . 81

x

4.1 Feedforward nonlinearity cancellation technique used (a) in the general

case (b) in the case of down-converters . . . . . . . . . . . . . . . . . . . . 87

4.2 The diagram of the proposed feedforward technique . . . . . . . . . . . . . 89

4.3 The spectrum at Node D with 5th order terms considered . . . . . . . . . . 94

4.4 Diagram of IM2 generator: (a) building block (b) circuit schematic . . . . . 96

4.5 Circuit schematic of the baseband multiplier . . . . . . . . . . . . . . . . . 100

4.6 Circuit schematic of the signal combiner . . . . . . . . . . . . . . . . . . . 101

4.7 The schematic of the op amp in combiner . . . . . . . . . . . . . . . . . . 102

4.8 Transfer function of the combiner illustrated in output spectrum, (a) for

two-tone test and (b) for the receiver where IF amplifier/filter is re-used . . 103

4.9 The circuit implementation of the proposed feedforward technique . . . . . 105

4.10 Simulated input and output signals of IM2 generator. . . . . . . . . . . . . 107

4.11 Simulated g2 versus VGS of M7 and M8 in Fig. 4.9. . . . . . . . . . . . . . . 108

4.12 Simulated phase shifts introduced by the IM2 Generator . . . . . . . . . . . 109

4.13 Simulated imbalance of the active balun in Fig. 4.9. . . . . . . . . . . . . . 110

4.14 Power of IM3 at multiplier output versus RF input of the chip . . . . . . . . 111

4.15 Simulated phase shifts introduced by the multiplier . . . . . . . . . . . . . 112

4.16 Die micrograph of the mixer . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.17 Measured and simulated IIP3 of the mixer. (Dashed curves are simulated

results) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.18 Output spectrum of the mixer (a) before and (b) after linearization . . . . . 117

4.19 IIP3 improvement versus two-tone spacing for the mixer . . . . . . . . . . . 118

5.1 Proposed broadband mixer configuration. . . . . . . . . . . . . . . . . . . 124

5.2 Stacked monolithic balun configurations. . . . . . . . . . . . . . . . . . . . 125

xi

5.3 Top and side views of the balun . . . . . . . . . . . . . . . . . . . . . . . . 125

5.4 Simplified balun circuit model of one branch. . . . . . . . . . . . . . . . . 126

5.5 Simulated frequency response with different Rf . . . . . . . . . . . . . . . . 127

5.6 Magnitude response of the balun’s circuit model with different Cf . . . . . . 128

5.7 The microphotograph of the chip. . . . . . . . . . . . . . . . . . . . . . . . 130

5.8 Conversion gain, reflection coefficient and noise figure. . . . . . . . . . . . 131

5.9 Simulated amplitude and phase imbalance. . . . . . . . . . . . . . . . . . . 131

xii

List of Abbreviations

CG-CS Common Gate-Common Source.

CMFB Common Mode Feedback.

CMOS Complementary Metal-Oxide Semiconductor.

CMRR Common Mode Rejection Ratio.

DS Derivative Superposition.

DSB Double Sideband.

FDD Frequency Division Duplexing.

FET Field-Effect Transistor.

GBW gain-bandwidth-product.

IF Intermediate Frequency.

IIP2 Input second-order intercept point.

IIP3 Input third-order intercept point.

IIP5 Input fifth-order intercept point.

IM2 Second-order intermodulation.

IM3 Third-order intermodulation.

LNA Low Noise Amplifier.

LNTA Low Noise Transconductance Amplifier.

LO Local Oscillator.

xiii

MMIC Monolithic Microwave Integrated Circuit.

MOSFET Metal-Oxide Semiconductor Field-Effect Transistor.

MSTM Modified Switched Transconductor Mixer.

NF Noise Figure.

P1dB 1-dB compression point.

PVT Process, Votlage, Temperature.

Q-factor Quality factor.

RF Radio Frequency.

RFIC Radio Frequency Integrated Circuit.

SAW Surface Acoustic Wave.

SoC System on Chip.

SOI Silicon On Insulator.

STM Switched Transconductor Mixer.

TIA Transimpedance Amplifier.

VGA Variable Gain Amplifier.

WCDMA Wideband Code Division Multiple Access.

WLAN Wireless Local Area Network.

xiv

1

Chapter 1

Introduction

1.1 Motivation

Growing demand for wireless hand-held devices with more functions, smaller sizes and

lower costs has been a significant driving force for research in radio frequency integrated

circuit (RFIC) over the past 15 years. As the number of communication bands increases

to provide more functionality and enable higher speeds, the bandwidth requirement of the

receivers inevitable increases.

With the bandwidth increase for multi-band support, the linearity requirement for re-

ceivers is progressively stringent. Unlike the narrowband design with tuned low noise am-

plifiers (LNAs), the wideband system amplifies both the wanted signal and any co-existing

radios present as blockers. Due to the nonlinearities of the system, intermodulations will

be generated out of these blockers and possibly lying upon the wanted signals. In order to

prevent these intermodulations from severely interfering with the wanted signals with large

strength, the receiver must be particularly linear. The off-chip surface acoustic wave (SAW)

filter (array) can be used at the front-end to suppress these blockers, so that the linearity

specification requirement is relaxed. However, this solution is not preferable because the

1.1. MOTIVATION 2

SAW filter can not be integrated on chip and thus hinders the increase for the integration

level of the system.

Besides the increasingly stringent demand on linearity, some longstanding performance

requirements also remain challenging as the bandwidth increases. For example, it is dif-

ficult to achieve low noise figure (NF) over the whole band up to 10 GHz, because the

impedance and noise match are deteriorated by the parasitic capacitors at high frequencies.

Although some wideband receivers with low NF are reported, they are mostly achieved at

the cost of high power consumption, which is not favored because it shortens the battery life

of the devices. Another example is the implementation of on-chip balun, which is widely

needed in receiver design due to the fact that most antennas and LNAs are single-ended

while the rest circuits are differential. While an external broadband balun can be used, it

usually occupies large area off-chip. In the effort to integrate the balun on the chip, the

issues of imbalance and huge losses still remain challenging, especially when it comes to

high frequency ranges.

To fulfill the relentless desire to increase the performance of wireless communication

systems, new circuit topologies need to be investigated that address the issues listed above.

This is the main motivation for the work in this dissertation. Among all the components

used in receiver chain, this dissertation predominantly focuses on the topology innovation

of an essential circuit, namely, the mixer, in order to meet the new requirements encoun-

tered in applications as described above.

As a fundamental circuit element in the receivers, a mixer is used to down-convert the

input signals from radio frequency (RF) to Intermediate frequency (IF) band in frequency

domain. In most cases, the mixer determines the receiver architecture and specifications

to a large degree. For instance, its linearity performance, which indicates its capability to

1.2. CHALLENGES IN CMOS RFIC 3

undertake the large input blockers, directly determines whether the off-chip SAW filters

can be removed or not. Besides, the noise of the mixer is one of the largest contributor to

the overall noise of the receiver, even though it is attenuated by the preceding amplifier.

Thus, topology innovation on the mixer circuit is important and meaningful to meet the

emerging trend in wireless communication evolutions described above.

1.2 Challenges in CMOS RFIC

Besides the performance requirements, the evolving of the IC fabrication process also

drives the circuit innovation. Over the past 25 years, the complementary metal-oxide-

semiconductor (CMOS) technology has been extensively used to implement RF circuits

and systems, which brings significant benefits of high integrity level and low cost to wire-

less communication products. On the one hand, most digital circuits are implemented in

CMOS process. With the RF circuits also built in CMOS, a system-on-chip (SoC) can be

potentially realized, which leads to significant reductions in devices size and cost. On the

other hand, CMOS process is generally much less expensive than most of the technologies

that are used in the past (e.g. GaAs).

With the continuous geometrical scaling down of CMOS, the high frequency perfor-

mance of the transistors increases considerably. Two figures of merits, transit frequency

(fT) and maximum frequency (fmax), are usually used to indicate the performance, ex-

pressed as [1]

fT =gm

2π(Cgs + Cgd)(1.1)

fmax =1

2

√fT

rgCgd(1.2)

where gm is the transconductance of the transistor, rg is the series gate resistance, and

1.2. CHALLENGES IN CMOS RFIC 4

Cgs and Cgd are the parasitic gate-source and gate-drain capacitances, respectively. With

the scaling down, the parasitic capacitance decreases, so that fT and fmax increase. For

instance, fT is approximately 45 GHz for 0.18 µm CMOS and approximately 105 GHz for

0.13 µm CMOS, respectively [2]. For RF circuits with frequency up to around 10 GHz, the

speed of the CMOS transistors is not a bottleneck any longer.

However, there are still several challenges when implementing RF circuits in CMOS

process. For example, it remains challenging to realize on-chip inductors with high qual-

ity factors (Q-factors). Generally the inductor performance is determined by its physical

characteristics regarding the loss mechanisms like resistive losses of the metal windings

and substrate losses. Resistive losses of the inductors are decided by the conductivity and

thickness of the adopted metal layer. The substrate losses are divided in two sections:

losses caused by capacitive coupling between metal windings to substrate and eddy current

effects in the substrate layer.

Furthermore, process scaling of CMOS technology also introduces new challenges to

RF circuit design, because many adverse effects for the analog transistors begin to manifest

themselves as the critical dimension shrink. Among these effects the most significant one

is the short-channel effect. As the channel length is reduced to the same order of magnitude

as the depletion-layer widths of the source and drain junction, the electron drift mobility

decreases. As a consequence, velocity saturation can be observed, which potentially leads

to an intrinsic gain degradation. Besides, voltage headroom decreases as the process scal-

ing. For CMOS 250 nm, 180 nm, 130 nm and 90 nm, the recommended supply voltages

are 2.5 V, 1.8 V, 1.2 V and 1 V, respectively, which makes it harder to achieve the same

level of linearity without changing the circuit topology.

The developments in this thesis are all implemented in IBM 130 nm CMOS technology,

1.3. THESIS CONTRIBUTIONS 5

in which the difficulties described above, such as short-channel effects and limited voltage

supply, are all have to be overcome. As well, in one of the designs, on-chip transformer is

implemented to realize a wideband balun. While managing to fulfill the performance re-

quirements, these challenges are also carefully considered when selecting the proper circuit

topologies and accomplishing the physical designs (layout design).

1.3 Thesis Contributions

This thesis proposes three novel active mixer topologies. Each of the mixers focuses on one

aspect of performance optimization that is suitable for different application circumstances.

They are described in details, as follows:

• Measurement and modeling of a new switched transconductor mixer with low power,

low noise and ultra-wide bandwidth. For this mixer, the transconductor stage with

fixed DC operating point is switched by the ac-coupled local oscillator (LO) signal

to realize the mixing, so that decade bandwidth is achieved with power-efficient LO

buffer. In-depth circuit analysis covers the aspects of bandwidth, noise as well as

design procedure to reveal behaviors of the proposed mixer. The mixer achieves a

low noise figure of 4 –5.2 dB over 1 – 10 GHz with a low power consumption of only

8.3 mW from a 1.2 V-supply (Chapter 3) [3].

• Proposal and validation of a novel feedforward linearization technique for active

mixers. This technique generates the third-order intermodulation tone (IM3) for the

cancellation fully in IF band, which leads to robust third-order input intercept point

(IIP3) improvement against parasitic capacitors. A Gilbert cell mixer with the pro-

posed technique applied on it is designed, fabricated, and measured to validate the

1.4. THESIS OVERVIEW 6

idea. Measurement results show that the proposed technique brings 12-dB IIP3 im-

provement to the mixer without deteriorating its conversion gain and noise figure.

(Chapter 4) [4, 5].

• Proposal and validation of a Gilbert-cell-based mixer with on-chip balun and wide

bandwidth. The mixer adopts a folded structure with its transconductor and the

switching stages coupled by an on-chip multifilament transformer, which makes it

possible to realize single-ended-to-differential conversion within the mixer. For the

first time, the transformer is designed to work as an over-coupled double tuned res-

onator to expand the bandwidth. The measurement results demonstrates a gain of

13.5 dB over 4 to 10 GHz for the mixer, with amplitude and phase imbalances lim-

ited to only 0.9 dB and ±2 over the band (Chapter 5) [6].

1.4 Thesis Overview

This thesis is organized topically by chapter. After a literature review, three novel mixers

designed to meet different systematic extremes are described, respectively, in the next three

chapters, with a summary given in the last chapter.

A literature review is first presented in Chapter 2. The mixer concept as well as per-

formance considerations are briefly introduced to provide necessary fundamentals for the

rest of discussions in the thesis. Besides, a summary of the previous work relevant to each

of the circuits demonstrated in the thesis is provided, which allows the contributions of the

thesis to be presented in a broader context.

Chapter 3 reports a switched transconductor mixer with low power, low noise and ultra-

broad band. The transconductor stage with fixed DC operating point is switched by the

ac-coupled LO signal to realized mixing. In this way, only a small LO signal is required to


turn the transconductor on and off and thus a low-power LO buffer can be used to achieve

wideband down-conversion. Inductive peaking technique is used at the RF port to eliminate

the capacitive loading effect resulted from the input transistors so that the bandwidth is

further expanded. As the noise power from LO stage appears in common mode at the mixer

output, good noise performance is realized, too. In addition, output distortion-cancellation

IF buffer is added to facilitate the testing. In this chapter, the bandwidth analysis for both

the baseline and proposed switched transconductor mixers are conducted first to obtain a

better understanding of the design philosophy for the proposed topology. Next, the design

process of the proposed mixer is described with the performance comparison to its baseline

counterpart provided. Additionally, IC implementation details are described including a

NF analysis to provide necessary insight into the main noise contributors and verifies the

effectiveness of series inductive peaking. Measurement results are shown in the end.

Chapter 4 introduces a highly linear mixer. This mixer is based on Gilbert Cell, with a

novel feedforward linearization technique to cancel its IM3. In the feedforward signal path,

the low-frequency second-order intermodulation tone (IM2) is created and multiplied by

the mixer’s output to directly generate the low-frequency IM3 for the cancellation. In such

a manner, most of the canceling operations are accomplished in IF band, so that the tech-

nique can improves IIP3 of the mixer regardless of the mixer topology and robust against

parasitic parameters and process variations. This chapter first describes the working princi-

ple of the proposed technique from systematic perspective. Then the circuit implementation

details of the key blocks are introduced, proving the feasibility of realizing this technique

in CMOS process. Based on these analysis, a Gilbert mixer linearized by the proposed

scheme is depicted with simulations results provided under process, voltage, temperature


(PVT) variations. In the end, the measurement results are given, which verifies the perfor-

mance improvement brought by the proposed linearization technique to the mixer.

Chapter 5 presents a low-power, wideband current commutating mixer with an on-chip

balun. The mixer adopts a folded structure with its transconductor and the switching stages

coupled by a balun, which is made of an on-chip multifilament transformer. With this balun

integrated, the single-ended-to-differential conversion is realized within the mixer block.

Since the transformer is located at the conjunction of the transconductor and the switching

stages, its bandwidth determines the bandwidth of the mixer. The transformer network is

designed to work at over-coupling state, so that a wide bandwidth can be achieved. A tun-

able resistive feedback is used in the transconductance stage to adjust for the wideband re-

sponse as well as the wideband input matching. In this chapter, the equivalent circuit model

of the transformer is introduced. Then, the circuit implementation details are demonstrated.

In the end, results are provided, including measured bandwidth, linearity, noise figure, as

well as simulated imbalance features to indicate the superiority of this design.

Chapter 6 concludes the thesis with a summary of the performance features and benefits

offered by the proposed mixer circuits. Recommendations for additional enhancements and

feature extensions of the proposed circuits are also given for future work.

9

Chapter 2

Literature review

This chapter provides a general introduction to mixers. It starts with a description of mixer

concept from mathematical perspective, with two major issues, image folding and balanced

structure, explained. Following it, circuit topologies as well as their latest performance

achievements and applications are reviewed. Besides, current commutating mixer is then

thoroughly analyzed. In the end, techniques to enhance the performances of active mixer

topologies in bandwidth, noise and linearity are reviewed, which provides a broader context

for the works presented in the thesis.

2.1 Mixer Concept

A mixer achieves frequency translation by multiplying two signals. Assuming the two input

signals A1cosω1t and A2cosω2t, the operation of the mixer can be described mathemati-

cally by the following equation:

(A1cosω1t)(A2cosω2t) =A1A2

2[cos(ω1 − ω2)t+ cos(ω1 + ω2)t]. (2.1)

2.1. MIXER CONCEPT 10

With either cos(ω1 − ω2)t or cos(ω1 + ω2)t chosen, while the other one filtered, it can be

regarded that the signal cosω1t is downconverted or upconverted by ω2, correspondingly. In

the case of downconversion, ω1 and ω2 are referred to RF and LO frequencies, respectively,

and ω1 − ω2 is the IF frequency. While in the case of upconversion, ω1 and ω2 are referred

to IF and LO frequencies, respectively, and ω1 + ω2 is the RF frequency. As the focus of

this thesis, downconversion mixer is analyzed in the following paragraphs if no otherwise

specified.

Besides the frequency of interest, there exists an image frequency on the other side of

the LO with respect to the input signal that will fall into the same output frequency after

the conversion. Besides the RF frequency ω1, 2ω2 − ω1 can also be downconverted by ω2

to the IF frequency ω1 − ω2, expressed as

(A1cos(2ω2 − ω1)t)(A2cosω2t) =A1A2

2[cos(ω1 − ω2)t+ cos(3ω2 − ω1)t]. (2.2)

As this image would end up overlapping on the signal of interest after frequency conversion,

it is desired to be suppressed. The commonly used image rejection method includes a filter

before the conversion that is usually implemented off chip, or a quadrature mixer with

polyphase filter that can be integrated on chip.

Based on (2.1), the frequency translation can be accomplished by the nonlinear devices.

Many types of nonlinearities can be used for mixing, among which the following three are

the most widely seen: I/V relationship of a diode, I/V relationship of a field-effect transistor

(FET) and I/O relation of a switch. To explain the working principle of the three mixing

method, RF and LO signals are assumed to be sinusoid waves, noted as

vRF = ARFcosωRFt, (2.3)


vLO = ALOcosωLOt. (2.4)

The I-V relation of a diode can be characterized as

id = Is

(e

vdVth − 1

)= Is

[1 +

vd

Vth+

1

2!

(vd

Vth

)2

+1

3!

(vd

Vth

)3

+ · · · − 1

](2.5)

where vd and id represent the voltage and current of the diode, and Is and Vth represent the

reverse-bias saturation current and the diode thermal voltage, respectively. If sum of RF

and LO signals are across the diode, i.e.

vd = ARFcosωRFt+ ALOcosωLOt, (2.6)

the squared term in (2.5) will produce the sum and difference frequencies, (ωRF +ωLO) and

(ωRF − ωLO), respectively, which indicates the frequency conversion. Besides the desired

tones, double frequencies 2ωRF and 2ωLO are also generated by squared term. Furthermore,

terms of other orders in (2.5) also generate corresponding harmonics. For example, the

linear term produces tones at ωRF and ωLO; the cubic term produces tones at 3ωRF, 3ωLO,

2ωRF ± ωLO and 2ωLO ± ωRF etc.. These terms need to be eliminated by filters after the

mixer.

Besides, I-V relation of the FET in saturation state can be characterized as

id =1

2K(vg − vs + VOD)2 =

1

2KV 2

OD +KVOD(vg − vs) +1

2K(vg − vs)

2 (2.7)

where id, vg and vs represent the current of the drain and the voltages of gate and source,

respectively, and K and VOD represent device coefficient and overdrive voltage of the FET.


With vRF and vLO applied at gate and source of the FET, separately, i.e.

vg = vRF, (2.8)

vs = vLO, (2.9)

(ωRF + ωLO) and (ωRF − ωLO) can be generated in the output current. Similar to the diode

case, tones at 2ωRF, 2ωLO, ωRF and ωLO are also generated simultaneously by the squared

and linear terms.

Last, but not the least, devices working as voltage-controlled switches can also be used

to realize mixing. With LO signal used to control the on/off and RF signal fed into one

terminal of the switch, the other terminal of the switch appears RF signal when the switch

is close, and zero voltage when the switch is open. The relationship between the output and

two inputs can be mathematically described as

vo = (VRF + vRF)

(1

2+

1

2sgn(vLO)

)=

1

2VRF +

1

2(vRF + VRFsgn(vLO)) +

1

2vRFsgn(vLO),

(2.10)

in which VRF represent the DC voltage carried by the RF signal, and sgn(vLO) can be

expanded as

sgn(vLO) =2

π

(cos(ωLOt)−

1

3!cos(3ωLOt) +

1

5!cos(5ωLOt)− · · ·

). (2.11)

Similar to the foregoing two cases, the product of vRF and vLO is generated, resulting in

desired tones at (ωRF + ωLO) and (ωRF − ωLO) appearing at the output. Along with these

tones, linear tones at ωLO and ωRF also appear at the output. However, contrast to the for-

mer two cases, double frequencies 2ωRF and 2ωLO are not generated. Instead, frequency


fLO 3fLO 5fLOfIF

RF signals Interferers

Figure 2.1: Spurious response: frequency translation by ωLO, its third and fifth harmonics.

translation is conducted by not only ωLO, but its odd harmonics (3ωLO, 5ωLO, etc.), which

converts their surrounding interferers to the band of interest, as shown in Figure 2.1. This

phenomenon is called spurious response, which is not desired and usually reduced by fre-

quency resources arrangement during system design [7].

As can be observed from above, RF and LO signals appear at the output in all the three

methods due to the existence of the linear term. This phenomenon is named as port-to-

port feedthrough, which causes signal leakage and is desired to be eliminated. The most

common method to resist this feedthrough is to recast signals of all ports in differential

manner, i.e. balanced manner. Here, the case of the switches are used as an example to

explain the working principle, while balanced structure can be applied to all three types of

nonlinearities for mixing.

Based on the number of differential ports, the mixers are categorized into unbalanced,

single-balanced and double balanced mixer. Unbalanced-mixers are implemented with all

three ports single-ended; single-balanced mixers with one port differential; and double-

balanced with all three ports differential, as illustrated in Figure 2.2 [8]. For the differential


RF OUT

LO

RL

RF

LO+

RL

LO-

RL

OUT+RF+ RL

RL

RF-

(a) (b) (c)

OUT-

LO+

LO+

LO-

OUT+

OUT-

Figure 2.2: (a) Unbalanced, (b) Single-balanced, (c) Double-balanced mixer implementedwith switches.

RF and LO ports, the expression of signals should be adjusted as

RF : VRF + vRF ⇒

RF+ : VRF + 12vRF

RF− : VRF − 12vRF

(2.12)

LO :1

2+

1

2sgn(vLO) ⇒

LO+ : 12

+ 12sgn(vLO)

LO− : 12− 1

2sgn(vLO)

(2.13)

And for each switch in Figure 2.2, the output signal is derived in the same manner as (2.10).

Together with (2.3) and (2.4), the output voltages of three types of mixers can be gotten, as

summarized in Table 2.1 on the next page.

As can be seen, three types of mixers realize frequency translation in the same man-

ner by producing component ARF cos(ωRF t)sgn(cos(ωLOt)). However, the unbalanced

mixer produces not only the desired signal products, but also RF and LO feedthroughs.

2.2. MIXER CIRCUITS REVIEW 15

Table 2.1: Output components of three types of mixers

Unbalanced Single-balanced Double-balanced

Desired Products 12ARF cos(ωRF t)sgn(cos(ωLOt)) ARF cos(ωRF t)sgn(cos(ωLOt)) ARF cos(ωRF t)sgn(cos(ωLOt))

LO Feedthrough 12VRF sgn(cos(ωLOt)) VRF sgn(cos(ωLOt)) —

RF Feedthrough 12

(VRF +ARF cos(ωRF t)) — —

Single-balanced mixer eliminates RF feedthrough, but LO feedthrough still exists. Double-

balanced mixer gets rid of both feedthroughs, producing a pure product of RF and LO sig-

nal. Thus, unless for specific purposes, most of the mixers are implemented in the double-

balanced structure for its high port-to-port isolation, regardless of the type of nonlinearities

it is using. As an example, diodes mixers that are implemented in the three structures are

provided here in Fig. 2.3

2.2 Mixer Circuits Review

Based on mathematical principles expressed in (2.5), (2.7) and (2.10), large number of

mixer circuit topologies can be realized. According to whether they consume DC power,

mixers can be roughly categorized into two groups, i.e. passive mixers and active mixers. In

this section, these mixer topologies are reviewed from their working principle, key features

to their popular fields of applications and recent trend.

2.2.1 Passive Mixers

Switch mixers in Figure 2.2 and Figure 2.3 are all passive, as they consume no DC power

to operate. Although they have conversion loss, passive mixers are still favored in many

applications that require simplicity, low power operation and high linearity.


RF Filter

VRF

VLO

VIF

VLO

(a) (b)

LO Filter

IF Filter VIF

VRF

(c)

VLO

VIF

VRF

Figure 2.3: Diode mixers in (a) unbalanced, (b) single-balanced and (c) double-balancedstructure [9] with permission c©2006 IEEE.

(a) Diode Mixers

Diode Mixers have been widely used in microwave integrated circuits (MMICs) due to their

simplicity, low noise and their capability to operate at frequencies that are not accessible

to transistor-based mixers. Besides these advantages, diode mixers also have the following

features. First, due to their passive nature, there is conversion loss instead of gain. Second,

since diode mixers are typically implemented in double-balanced structure to achieve high

port-to-port isolation, on-chip baluns are usually required, which occupy a large chip area.

The research on diode mixers focuses on two aspects in the past 20 years, i.e. enhancing


the performance and minimizing the device dimensions. The performance of diode mixers

depends largely on the qualities of diodes (and the process) that are adopted. For instance,

wide bandgap materials are often used for the diodes to improve linearity. The idea of

using wide bandgap technology in diode mixers was first proposed by Fazi and Neudeck

in 1997 [10]. Based on it Eriksson etal continued to propose a Schottky mixer on SiC

substrate with an IIP3 of 31 dBm at 850 MHz in 2003 [11]. These two previous works both

used a hybrid design, so in 2006, a fully integrated design on SiC MMIC is reported, which

proposed a Schottky Diode S-band (2-4 GHz) mixer with an IIP3 of 38 dBm and input

second-order intercept point (IIP2) of 58 dBm at 3.3 GHz, and a typical 1-dB compression

point (P1dB) of 23 dBm [9].

Furthermore, efforts have been made to minimize the size of diode mixers by decreasing

the area of on-chip balun. Traditional transformer-type dual Marchand balun used in diode

mixers is half-wavelength (λ/2) balun, which leads to large chip area in the frequency range

up to 60 GHz [12]. To decrease the chip area, three novel miniature Marchand dual baluns

over 25 – 45 GHz are proposed in [13], which include a novel double-spiral transformer, a

dual balun consisting of two trifilar cascaded transformers and a 3-D structure dual balun.

These designs achieve 80% size reduction while maintaining good performances. What

is more, a 20 – 47 GHz diode mixer using coupled-coplanar waveguide (CPW) Marchand

dual baluns is also proposed, which achieves both compact size and a high coupling coef-

ficient needed for the balun [14]. Besides the innovation on the balun structure, a lumped

miniature dual-balun mixer in the S-band was presented, which achieved the smallest chip

area at the time it was reported [15]. With the increasing of the frequency, the transformer

is not able to operate properly. Instead, a wide range of 90 and 180 couplers can be

used. For instance, a coupler single-balanced mixer MMIC is demonstrated in [16] which


operates at 94 GHz.

(b) FET Mixers

One advantages of CMOS technology is that it offers excellent switches, which can be

exploited to build passive mixers as mathematically explained in (2.10). Mixers made of

FET switches, noted as resistive mixers, not only have the advantages of simplicity and zero

power consumption shared by other passive mixers, they also demonstrate high linearity

and low flicker (1/f ) noise, which makes them appealing options in circumstances such as

blocker-tolerant and direct-conversion receivers.

Passive mixers consisting of FETs have been extensively utilized in the wideband

direct-conversion receivers for multiband, multimode applications because of its superior

linearity and low flicker noise [17–29]. Since RF filters are almost always fixed, multiple

front-ends are required to cover the large number of frequency bands serviced by a mod-

ern wireless device. Without fixed RF filtering, a single wideband receiver that is tunable

over the entire spectrum of interest has to be able to handle adjacent strong interferers. A

conventional wideband design in voltage-mode is shown in Fig. 2.4. Given the voltage

amplification required to achieve a competitive noise figure and low supply voltages used

in modern CMOS process, a 0 dBm adjacent blocker will cause the front-end to saturate.

To address this issue, an architecture consisting of a low noise transconductor amplifier

(LNTA), a passive mixer and a transimpedance amplifier (TIA) is widely used, as shown

in Fig. 2.5 [17, 18, 20, 21, 25, 28, 29]. As can be seen, the input signal is converted to the

current mode at the beginning of the front-end, avoiding the large voltage swing resulted

from voltage amplification of the large adjacent blockers.

Two variations of passive mixers in this applications have to be mentioned due to their


Figure 2.4: A wideband receiver without RF filtering saturated by a large out-of-bandblocker [28] with permission c©2012 IEEE.

Figure 2.5: Receiver architecture: LNTA, passive mixer, transimpedance filter [29] withpermission c©2013 IEEE.

extremely extensive applications. First, instead of using 50% duty cycle, 25% duty-cycle

LO is used for better gain, noise and linearity performances of the receiver [21,29]. Fig. 2.6

shows the quadrature LO waveforms according to this scenario. With the Fourier series for

LO waveforms having a duty cycle of d, the RF current entering each switch generates an

IF current expressed by

IIF(t) =2

π

sinπd

2dIRF0cosωIFt, (2.14)


Figure 2.6: 25% duty cycle LO waveforms at mixer gates (single-ended) [21] with permis-sion c©2009 IEEE.

where IRF0 represent amplitude of the RF current. As can be observed, d=0.5 yields a gain

of 2/π while d=0.25 leads to a gain of 2√

2/π, which is 3 dB higher. In addition, in the

quadrature structures, mixer switches driven by LO waveforms shown in Fig. 2.6 are not

on simultaneously, so that smaller noise and nonlinearity are achieved.

Second, the passive mixer is modified to also operate as an N-path filter, which can

suppress the voltage gain at blocker frequencies [18, 19, 22–24, 26–28]. Fig. 2.7 provides

a typical architecture of this type. As can be seen, the passive mixer is modified to have

an array of switches (N switches) controlled by a square wave with a frequency of fLO and

a duty cycle of TLO/N . In this way, a high-Q bandpass filter around LO frequency can

be realized [30]. As the center frequency of the bandpass filter tracks the LO frequency, it

suppresses the blockers while still maintaining the capability of down-converting the signal

of interest in a wide frequency range. While having many applications in both multiband

and software-defined radio (SDR) receivers, this structure suffers from poor to moderate


Figure 2.7: N-path filtering in the passive mixer-based receiver architecture: (a) Receivertopology (b) N-path filtering [28] with permission c©2012 IEEE.

noise performances [18,19,22–24,26,27]. To improve the noise performance while keeping

the blocker capabilities, [28] proposed a noise canceling scheme that finally can achieved

low noise and blocker tolerant capabilities simultaneously that is suitable for wideband

wireless applications.


Figure 2.8: Circuit schematic of the resistive FET ring mixer (double-balanced mixer) [31]with permission c©2012 IEEE.

On the other hand, the speed of resistive mixers has increased drastically in the past

20 years as the downscaling of the transistor gate length as well as widely use of SOI

technology in CMOS. In 2005, a single-FET mixer in 90-nm SOI CMOS technology is

proposed to work at 26.5 – 30 GHz, which is highest operation frequency achieved by FET

switches to its date [32]. Implemented with only one transistor, RF and LO signals are fed

into the source and gate terminals, respectively, and IF port is at the drain. Parallel LC

tanks are used at both RF and IF ports and an inductor is used at LO gate for the impedance

matching, which also serves as bandpass filters to provide isolations between the ports. The


conversion loss for this circuit is between 9 dB and 13 dB from 26.5 GHz to 30 GHz with

an LO power of 5 dBm. The IIP3 was 12.7 dB and the single-sideband noise figure was

11.4 dB. The measured isolations were between 22 dB and 33 dB for all ports.

The operation frequency of resistive mixers continued to be explored. Instead of using

single FET as in [32], most of them adopt double-balanced configuration for the good

isolation between ports, as shown in Fig. 2.8. In 2010, [33] uses the circuit in Fig. 2.8 to

realize a 15 – 50 GHz mixer in 0.18-µm CMOS technology, which is the highest frequency

MMIC resistive FET ring mixer using CMOS technologies to date. This mixer exhibits

a conversion loss of 13 – 17 dB, and port-to-port isolation of better than 30 dB over the

working band. Furthermore, also based on circuit in Fig. 2.8, authors in [31] proposed

a 40 – 110 GHz mixer in 90-nm CMOS low-power process in 2012. By employing a

weak inversion biasing technique, this mixer can operate with a low LO drive power while

maintaining reasonable conversion gain performance. Measurement results show that a

conversion loss of -1 dB is achieved with an LO drive power of -2 dBm. The isolations

between the ports are above 35 dB.

2.2.2 Active Mixers

Compared with passive ones, active mixers are often more attractive because of their con-

version gain. With conversion gain in a mixer, the receiver needs less amplifiers to achieve

the same system gain. Furthermore, noise performance requirement on stages following

the active mixer is mitigated.

A single FET mixer is the simplest active mixer. Two typical single FET configurations

are shown in Fig. 2.9. Essentially, the large LO changes the transistor’s bias point and

in turn change its transconductance (gm). For the gate-pumped mixer in Fig. 2.9(a), the


RF Filter

Rload

M1

VDD

VRF

VLO

VIF

M1VRF

VLO

VIF

(a) (b)

LO Filter

IF Filter

RF Filter

IF Filter

LO Filter

Figure 2.9: Single FET mixers: (a) gate-pumped and (b) drain-pumped.

transistor is biased at pitch-off, so that with LO waveform from valley to peak, gm has a

huge change from a low state and a high state and vice versa. In this way, the desired

mixing behavior is achieved and the power conversion gain assuming all ports are matched

can be expressed as

G =g2

1Rd

4ω2RFC

2gsRi

(2.15)

whereRd is the output resistance,Ri is the input resistance of the transistor and g1 is weight

of component cos(ωLOt) in gm. Since gm also contains high order harmonics of cos(ωLOt),

a wide range of undesired spectral components are also generated besides the desired mix-

ing product. What is more, RF and LO are connected directly, so RF-LO isolation is quite

poor, which requires filters with high Q to enhance the RF-LO isolation.

To further improve isolation between RF and LO ports, drain-pumped configuration is

proposed, as in Fig.2.9(b). Instead of using gate voltage, the voltage at drain terminal is

controlled by the LO power to achieve large jump of gm, in turn achieving mixing. Al-

though the LO-to-RF feedthrough is largely cut down, parasitic capacitor between gate and


Rload

M1

VDD

VRF

VLO

VIF

(a)

VDD

Rload

M2 M3

(b)

Rload

VDD

VIF

VDD

Rload

iRF

Figure 2.10: Current steering mixer: (a) circuit schematic and (b) mixer operation.

drain terminals, Cgd, still provides a signal path that deteriorates isolation at high frequen-

cies. A design example of gate-pumped mixer reported in [34] demonstrates a conversion

loss of 2 dB operates at 60 GHz. It is fabricated in 130 nm CMOS technology and measured

with a low LO power of 0 dBm. What is more, the drain-pumped mixer in [35] achieves

11 dB conversion loss at 28 GHz. Fabricated in 180 nm, it costs only 0.6 mA from 1 V

supply, making it suitable for low voltage and low power design. From the performance

achieved, it can be seen that both gate-pumped and drain-pumped mixers are suitable for

high frequency applications despiting their poor port-to-port isolations.

Among all types of active mixers, the Gilbert cell mixer is the most popular one. This

mixer can easily be implemented monolithically and has many advantages such as high

gain and high port-to-port isolations. As Gilbert cell mixer is the focus of this thesis, it

will be introduced in details in the next four sections, each focusing on circuit analysis and

advanced structures with enhanced performances in noise, bandwidth and linearity.

2.3. GILBERT CELL MIXER 26

2.3 Gilbert Cell Mixer

The Gilbert cell mixer is in fact a double-balanced current commutating mixer. To provide

its theoretical basis, the single-balanced current commutating mixer is analyzed first. As

depicted in Fig. 2.10, this mixer consists of three transistors (M1 – M3) and two load resis-

tors (Rload). M1 serves as a transconductor (gm) which converts the RF voltage signal into

current. Controlled by VLO, this current is steered into either M2 or M3, and then converted

back to voltage by Rload. Suppose VRF and VLO are defined as in (2.3) and (2.4) and that

switching is ideal, the output current can be gotten as

Iout = gmARFcos(ωRFt)sgn(cos(ωLOt)) +1

2IDCsgn(cos(ωLOt)) (2.16)

With sgn(cos(ωLOt)) expanded, the conversion gain of this mixer can be expressed as

ACG,S =2

πgmRload. (2.17)

As seen in (2.16) and also discussed in Sec. 2.1, this single-balanced current commutat-

ing mixer achieves frequency translation and good RF-IF isolation, but suffers from poor

LO-IF isolation. To address this issue, a double-balanced current steering mixer, i.e. Gilbert

cell mixer, is built by cross-coupling the drains of two single-balanced ones, as shown in

Fig. 2.11. For this configuration, the output current of the Gilbert cell can be written as

Iout = gmARFcos(ωRFt)sgn(cos(ωLOt)). (2.18)

As can be seen, the LO terms are successfully eliminated while the product of LO and RF

remains the same. Consequently, the conversion gain of the Gilbert cell mixer is the same


Rload

1

VDD

VLO

VIF

VDD

Rload

3 4

IDC

2

65VLO

VRF VRF

VIF

VLO

Figure 2.11: Gilbert cell mixer.

as its single-balanced counterpart.

The above analysis is based on the assumption that switching of M2 and M3 is perfect.

In reality, however, VLO needs to exceed a certain voltage (|vin|max) to turn the transistors

fully on. As a result, there must be a time interval (4) during which |VLO| is less than

vin, and M2 and M3 have current going through them simultaneously. Thus, the output of

the mixer is in fact not a product of VRF and a square wave, but a product of VRF and a

quasi-square wave instead, expressed as

Vout = gmRloadARFcos(ωRFt)p(t) (2.19)

in which p(t) represents this quasi-square wave.


VLO(t)ALOVx

-Vx

TLOsgn(VLO(t))

t

t

t

1

-1

1

-1

p(t)

Figure 2.12: Waveform of VLO(t), sgn(VLO(t)) and p(t) from [36] with permission c©2000IEEE.

The waveforms of square wave and quasi-square wave are demonstrated in Figure 2.12

for comparison. Expanding p(t) in the same way as that has been done to sgn(cos(ωLOt))

in (2.11), the coefficient for component cos(ωLOt) is no longer 2π

. An estimation can be

expressed as [36]:

c ∼=2

π(sin(π4 fLO)

π4 fLO), (2.20)

which is apparently smaller than 2π

. With the decreasing of 4, p(t) is close to an ideal

square wave and c to 2π

. Several measures can be taken to reduce 4, so that switching


tends to be ideal and better performances can be achieved. Among these methods the

most straightforward one is to increase amplitude of VLO, which is less attractive as it

introduces more spikes in signals as well as more LO feedthrough. Another method is

to increase the size of the switching transistors, which on the other hand decreases the

bandwidth and increases the flicker noise caused by higher parasitic capacitances. The

most appealing modification is the use of current bleeding techniques [37], which not only

increases conversion gain, but also improves noise and linearity performance. This method

will be analyzed in details later on.

Noise of Gilbert cell Due to the frequency conversion within the circuit, the noise of the

mixer can not be analyzed in the same way as amplifiers. In the following, the noise contri-

butions from each stage of the current commutating mixer (the transconductance, switches

and output load) to the output are investigated. Since the noise signals from low and high

frequency demonstrate different forms at the IF output, they are analyzed respectively. At

low frequencies, flicker noise is usually dominant, while at high frequencies, white noise

is more prominent.

(1) Low Frequency Noise First, flicker noise from the load overlaps on the IF signal

directly without any frequency translation. To reduce it, components with less flicker noise,

such as p-Channel FETs and polysilicon resistors, can be used. Second, flicker noise from

the transconductor stage is upconverted by fLO and its odd harmonics, which naturally

avoids the output IF band. Although the mismatch of switches can introduce some flicker

noise from the transconductor to the IF band, it can be reduced by careful layout. Third,

the switches are the main source of flicker noise, which can manifest themselves through

both the “direct” and “indirect” mechanisms [38]. The single-balanced mixer circuit model


used for the analysis is drawn in Fig. 2.13.

In the direct mechanism, flicker noise is referred to a voltage source with slowing

changing amplitude at the gate of one switch in with its waveform shown in Fig. 2.14(b).

At every skew, noise either advances or retards the zero-crossing time at output by 4t =

Vn(t)/S, where S is the slope of LO voltage at the switching time. In this way, the mixer’s

output current consists of a square-wave with frequency ωLO and amplitude I, superposed

with a pulse train of random widths4t and amplitude of 2I at a frequency of 2ωLO, shown

in Figure 2.14(a). From the perspective of sampling theory, this pulse train can be approx-

imated as noise Vn sampled by (2I/S)δ(t). Thus in the frequency domain, noise current

at the output appears at DC without frequency translation. As well, it also appears at even

multiples of ωLO. To quantify it, the average noise current in one LO period can be written

as

io,n =2

T× 2I ×4t =

2

T× 2I × Vn

S= 4I

Vn

S × T, (2.21)

where T is the period of LO, equal to 2π/ωLO.

The indirect mechanism first came to picture when square-wave was fed into LO to

eliminate the flicker noise. It is related to the parasitic capacitor Ctail in Figure 2.13. Sup-

pose flicker noise vn does not exist, the voltage at the tail, Vs, will remain unchanged with

the switch pairs on and off. However, with vn added to the gate of one switch, Vs appears to

have a vn for half of the period of LO, which charge and discharge Ctail with the frequency

of fLO. Due to current steering, there is a charge current with 2fLO added to output because

of this, which indicates the existence of flicker noise. The noise current is then expressed

as

io,n =2Cp

Tvn

(CpωLO)2

g2ms + (CpωLO)2

(2.22)


Rload

VDD

VLO

VIF

VDD

Rload

M2 M3

ICtail

vn

Figure 2.13: Single-balanced mixer with switch noise referred to the gate from [38] withpermission c©2000 IEEE.

in which gm indicates the transconductance of a switch. This indirect mechanism completes

the transformation of switch flicker noise to the output frequency band. It reveals the risk

of using larger switches because it leads to larger flicker noise.

(2) High Frequency Noise As there is no frequency translation from the load to the

output, white noise from the load appears directly at the output. On the other hand, white

noise from the transconductor stage is downconverted by fLO and its odd harmonics. In

this way, all the white noise around fLO and its odd harmonics appears at the frequency of

interest, overlapping one another, as shown in Figure 2.15.

Additionally, the foregoing model used for analyzing flicker noise from the switch can

also be employed for the analysis of thermal noise from switches. In the direct mechanism,

the noise current at the output consists of train of pulses, with a rate of 2fLO, an amplitude


(a)

(b)

Figure 2.14: Mixer output current with noise: (a) ideal output current and noise impulseand (b) impulse sampling train and flicker noise from [38] with permission c©2000 IEEE.

fLO 3fLO 5fLOfIF

Figure 2.15: Frequency translation of white noise originating in RF input transconductorfrom [38] with permission c©2000 IEEE.


of 2I/S and a width randomly modulated by white noise. However, since the white noise

frequency of interest is comparable to fLO, it can no longer be regarded as ideal sampling,

but a sampling with finite pulse width. In this way, output current is then expressed as

io,n = p(ωLOt) · Vn(t) (2.23)

in which p(ωLOt)is the periodic sampling function, with amplitude equal to transconduc-

tance of switches and frequency of 2ωLO. Transformed to the frequency domain, the power

spectral density of the output current noise is

i2o,n = 4KTγ4I

πALO(2.24)

where γ is the channel noise factor and ALO is amplitude of LO voltage. As can be seen,

the output noise density of switches only depends on the LO amplitude and bias current,

and not on the transistor size.

Besides, Ctail also affects the switch noise at high frequency by an indirect mechanism.

Additionally, large Ctail affects the gain of the mixer at high frequency, which directly

translates to an increase in noise figure.

Linearity of Gilbert cell While Gilbert mixer provide conversion gain, this comes as

a tradeoff with significantly increased intermodulation distortion, which is mainly con-

tributed by both the switching pairs and the transconductor. The switches affect the lin-

earity when the switching action is imperfect. Measures that can be taken to improve the

switchings are already described in the foregoing paragraphs. Usually, a large LO drive is

required. However, an excessive one actually degrades linearity. According to [5], a spike


results from the over-drive LO signal through Cgs of switching transistors, which causes

the transistors to enter their linear region. Thus, no more LO power should be used than

what is required to provide reliable switching.

With the LO power and the switch size carefully designed, the linearity of the Gilbert

cell mixer is primarily constrained by the transconductor [13]. The I-V curve of a weakly

nonlinear transconductor can be approximated by the first three power series terms

I = g1V + g2V2 + g3V

3, (2.25)

where g1,2,3 are the linear transconductance and the second/third-order coefficients, respec-

tively. The IIP2 and IIP3 [1] of the transconductor are determined by the ratio of these

terms:

AIIP2 =

√g1

g2, (2.26)

AIIP3 =

√4

3

g1

g3. (2.27)

The sources of nonlinearities vary for low and high frequencies. Take a transistor as an

example. In low frequency, g3 only consists of the intrinsic third-order distortion of the

transistor. However, in high frequency, g3 consists of both the intrinsic third-order distor-

tion of the transistor and “second-order interaction”. This new component is caused by the

intrinsic second-order distortion of the transistor combined with the feedback, which only

manifests itself at high frequency by parasitic capacitors such as Cgd and many others.

One advantage of the Gilbert cell when it comes to intermodulation distortions is that,

unlike the single balanced mixer, there is cancellation of the even-order distortion prod-

ucts. This feature is very appealing in the direct-conversion receiver, where stringent IIP2

requirement is demanded. Nevertheless, the mismatch of the switches as well as LO signal


can still deteriorate the even-order intermodulation products at the mixer output. Thus, the

small g2 of the transconductor stage is still highly desired.

Bandwidth of Gilbert cell Unlike the RF amplifier which usually has inductors involved

and a bandpass feature demonstrated, the Gilbert cell mixer often shows a low-pass transfer

function. On the other hand, due to the frequency conversion, the mixer’s output is at IF

band, so that the RF bandwidth is not determined by the circuit network at mixer output.

Instead, it is determined by the time constant of common-source node of the switching

pairs.

The single-balanced mixer in Fig. 2.13 can also be used for the bandwidth analysis. As

can be seen, a portion of RF current from transconductor stage is fed into the switches (M2

and M3) and contributes to the conversion gain, while the remaining portion leaks to ground

through the parasitic capacitor Ctail. With the increasing of RF frequency, the portion that

leaks to ground increases, and the conversion gain thus decreases correspondingly. To

include this phenomenon, the conversion gain of the mixer can be further expressed as

AV,CG =2

πgm

gm,LO

gm,LO + jωCtailRload (2.28)

where gm,LO represents transconductance of LO stage.

Several characters about the mixer’s bandwidth can be reveal from (2.28). First, since

the dominant impedance of the node (1/gm,LO) is approximately in the range of 80 to 200

Ω, the bandwidth of the mixer could be up to 5 to 8 GHz, which is several times larger than

its amplifier counterpart made of same transistor sizes. Second, with the above mechanism

revealed, improvement can be made by modifying the circuit network at this node to further

expand the bandwidth for Gilbert cell mixer. In fact, the mixer presented in Chapter 5 uses

2.4. LOW NOISE MIXER REVIEW 36

this method to realize a Gilbert mixer from 4 to 10 GHz.

2.4 Low Noise Mixer Review

The circuit analysis in last section reveals that noises from different frequencies and stages

of the Gilbert cell mixer transfer to the output through different mechanisms. Based on

the analysis, many noise reduction techniques were proposed to lower the noise figure. A

brief review is provided in this section. As the noise reducing principles for low and high

frequencies are different, they are discussed separately.

2.4.1 Flicker Noise Reduction

It was disclosed in Sec. 2.3 that the switches are the main contributors to flicker noise with

the load components carefully selected. Based on (2.21), flicker noise can be reduced by

two methods: increasing the slope of LO signal normalized to its frequency (S × T ) and

decreasing the bias current of the switches [39]. The first one is unappealing because it

introduces other problems. For instance, enlarging LO amplitude can produce spikes in the

signal; and a large switch size brings more parasitic capacitance, which in turn increases

the flicker noise through indirect mechanism.

Reducing flicker noise by decreasing the bias current in the switches is promising if

the high conversion gain can be maintained at the same time. This can be achieved by the

current bleeding technique that was first proposed in [37], as demonstrated in Figure 2.16.

As can be seen, current source made of M7,8 feeds some DC current to M1,2 to ensure large

transconductance, while its high impedance forces all the RF current into the switches.

In this way, the large conversion gain is guaranteed while the current through switches


decreases. Although this configuration reduces flicker noise produced by the direct mech-

anism, the use of a current source transistor causes new problems. First, more white noise

are introduced at the output. Second, the parasitic tail capacitance is increased, which not

only enhances flicker noise from the indirect mechanism, but also lowers the bandwidth.

Last but not the least, due to the finite input impedance of the transistor as a current source,

the degradation of conversion gain of mixer is inevitable.

Modified current bleeding techniques are proposed in the effort to solve these prob-

lems. First, with the gate connected to VRF by a capacitor, the bleeding current source

transistor is also used to contribute to the overall transconductance [40,41]. This structure,

commonly called current reuse bleeding, inherits all the benefits of the bleeding effect. In

addition, since the bleeding current source in this topology is made part of the drive stage,

the noise figure is naturally reduced. Along with it, higher conversion gain is achieved.

Second, dynamic current injection technique is proposed in [39, 42], which is essentially a

bleeding circuit that only injects current when both switches are on. With this technique

used, white noise of bleeding circuit is not added at the output, which lowers the noise fig-

ure. Besides, cross-coupled bleeding was also proposed [43]. With two bleeding transistors

cross-coupled with each other by capacitors, the conversion gain of mixer increases and its

noise figure decreases significantly.

To eliminate the flicker noise from the indirect mechanism, an inductor can be used to

resonate out the parasitic tail capacitance [44]. More commonly, the inductor and current

bleeding structure are used together [45]. Besides, the positions of inductors and bleeding

current source have to be elaborately chosen to achieve the best noise figure and conver-

sion gain [45]. Another interesting point worth noting is that resonant inductor could be

substituted by differential active inductor, which saves chip area while good noise figure is


Rload

1

VDD

VLO

VIF

VDD

Rload

3 4

2

65VLO

VRF VRF

VIF

VLO

VDD

Vb

7 8

Figure 2.16: Gilbert cell mixer with current bleeding.

achieved [46].

2.4.2 White Noise Reduction

As the major source of thermal noise, transconductor stage can be replaced by an low

noise amplifier (LNA) to reduce noise figure. Two commonly used LNA structure, source

degeneration and common gate, could be employed. The mixer with source degeneration

as transconductor stage can achieve a double sideband (DSB) noise figure as low as 3.5

dB [44, 47]. However, due to bandpass nature of the source degeneration structure, it can

only operate with a very limited bandwidth. On the other hand, the mixer with common

gate transconductor stage is able to achieve broad bandwidth, but its noise performance is

not as good. To further decrease its noise figure, noise cancellation techniques can be used

to eliminate the noise contribution from common gate transistor [48]. In this way, low noise


Rload

1

VDD

VLO

VIF

VDD

Rload

3 4

2

65VLO

VRF VRF

VIF

VLO

VDD

Vb

7 8

Ls Ls

Lg LgCex Cex

(a)

Rload

1

VDD

VLO

VIF

VDD

Rload

7 8 109 VLO

VRF VRF

VIF

VLO

VDD

Vb

11 12

Lpeak

Lg

LpeakVDD

Rl

Lg

VDD

Rl

2

3

4

5

6

(b)

Figure 2.17: Low noise current bleeding mixers with (a) source degeneration transconduc-tor from [47] with permission c©2011 IEEE and (b) common gate tranconductor from [48]with permission c©2010 IEEE.

2.5. LINEAR MIXER REVIEW 40

figure is achieved for the Gilbert cell mixer while broad operating band is still maintained.

According to (2.24), current bleeding technique is an effective method to decrease ther-

mal noise from switching stage as well. In the practical uses, noise reduction techniques

for flicker and white noises are often used simultaneously to achieve satisfying noise per-

formance, as can be seen from examples in Figure 2.17 [47, 48].

2.5 Linear Mixer Review

The discussion in Sec. 2.3 reveals that the linearity of the Gilbert mixer is limited by the

transconductor stage if proper switch size and LO power are chosen. Since the transcon-

ductor stage is essentially an RF amplifier, most of the linearization techniques for RF

amplifiers can be applied to improve the linearity of Gilbert mixers.

A large number of works have been proposed to linearize the RF amplifiers, specifically,

to improve IIP2 and IIP3. Those methods are roughly categorized into 8 clusters: a) feed-

back; b) harmonic termination [49–56]; c) optimum biasing [57]; d) feedforward [58, 59];

e) derivative superposition (DS) [60–65]; f) IM2 injection [66]; g) noise/distortion cancel-

lation [67–70]; and h) post-distortion [71–73]. As seen from the substantial papers listed,

linearization technique has been extensively researched before, and even introducing each

of the above category itself could form a substantial review paper, separately. Here, a brief

summary is demonstrated in Table 2.2 on the next page to list the nonlinearity sources that

each technique can suppress. Generally, IIP2 is degraded by the intrinsic second-order dis-

tortion, while IIP3 is degraded by both intrinsic third-order distortion and the “second-order

interaction”, which is caused by intrinsic second-order distortion combined with feedback.

With Table 2.2 on the next page provided, the linearity specifications that each method can

improve are clear.


Table 2.2: Nonlinearity sources and linearization techniques

Intrinsic 2nd-order Intrinsic 3rd-order 2nd-order interaction

Feedback

Harmonic termination

Optimal biasing

Feedforward

Derivative superposition (DS)

IM2 injection

Noise distortion cancellation

Post-distortion

Most of the above linearization techniques for RF amplifiers have been used to increase

IIP2 and IIP3 of the Gilbert cell mixers. Through an in-depth analysis, three mechanisms

responsible for second-order intermodulation in active mixer are revealed in [74] — self-

mixing, second-order distortion of the transconductor and nonlinearity and mismatches in

the switching. Leveraging these findings, authors in [75] employ capacitive degeneration

to decrease the IM2 contribution of transconductor, and uses LC resonator to to eliminate

the IM2 contribution of switches through tuning out the parasitic capacitance at source of

switching pairs. This work achieves IIP2 of +78 dBm with a conversion gain of 16 dB.

It is proposed in [76] to inject a programmable nonlinear current into the mixer output,


and improves the IIP2 by more than 25 dB with an extra 1 mA of current consumption.

Similarly, another method is proposed in [77] to inject an IM2 current into the mixer output.

With a variable gain amplifier to control the amplitude of the injection component, this

technique could adjust with the temperature variation of the IM2 distortion. Besides IIP2

enhancing techniques, IM2 injection technique is used in [66] to cancel the intrinsic third-

order distortion of the mixer transconductors. Authors in [78] also adopt IM2 injection

technique, and manage to improve both IIP2 and IIP3 Simultaneously. The simulation

results show that +93 dBm IIP2 and +15 dBm IIP3 are achieved under 1.8 V voltage supply.

This is the highest linearity performance achieved so far for direct conversion receiver

applications. Most recently, the topology reported in [42] utilizes negative impedances at

the source of mixer switches to cancel the IM3 (and the flicker noise). Through dynamic

current bleeding provided by these negative impedances, an IIP3 of 11.8 dBm is achieved.

Although these works achieve high IIP2 and (or) IIP3, each of linearization technique

has its own suitable circumstances as well as drawbacks. For example, DS technique is used

in Gilbert cell mixers to cancel the intrinsic third-order distortion and effectively improves

the IIP3 without costing much power and area budget [61, 79–81]. However, it is very

sensitive to the bias and only functions well below 1 GHz [62, 82]. On the other hand, for

another example, IM2 injection technique [66, 78] can be only used in the differential pair

with a tail current source, which serves as the port for the IM2 component to be injected in.

Besides aforementioned linearization methods, a systematic level linearization tech-

nique, noted as adaptive feed forward error cancellation, is proposed in [83] with its scheme

shown in Fig. 2.18. The system consists of a main and an auxiliary paths. Main path is

the original receiver with self-generated interference. The auxiliary path is used to take

the input signals, regenerate distortions and then feed forward to the output of main path


Figure 2.18: General adaptive feedforward receiver concept [83] with permission c©2008IEEE.

to cancel out the distortions. This technique is advantageous because it improves the lin-

earity regardless of the architecture of the original receiver, resulting in large flexibility in

applications. Mathematical basis for this technique is provided in [84] while [83] demon-

strates a specification-compliant custom-designed example, with its systematic architecture

shown in Fig. 2.19. In this receiver, an auxiliary path almost identical to the main path is

built. Although this work achieves superior linearity performance, the use of auxiliary path

not only doubles both power consumption and chip area, but also introduces complex dig-

ital processing circuit. These drawbacks actually provide us with large room for further

improvement, which is one of the focuses in this thesis.

2.6. WIDEBAND MIXER REVIEW 44

Figure 2.19: UMTS receiver architecture with adaptive linearization in [83] with permis-sion c©2008 IEEE.

2.6 Wideband Mixer Review

As revealed in Sec. 2.3, the bandwidth of Gilbert cell is determined by the time constant of

the circuit network at the common node of switch pairs. Based on this observation, many

attempts to modify the transfer function of this circuit network have been made to improve

the bandwidth of Gilbert mixer, which includes adding inductive peaking, introducing neg-

ative impedance and switching the RF port position.

Inductive peaking is a widely used technique to expand the bandwidth, which can mit-

igate the loading effect to delay the charging of parasitic capacitors through forming an

inductive peaking network [1]. There exists series and shunt peaking techniques, both

of which can be employed in mixer design, as illustrated in Fig 2.20. Shunt peaking

is adopted in [47, 85] by adding an inductor between the two common-source nodes of

double-balanced switch pairs; authors in [48] employ a series peaking inductor of 1.02 nH,

which increases the 3 dB cutoff frequency by 2.3 GHz. Series peaking is also employed


RF Stage

LO Stage

Lpeak

VRF+ VRF-

VLO+ VLO-

VIF+ VIF-

Ctail Ctail

(b)

RF Stage

LO Stage

Lpeak

VRF+ VRF-

VLO+ VLO-

VIF+ VIF-

Cp Cp

Cp Cp

(a)

Figure 2.20: Inductive peaking in Gilbert mixers (a) series (b) shunt.

in [86], which effectively extends the bandwidth from 4 to 10 GHz.

Besides, a negative impedance can be introduced to the node, as shown in Fig. 2.21(a)

[87]. The input admittance of the added circuit can be written as

Yn = gm

(1 +

ω2LC

1− ω2LC

)+ j

ωC

1− ω2LC(2.29)

where gm and C are the transconductance and the gate source capacitance (Cgs) of MA.

If 1 − ω2LC < 1, the real and imaginary parts become negative. Three kinds of effect

due to this additional circuit block enhance the conversion gain and the high frequency

performance. First, it generates negative resistance at the output of transconductor stage,

which boosts the small signal gain [8]. Second, the parasitic capacitance at the node can be

canceled by the negative imaginary part of Yin, which enhances the gain at high frequencies.

Finally, the additional circuit injects bias current to the transconductor stage, increasing the

gm that it can achieve. Measurement shows that a high conversion gain of 9.12 dB is

achieved by this mixer from 22 to 26 GHz.

Last, but not the least, RF port position can be modified so that Ctail is no longer part


Rload

1

VDD

VLO

VIF

VDD

Rload

5 6 87 VLO

VRF VRF

VIF

VLO

Vb

Lg2

Lg

VDD VDD

3 4

A A

LpLp

Cg Cg

VP VP

(a)

Rload

3

VDD

VLO

VDD

Rload

1 2 4

VDD

5

Vc

Rvar

VRF C1

6 7

CP

RSW-1/gm4

VIF Buffer VIF,OUT

(b)

Figure 2.21: Wideband Gilbert mixer in (a) [87] with permission c©2009 IEEE and (b) [88]with permission c©2014 IEEE.

2.7. SUMMARY 47

of RC network that determines the bandwidth. As can be seen in Fig. 2.21(b), [88] has the

RF signal fed into the directly through a transmission line and an ac coupled capacitor. In

this way, Ctail is now a part of matching network, instead of a load of the node. Combined

with a cross-coupled pair that provided at negative impedance at the mixer output, 20.7 dB

gain can be achieved over a frequency range of 10 to 67 GHz with a power consumption of

only 1.44 mW. This is the highest gain ever achieved over this range of frequency. What is

more, by controlling the bias current of the negative impedance, a wide gain tuning range

of 40 dB is also achieved.

Besides the bandwidth enhancement techniques proposed for Gilbert mixer, the wide-

band matching network is also desired in two situations. First, it is desired when the operat-

ing frequency rises to microwave range for the chip dimensions. Second, it is desired when

the mixer chip is used as a stand alone device. Many wideband matching techniques for

the Gilbert mixers have been proposed too. A common-gate-based, noise-canceling circuit

is used in [48] to realize a wideband matching from 1 to 7 GHz; A common-gate RF stage

with the cross-coupled complementary transistors is adopted in [86] to realize the input

matching for 1 to 10 GHz with a conversion of 3-8 dB; And an LC ladder at the gate of the

common-source transconductor stage is employed in [89] to realize a 25-75-GHz Gilbert

mixer in 90 nm CMOS process.

2.7 Summary

This chapter provides a general review of CMOS downconversion mixers. The current

commutating mixer is thoroughly analyzed first, followed by a summary of performance

enhancing techniques that bring improvements on mixers’ bandwidth, noise and linearity

specifications. With the broader context demonstrated by this chapter, three novel mixer

2.7. SUMMARY 48

topologies with significant performance upgrading are readily presented in the next chap-

ters.

49

Chapter 3

A Low-Power, Low-Noise, Decade-Bandwidth Mixer

3.1 Introduction

In this chapter, modeling and measurement of a modified switched transconductor mixer

(MSTM) with low power, low noise and ultra-broad band are presented. This mixer was

first designed by Ahmed El-Gabaly, a former lab member, but never got measured and an-

alyzed. In this chapter, bandwidth analysis of the proposed mixer is first carried out, which

is followed by a discussion on parameters selection and the performance comparison with

the traditional switched transconductor mixer (STM). Additionally, a NF analysis provides

necessary insight into the main noise contributors and verifies the effectiveness of series in-

ductive peaking in the design. These analyses disclose the main advantage of the proposed

mixer: MSTM can work with much less power than STM to achieve same bandwidth and

noise figure, which makes it a preferred choice in low-power ultra-wideband applications.

Ultra broadband low-noise mixers are needed in the multi-band wireless hand held de-

vices and infrastructure. As the number of communication bands increases to provide more

functionality, to handle more users and to enable higher speeds, the bandwidth, NF and lin-

earity specifications of wideband receivers are becoming more stringent. Ultra broadband

3.1. INTRODUCTION 50

active down-conversion mixers are attractive for multi-band RF receivers because they have

the known benefits of high gain and low LO power, yet their moderate to high NF levels,

in the absence of noise mitigation strategies, places strict gain and NF requirements on

the preceding LNA. Therefore, further advances are needed in ultra broadband low-noise

mixers to relax such requirements on the LNA without compromising interdependent per-

formance metrics, including power dissipation.

Several different topologies exist for wideband low-noise down-conversion [90–94].

Among them the most recent and effective approaches are based on current-commutating

mixers with noise-cancelling transconductors [90–92]. The noise cancellation can be real-

ized in various forms. A cross-coupled transistor pair is used in [90] to realize partial noise

cancellation of the common-gate input transistors. A parallel common-source transistor is

employed in [91, 92] to cancel the noise of the common-gate input transistors.

Often, the mixer LO switches are implemented at the current mirror nodes of an am-

plifier in [93] to achieve wideband low-noise down-conversion. While this technique com-

bines the advantages of passive and active mixers, such as low noise and high gain, its

noise bandwidth is limited due to the use of a resonating tank to suppress the major noise

contributors. In [94], the bulk-injection technique is adopted to realize a mixer that covers

the span 3.1−10.6 GHz at a low power consumption of 0.88 mW but a NF of 11.7 dB.

In addition to the efforts in wideband low-noise down-conversion described above,

STM proposed in [95] shows superior noise performance with low power consumption and

low voltage supply. With the transconductors turned on and off by the switches connected

to the supply rails, this mixer’s NF is lower compared to its current-commutating counter-

part for high LO frequencies due to the absence of LO noise at the output. One method to

expand the bandwidth of the STM topology is by adding a push-pull LO driver [96], yet

3.2. PROPOSED METHOD TO INCREASE THE BANDWIDTH OF THE STM 51

this approach increases the power dissipation of the circuit.

The mixer structure presented in this chapter is based on the STM topology. Modifica-

tions are made to inherit superior noise performance of STM while less power is needed to

realize ultra broadband operation. Besides the modification on the mixing core, inductive

peaking is adopted at the RF port to eliminate the capacitive loading effect from the input

transistors. An IF buffer is also integrated on-chip to facilitate experimental testing of the

mixer by providing the drivability of the output 50-Ω load. The buffer incorporates a deriva-

tive superposition distortion canceling subcircuit [61,63–65] to reduce the intermodulation

distortion it produces to better characterize the mixer’s IP3 performance.

3.2 Proposed Method to Increase the Bandwidth of the STM

A qualitative description of the factors that impact the frequency response of the baseline

STM is first provided followed by the proposed method to improve the bandwidth of the

STM using a modified STM (MSTM). A detailed one-to-one comparison between the base-

line STM and the MSTM is carried out in simulation to show the effectiveness of the new

approach.

3.2.1 Bandwidth considerations in the baseline STM

The circuit diagram of the baseline STM topology is given in Fig. 3.1(a). It uses a differ-

ential pair (M1, M2) as the transconductor and a switching block [95]. The switch is driven

by the LO signal and turns the transconductor pair on and off by chopping its tail current,

thus producing the mixing action. The topology is very well-suited for low-voltage appli-

cations and demonstrates potential for significant reductions in NF, because the noise from

the LO stage appears in common mode at the mixer output and thus does not deteriorate


Figure 3.1: Bandwidth study of the baseline STM: (a) schematic of the baseline STM [95];(b) schematic of the inverter-based LO buffer [95]; (c) waveform of VA with the increase ofLO frequency; (d) schematic of the “push-pull” LO buffer [96].

the differential output signal.

Similar to the current-commutating mixer, the STM transconductor needs to be turned

completely on and off with little transition time to achieve best performance. This is

achieved by the switching stage, which is typically built with CMOS inverters. In a fully-

integrated radio chip, the LO power produced by the frequency synthesizer requires an ad-

ditional boost to produce a suitable waveform to drive the mixer such as the inverter chain

depicted in Fig. 3.1(b). At low LO frequencies, with proper transistor dimensions chosen

for the LO buffers and the switch, VA can be switched between supply rail and ground


completely and symmetrically. As a result, the conversion gain of the STM is verified [95]

to be the same as that of the current-commutating mixer.

A salient factor that impacts the bandwidth of the STM is the ability of the LO switches

and the inverter-based buffers to produce a rail-to-rail output as the frequency increases.

As illustrated in Fig. 3.1(c), as the LO frequency increases, the time that can be used for

the high/low transitions of VA decreases while the time constants of the inverters remain

unchanged. Eventually when the frequency is larger than a certain value, VA cannot fully

transition from rail to rail. Transients will make the sawtooth waveform VA drift up and

down from the center, which compromises the on/off switching response of the transcon-

ductor and, hence, the mixer.

Efforts have been made to expand the bandwidth of the STM by adding a wideband LO

driver. One such driver used in [96] is drawn in Fig. 3.1(d), which is a “push-pull” structure

to increase the output current-driving behavior. Furthermore, the common-mode voltage of

the driver’s output is fixed by the common-mode feedback circuit. In this way, even if the

magnitude of the driver output voltage cannot reach the supply rail at high frequency, the

transient drift of the signal at VA is much reduced. With VA more consistently centered at

the middle of the supply voltage, the transconductor’s switching is sustained up to a higher

frequency than before. The cost of increasing the frequency response with the push-pull

driver in Fig. 3.1(d) is a noticeable increase in the power consumption. For instance, to

obtain an STM with 8 GHz bandwidth, the buffer design in [96] draws 5 mA per LO+/LO-

buffer from a 1.2 V supply.


3.2.2 The proposed MSTM concept

Based on the above analysis, STM is power-consuming when operating in wideband be-

cause the switches require wideband LO drivers, which dissipate large amount of power.

Addressing this issue, an MSTM is proposed, in which transconductors can be turned on

and off without rail-to-rail-operating switches, and the power-hungry LO drivers of the

switches can be eliminated while an ultra-wide band can still be achieved. In this way, the

power consumption can be decreased with the same LO power as STM.

The proposed MSTM is depicted in Fig. 3.2(a). The transconductor stage consists of

the differential pair (M1-2) and a resistor RB. The LO signal is fed-in through the coupling

capacitor CB to turn the transconductor on and off and an LO buffer amplifier provides the

driving ability. In the following, the working principle of the MSTM is described to show

how a nearly-constant conversion gain over an ultrabroad bandwidth is achieved when the

LO signal power exceeds a small threshold while keep the buffer circuit power consumption

at a low level.

If the LO signal reaching node A in Fig. 3.2(a) is small, the circuit forms a multiplier be-

cause RF and LO signals together modulate the transconductance (gm) of M1,2. In this case,

the conversion gain exhibits a quite linear dependence on the strength of the LO signal.

As the LO power increases, M1,2 will turn off for part of the LO period. As the LO keeps

rising, M1,2 can eventually turn off for approximately half of the period. Consequently, the

transconductor is turned on and off alternately by the LO and a mixer with similar behavior

of STM is realized.

Next, two key points related to the working principle of the MSTM will be discussed:

(i) the minimum voltage swing of VA needed to fully turn the transconductor off and (ii) the

effective gm of the MSTM. To assist the explanation, refer to Fig. 3.2(b) which shows the


Figure 3.2: Bandwidth analysis of the modified STM (MSTM) (a) schematic of the MSTM;(b) waveforms of VA, current through the transconductors I1,2 and their transconductancegm1,2.


waveform at node A, the currents I1,2 through M1,2, and the instantaneous transconductance

of the transistors gm1,2.

The transconductor has to be biased at a point where M1,2 can provide substantial

transconductance. As seen in Fig. 3.2(b), the bias voltage of the gates and the sources

of M1,2 are denoted as VRF,CM and VA,DC, respectively. In this way, the overdrive voltage of

M1,2, VOD, is

VOD = VRF,CM − VA,DC − VTH (3.1)

in which VTH represents the threshold voltage of M1,2. Under this condition, the transcon-

ductance of M1,2 is denoted as gm,0, and the impedance looking into the node A from the

buffer output is (1/2gm,0)//RB. Second, in the MSTM, the load of the LO buffer varies as

a function of the transconductance of M1-2, which impacts VA. For the trivial case when

the LO buffer drives a fixed impedance equal to the impedance of node A under DC bias,

i.e.(1/2gm,0)//RB, let the amplitude of the buffer output be denoted as va, as illustrated

with the dashed curve in Fig. 3.2(b). Now, the solid curve in Fig. 3.2(b), VA is in fact

asymmetrical to VA,DC. As VA increases, the output impedance of the buffer increases from

(1/2gm,0)//RB towards RB, which reinforces the rise of VA. As a result, the upper half

increment of VA from VA,DC is somewhat larger than va. For simplicity, let it be equal to va.

The smallest value of VA that turns M1,2 off, denoted as VOFF, is

VOFF = VRF,CM − VTH, (3.2)

the corresponding minimum amplitude of the buffer output needed to turn off M1,2 can be

written as

va,min = VOD. (3.3)


When va increases beyond va,min, the transconductor will remain off.

On the other hand, with the same amplitude fed into the LO buffer, the low voltage

appearing at the buffer output, denoted as VON, is much closer to VA,DC due to the negative

feedback in the system. As VA decreases, the transconductance of M1,2 increases, which

decreases the load impedance and thus the gain of the buffer. Therefore, the drop in VA is

diminished and VA still remains close to VA,DC. Thus with a large range of va, the effective

transconductance of the MSTM is approximately gm,0, which is the transconductance under

the DC bias as described above.

To summarize, va must exceed va,min given by (3.3) to make the MSTM work prop-

erly. When va is small, the conversion gain increases linearly to va. As va exceeds va,min,

the effective transconductance remains close to gm,0 and thus the conversion gain stays as

a constant as va increases. The relation between the conversion gain and va is further il-

lustrated by the curve in Fig. 3.3(a). As can be seen, when va is smaller than va,min, the

conversion gain increases linearly. As va exceeds va,min, the conversion gain tends to stay

stable. This character is used here to make the MSTM operate in a wide band without

having a power-consuming wideband LO driver, as explained below.

For the low-pass LO buffer with a certain bandwidth, its output power rolls off quickly

at high frequencies, as illustrated in Fig. 3.3(a). With the increase of LO frequency from

f1 to f3, the amplitude at the buffer output drops considerably from va,1 to va,3. How-

ever, as va,1, va,2 and va,3 are all larger than va,min, the conversion gain realized by MSTM,

ACG,1−ACG,3, are close to one another. Consequently, a nearly flat conversion gain of the

MSTM over a wide frequency from f1 to f3 is achieved, which is illustrated in Fig. 3.3(b).

Therefore, with this feature, a very low-power LO buffer can be used to realize wide-band

down-conversion.


Figure 3.3: Frequency response of the modified STM (a) with VA as an intermediate vari-able; (b) direct relation between conversion gain and frequency.


Figure 3.4: (a) Double-balanced modified switched transconductor mixer (MSTM). (b)Double-balanced switched transconductor mixer (STM) with current-reuse amplifiers asLO buffers.

3.2.3 Simulation verification

A double-balanced mixer based on the proposed MSTM topology is designed in a standard

0.13 µm CMOS process. Design process and the related simulation results are demon-

strated in details. Additionally, an STM design instance is provided for comparison pur-

poses.

(1) Wideband MSTM design

The schematic of the double-balanced MSTM is shown in Fig. 3.4(a). M1-4, RB and CB

are used to realize the MSTM core proposed in Section 3.2.2. Complementary, current-

reused amplifiers (M5−8, RF) are adopted to realize the LO driver which is symbolized in

Fig. 3.2(a). Additionally, self-biased current sources (M9−10, RIF) are used to provide a

high-impedance load of the mixer.

In this design, the width of M1−4 is made relatively large (W = 80 µm) so that VGS is


close to the threshold voltage VTH. This arrangement is made so that a large transconduc-

tance can be obtained when the transconductor is turned on, and low input-referred noise

can thus be achieved. Second, a very low overdrive voltage near 0 V results in this way,

which allows the transconductor to turn off easily.

The LO buffers adopt the current reuse complementary amplifier structure for its high

current efficiency to generate transconductance (gm), as seen from Fig. 3.4(a). RF is used to

stabilize the output DC voltage while its resistance is chosen to be large enough to realize

adequate gain of the amplifier. The transfer function of the amplifier can be approximately

expressed as (gmN + gmP)(roN//roP//RA//CA), in which RA and CA represent the resistance

and capacitance at node A and the rest represent their usual meanings for the LO buffer. As

described in foregoing analysis, RA equals to (1/2gm,0)//RB under DC bias point, which is

close to 50 Ω in this design. With 1.5 mA current assigned to each single-ended LO buffer,

a -0.5 dB gain with 3-dB bandwidth of 10 GHz is achieved.

Simulation waveforms of the common source voltage VA and current through M1,2

noted as I1,2 are plotted in Fig. 3.5. The waveforms of both 1 GHz and 10 GHz when

the LO power is -1 dBm are plotted (solid line). As can be observed, when the LO fre-

quency is 1 GHz, the transistor is off when VA exceeds around 0.3 V and on otherwise.

The shape of waveforms for both voltage and current are same as predicted in Fig. 3.2(b).

With the frequency increasing to 10 GHz, the magnitude of VA decreases due to the limited

bandwidth of the LO driver. As a consequence, the duty cycle within which M1,2 are fully

on or off decreases and the transition time increases correspondingly. What’s more, due

to the decrease of the VA magnitude, the maximum current when M1,2 are on decreases to

around 0.8 mA, which leads to a decrease of the effective gm of the mixer. The increase

of the transition time and decrease of the effective gm from 1 GHz to 10 GHz are the two


0

0.2

0.4

0.6

0.8

VA (

V)

4 4.5 5 5.50

0.5

1

1.5

time (ns)

I 1,2 (

mA

)

VA,DC

(a)

0.1

0.2

0.3

0.4

VA (

V)

0.3 0.35 0.4 0.45

0

0.5

1

time (ns)

I 1,2 (

mA

)

VA,DC

(b)

Figure 3.5: Waveforms of VA and I1,2 with LO input power at -1 dBm (solid line) and -13dBm (dashed line) when LO frequency is (a) 1 GHz, (b) 10 GHz.

causes for the conversion gain drop. However, as depicted by the conversion gain curve in

Fig. 3.6, the gain drop is around 2 dB from 1 GHz to 10 GHz when the LO power is -1

dBm. In this manner, a wideband operation is achieved.


Figure 3.6: Output power of LO buffer and voltage conversion gain of the MSTM.

For comparison, the waveforms for both 1 GHz and 10 GHz when the LO power is

12 dB smaller (-13 dBm) are plotted in Fig. 3.5 (dashed line), too. Under this condition,

even at 1 GHz, VA magnitude is too small to fully turn M1,2 off. As a result, the LO signal

is modulating gm and the conversion gain is approximately linear to the signal strength of

LO buffer output, as mentioned in the preceding description. To verify it, the conversion

gain curve when LO power is -13 dBm is also plotted (dashed line) in Fig 3.6. As can

be seen, the gain drop is around 5 dB from 1 GHz to 10 GHz, and the slope of the curve

is approximately the same as the LO buffer output, which is depicted in the upper plot in


Fig 3.6. Besides the much smaller bandwidth, the conversion gain is smaller because a

lower effective gm is produced.

The LO input power also affects the bandwidth of the mixer. To reveal this relation, the

voltage conversion gain of the MSTM and the output power of the LO buffer at node A are

drawn with different input LO power levels in Fig 3.6. As before, the impedance of node

A changes with VA. To obtain a normalized output power of the LO buffer over frequency,

assume that the buffer is driving a fixed load of (1/2gm,0)//RB. From the graphs, it is easily

observed that the rolloff of the conversion gain is much slower than that of the LO buffer

output power for the LO input power is -5 dBm and above. Thus, wider bandwidth can be

obtained for the MSTM than that of the adopted LO buffer. When an LO power of -5 dBm

is fed-in, the voltage conversion gain of the mixer drops by 1 dB at about 10 GHz from

its low frequency value, while the corresponding LO output power is around -8 dBm at 10

GHz. When the input LO power increases to -1 dBm, under the same LO buffer bandwidth,

the frequency at which the LO output power drops to -8 dBm is widened to around 23 GHz.

Correspondingly, the -1 dB bandwidth of the voltage conversion gain is extended to about

the same frequency of 23 GHz, as expected. In this work, the input LO power of -1 dBm is

adopted to achieve a flatter conversion gain.

The design parameters and the performances are summarized in Table 3.1 and 3.2,

respectively.

(2) Performance comparison with STM

To demonstrate the power efficiency of the proposed MSTM, an STM is designed with the

same 0.13 µm process to achieve the same bandwidth for comparison purposes. For a fair

comparison, the same supply voltage of 1.5 V, notwithstanding the fact that the STM can


Table 3.1: Overview of the Simulation Parameters Used for STM and MSTM mixers ofFig. 3.4.

Property MSTM STM

gm & Load (W/L)1−4 (W/L)9,10 RIF (W/L)1−4 (W/L)9,10 RIF

Devices 80/0.12 130/0.4 3 kΩ 80/0.12 130/0.4 3 kΩ

Switching (W/L)5,7 (W/L)6,8 (W/L)5,7 (W/L)6,8

& 45/0.12 15/0.12 30/0.12 15/0.12

Driving RB RF CB (W/L)11,13 (W/L)12,14 RF

Devices 400 Ω 3 kΩ 4 pF 90/0.12 28/0.12 150 Ω

Simulation Voltage LO Voltage LO

Parameters 1.5 V - 1 dBm 1.5 V - 1 dBm

work at lower supply voltages. The resistor RB in the MSTM inevitably reduces its voltage

headroom, which precludes its use in low-voltage environments−a conscious design trade-

off in order to improve energy efficiency. The same LO power is adopted for the two

mixers and the components sizes are chosen to be equal whenever possible, as summarized

in Table 3.1.

The schematic of the STM is shown in Fig. 3.4(b). With an input LO of -1 dBm,

buffers are needed to properly drive the switches up to 10 GHz. In the 0.13 µm process

used here, the time constant of the inverter is around 20 ps when driving the inverter of the

same size. Therefore, a simple inverter is not a suitable choice to implement the buffer.

Instead, a current-reuse complementary amplifier is adopted for design simplicity, as seen

in Fig. 3.4(b). With the bandwidth of STM guaranteed to be the same as the MSTM, the

sizes of the switches (M5−8) and the drivers (M9−12) are optimized for the least power


consumption.

The performances of the two mixers at 1, 4, 7 and 10 GHz are summarized in Table 3.2.

From the conversion gain variation over LO frequencies, it is found that the bandwidth of

the two mixers is approximately the same. With the same transistor sizes for the transcon-

ductors and the load, the two mixers demonstrate conversion gain and noise figure of the

same level. Because of the modulating effects of the gm by the LO when the transconduc-

tors are on, the IIP3 of the MSTM is 2-4 dB worse than that of the STM. What is more,

the simulated IIP2 with IF frequency of 250 MHz and two-tone spacing of 10 MHz is also

provided in Table 3.2. Although a degradation is observed compared to the STM, the IIP2

of the MSTM is still acceptable for the linear receiver. In wideband systems, for often

times the intermodulation products fall into RF band of interest before the downconver-

sion, which causes a severe deterioration of the IIP2. If possible, band-select filter can be

adopted at the front-end to mitigate the IIP2 requirements.

The power consumption of the MSTM is 8.25 mW, which consists of 3.75 mW for the

transconductance core and 4.5 mW for the LO buffer. The power consumption of the STM

also consists two parts, one for the mixer itself and the other for the LO driver. The mixer

itself consumes a static power of 3.75 mW for the transconductor and a dynamic power

for the switches, ranging from 0.78 mW at 1 GHz to 7.84 mW at 10 GHz (around 0.78

mW/GHz). The LO driver for the STM consumes a power of 9 mW.

If the STM is designed for a narrower bandwidth, the power-hungry LO driver can be

substituted with a much power-efficient inverter. What is more, the sizes of the switches

(M5-8) can also be decreased, so that even less dynamic power is consumed. In such a

manner, the STM is more power-efficient than the proposed MSTM. However, for the STM

to reach a bandwidth of 10 GHz requires 20.59 mW of total dc power, which is 2.5 times

3.3. IC IMPLEMENTATION 66

Table 3.2: Simulated performance of the STM and MSTM mixers of Fig. 3.4 for a fixed IF= 250 MHz.

MSTM STM

LO Frequency (GHz) 1 4 7 10 1 4 7 10

Conversion Gain (dB) 19.6 19.5 18.8 17.8 19.7 19.4 17.9 16.6

NF (dB) 4.3 4.4 4.7 5.4 4.4 4.8 5.9 6.9

IIP3 (dBm) -0.6 -2.6 -1.2 -1.1 4.3 3.2 2.5 1.7

IIP2 (dBm) 42.0 38.6 39.1 39.6 49.7 42.5 40.0 55.0

Pdis MSTM / Static for STM (mW) 3.75 3.75 3.75 3.75 3.75 3.75 3.75 3.75

Pdis dynamic for STM (mW) - - - - 0.78 3.14 5.49 7.84

Pdis LO Buffer (mW) 4.5 4.5 4.5 4.5 9 9 9 9

Pdis Total (mW) 8.25 8.25 8.25 8.25 13.53 15.89 18.24 20.59

more power than the MSTM needs to yield the same bandwidth.

From this performance comparison, it can be concluded that the MSTM renders com-

petitive performance compared to traditional STM when both are designed for wideband

operation with the same LO power. The MSTM is more power-efficient at the cost of the

reduced voltage headroom.

3.3 IC Implementation

A mixer RFIC using the proposed MSTM is designed and fabricated in a standard 0.13 µm

CMOS process and its schematic is provided in Fig. 3.7. The mixer core adopts the same

topology and design parameters used in the simulations in the previous section. Besides,

two modifications are made for the convenience of the testing as well as better performance.


Figure 3.7: Circuit schematic of the proposed mixer.

First, inductors (LG) are added at the gate of transconductor transistors to compensate the

gain and noise degradation in high frequencies caused by input parasitic capacitors. Sec-

ond, an IF output buffer is designed to convert the differential output to single-ended and to

provide the 50-ohm output impedance, which simplifies the testing. Distortion-cancelling

technique is used in the IF buffer to eliminate its non-linear effect to the mixer. The design

details and modelling of the chip are provided in this section.

3.3.1 Input inductive peaking

Although a flat voltage gain over a wide band is obtained, the mixer could still hardly

achieve wideband because of the pole introduced by the input capacitors of the mixer. As


Figure 3.8: Small signal half-circuit model of M1−4 with LG under test.

in foregoing description, the width of M1-4 is made relatively large for the best of the perfor-

mance. However, larger device width implies higher gate parasitic capacitances (dominated

by CGS), which introduces substantial loading effect to the preceding stage and deteriorates

the gain and NF.

To further enhance the performance at high frequency, inductors LG are added in series

with the gates of M1−4, as shown in Fig. 3.7. LG can mitigate the loading effect through

forming an inductive peaking network to delay the charging of the gate capacitors by the

preceding stage. In a single-chip receiver, LG is typically used together with the load induc-

tor of the preceding stage to form shunt-and-series or shunt-and-double-series peaking [97]

to trade the delay for the bandwidth. While in this work, as the proposed mixer is designed

as a stand-alone chip for research purposes, LG is adopted here to prevent CGS from loading

the signal source in the testing.

The small signal half-circuit of the transconductor stage is given in Fig. 3.8. As can be

seen, in the absence of LG, the source impedance RS/2 and CGS form a low-pass network,

which degrades its performance at high frequency. With LG added, RS/2, CGS and LG form

a series inductive peaking network. The value of LG is chosen based on tradeoffs between

the maximum bandwidth, the maximum flatness and minimum phase distortion [1]. For a


stand-alone chip, LG value that fulfills RS/2 =√LG/√CGS is preferred. In this way, LG

and CGS form an ”L” model of transmission line with characteristic impedance of RS/2,

which can be regarded as an ”extension” of the source impedance all the way to the gate

of the input transistors. Through the parasitic extraction, it is found that the CGS is around

125 fF, so 0.31 nH should be chosen for LG. In this work, a larger inductor of 0.5 nH is

adopted, so that the small gain drop due to the LO power drop at high frequency can be

compensated, too.

3.3.2 Quantitative analysis and simulation results

According to [95], the conversion gain expression of the switched transconductance mixer

is the same as current steering mixer. With the input network taken into consideration, the

conversion gain of the proposed mixer under test can be expressed as

ACG,V =c0gm,0RO√

(1− ω2LGCGS)2 + ω2(RS/2)2C2GS

(3.4)

where RO is the load resistance. c0 represents the nominal value of the voltage conversion

gain for the switching operation alone, and is equal to 2/π if the transition time is short

enough to be ignored [95, 98].

The calculated and simulated conversion gain curves with and without LG are shown

in Fig. 3.9(a). A good matching can be observed between the two, yet there is still some

deviation. This is because, gm,0, which is used in the calculation, is slightly different from

the actual effective transconductance. In this way, the trivial rolling-off of the conversion

gain caused by the LO drop, as depicted in Fig. 3.2(b), is not considered in the calculation.

Nevertheless, the calculated result can well describe the trend of the gain change and the

error is of limited amount.


The simulation result shows that a high gain of 19.5 dB is achieved and only around 1

dB drop is observed at 10 GHz with LG added. Comparing the curves of conversion gain

with and without LG, it can be observed that the gain at 10 GHz can be pulled up by around

1.5 dB.

The NF of switched transconductor mixers was analyzed before in [95], and the analysis

is analogous to that of Gilbert cell mixers [98]. Here we analyze the NF of this mixer using

the same approach [95,98], but withLG andCGS taken into account to capture the frequency

response. The thermal noise (Sn) at the output of the mixer (IF+ and IF− in Fig.3.7) is

given by:

Sn = α4kTRSg2

m[(1−ω2LGCGS)2+ ω2(RS/2)2C2

GS

]+ α4kT (2γgm) + α4kT (2γgmp) . (3.5)

A portion of which is due to the input source resistance:

Ssn = 4kTRS2c0

2g2m[

(1−ω2LGCGS)2+ ω2(RS/2)2C2GS

] . (3.6)

So the DSB noise factor (F) is given by:

F =Sn

Ssn=

α

2c02

+α

2c02

2rg

RS

+α

2c02

2γ

gmRS

[(1−ω2LGCGS

)2+ ω2 (RS/2)2C2

GS

]+

α

2c02

2γgmp

g2mRS

[(1−ω2LGCGS

)2+ ω2 (RS/2)2C2

GS

](3.7)

where gmp is the transconductance of M9−M10. γ is the excess noise factor and chosen


0 1 2 3 4 5 6 7 8 9 10 1116

18

20

22

24

LO Frequency (GHz)

Con

vers

ion

Gai

n (d

B)

With LG

Sim

With LG

Calc

Without LG

Sim

Without LG

Calc

(a)

0 1 2 3 4 5 6 7 8 9 10 112

3

4

5

6

7

8

9

LO Frequency (GHz)

NF

(dB

)

With LG

Sim

With LG

Calc

Without LG

Sim

Without LG

Calc

(b)

Figure 3.9: Simulated gain and NF of the mixer core with and without LG.


to be 1.33 for the calculation. α models the effective noise folding due to switching. It is

equal to the power of the (normalized) switched transconductance waveform, which varies

between +1 and −1 as the RF transconductors alternately turn on and the output current is

commutated. 0.4 is chosen for α here, and the term α/(2c20) in (3.7) therefore takes on a

value of 0.5.

The proposed MSTM inherits from the original STM topology the improved noise be-

havior relative to the active commutating-mixer. For STM, the switches are connected to

the common source terminals of the transconductor differential pairs. As a result, the noise

current introduced by the switching devices appears as common-mode at the mixer output,

which is rejected when the output voltage is taken differentially. Despite the topology dif-

ferences of the MSTM in the LO path, the position of the switching stage relative to the

transconductor stage of MSTM is the same as in the STM. Consequently, the noise cur-

rent from switching devices in MSTM also cancels in the differential output. This effect is

also revealed by (3.5) to (3.7), in which noise contributions from LO switches M5−M9, the

feedback resistors RF, the bias resistors RB are absent. Thus, similar to STM, lower output

noise (Sn) and NF is obtained with the MSTM.

The existence of LG can further reduce the NF at high frequencies as depicted in (3.7).

The calculated and simulated DSB NF curves of the mixer with and without LG are also

provided in Fig. 3.9(b). The simulation results are gotten with the IF output frequency kept

constant at 250 MHz, i.e. the input RF frequency is swept in tandem with the LO frequency.

As can be observed, the increase in NF at high frequency is diminished by LG prominently.

Quantitatively, the NF can be reduced by about 1 dB at around 10 GHz. A good agreement

between the calculated and simulated NF can be observed too.


Figure 3.10: Circuit schematic of the proposed IF output buffer.

3.3.3 IF buffer

An IF output buffer following the proposed mixer is designed on chip. The purpose of

having this buffer is to convert the mixer’s differential IF port (IF+ and IF-) to a single-

ended output, and to drive the relatively low impedance 50 Ω load in the testing. Since the

mixer has sufficient gain to make the buffer’s noise contribution negligible, this buffer is

optimized for linearity performance.

With these design considerations, an active current mirror with DS technique [61, 63–

65] is proposed to realize the IF output buffer, as can be seen in Fig. 3.7. The same

schematic is redrawn in Fig. 3.10 for the convenience of discussion. The active current mir-

ror is made of M11−12 and M15−17, and body-biased auxiliary transistors M13−14 are added

to cancel the third-order distortions and to improve the IP3 performance of the buffer.

With the body terminals of M13−14 biased at 2.4 V, their body-source voltage and thus


Table 3.3: Component Values for the IF Buffer

Transistor (W/L)11,12 (W/L)13,14 (W/L)15,16 (W/L)17

Size 30/0.12 110/0.12 250/0.12 60/0.4

Component RBB

Value 10 kΩ

the threshold voltage are increased, which decreases their dc current for weak channel in-

version. This changes the sign of the third-order transconductance of M13−14 from negative

to positive, which is now opposite to that of the NMOS devices M11−12 (biased in strong

inversion). Therefore the third-order distortion currents can be rejected upon summation at

the outputs. With the assistance of the two devices, the IIP3 of the buffer is improved from

16.1 dBm to 27.9 dBm.

The IF buffer has a 2 dB loss and 5 GHz 3-dB bandwidth at cost of 9.2 mA when

driving a 50 Ω load. As the IF amplifier is cascaded with the mixer, its common-mode

(CM) properties are also simulated. Without device mismatch, the gain from CM input to

the output is less than -40 dB up to 500 MHz. Furthermore, with 10% mismatch added

between the transconductor transistors M11 and M12, the same gain is simulated to be less

than -35 dB to 500 MHz. Considering the gain of the amplifier is -2 dB, a common-mode

rejection ratio of more than 33 dB is acquired. The transistor dimensions and passive

component values used are provided in Table 3.3.

Simulations show that the IF buffer has a 3-dB bandwidth of 5 GHz, which substantially

exceeds the IF output frequency band of the mixer (5 MHz to 500 MHz) chosen for this

work and, therefore, the buffer has negligible to no impact on the frequency response of

the mixer. Similarly, the IF buffer with an IIP3 of +27.9 dBm introduces only a minimal to


Table 3.4: Selected Simulation Results for Mixer Core & IF Buffer

Mixer Gain 1-dB Bandwidth DSB NF IIP3

Core 19.5 dB 1-10 GHz 4 - 5 dB -0.7 dBm

IF Gain 3-dB Bandwidth NF IIP3

Buffer -2 dB 5 GHz 8.8 dB 27.9 dBm

Figure 3.11: Photograph of Broadband Mixer IC.

negligible degradation to the distortion behavior of the mixer core, which shows an IIP3 of

-0.7 dBm and a conversion gain of 19.5 dB. A summary of the mixer core and the IF output

buffer’s simulated behavior is shown in Table 3.4.

3.4. MEASUREMENT RESULTS 76

3.4 Measurement Results

A photograph of the IC is shown in Fig. 3.11. It occupies a die area of 1 mm2 including

bonding pads, decoupling capacitors and the chip guard ring (plus chamfer regions), while

the core circuit area is 405 µm × 480 µm. The chip consumes 22.3 mW of power from a

1.5 V supply, in which the mixer core costs 8.25 mW.

The broadband mixer IC was measured directly on-wafer using 40 GHz coplanar waveg-

uide (CPW) probes and dc probes. A 50 GHz Keysight spectrum analyzer (E4448A) with

the NF measurement software was used for gain, NF and linearity measurements. Off-chip

bias-tee’s and dc blocking capacitors were employed at the RF input and IF output respec-

tively, in order to bias the IC and protect the measurement equipment. In addition, external

180 hybrids were used to provide differential RF and LO input signals from the single-

ended sources. For all simulations and measurements, the LO power was fixed at -1 dBm,

and the RF (fRF), LO (fLO) and IF (fIF) frequencies were chosen such that fRF = fLO + fIF.

Fig. 3.12 shows the measured gain and DSB NF of the mixer versus LO frequency

in comparison with the simulation results. In these measurements, the RF frequency was

swept in tandem with the LO frequency, keeping the IF frequency fixed at 250 MHz. The

measurements show that a high gain of 15.5 – 17.5 dB and a low NF of 4 – 5.2 dB are

achieved from 1 GHz to 10 GHz. The NF is as low as 4 dB at 7 GHz. These results

demonstrate that the RF 3-dB bandwidth of the mixer is quite wide, exceeding 10 GHz.

There is good agreement between the measured and simulated results.

The gain and DSB NF of the mixer was also measured over a broad range of IF fre-

quencies from 5 MHz to 500 MHz. Fig. 3.13 shows the results obtained at two different

LO frequencies of 4 GHz and 7 GHz. A peak gain of 21 dB is achieved at IF frequencies

below 100 MHz, and the IF 3-dB bandwidth is beyond 250 MHz. It should be noted that


0 1 2 3 4 5 6 7 8 9 10 1113

15

17

19

21

LO Frequency (GHz)

Con

vers

ion

Gai

n (d

B)

Meas. GainSim. Gain

(a)

0 1 2 3 4 5 6 7 8 9 10 112

3

4

5

6

7

LO Frequency (GHz)

NF

(dB

)

Meas. NFSim. NF

(b)

Figure 3.12: Measured mixer performance over LO frequency: (a) gain and (b) NF


0 100 200 300 400 50010

12.5

15

17.5

20

22.5

25

IF Frequency (MHz)

Con

vers

ion

Gai

n (d

B)

4 GHz7 GHz

(a)

0 100 200 300 400 500

3

4

5

6

7

IF Frequency (MHz)

NF

(dB

)

4 GHz7 GHz

(b)

Figure 3.13: Measured mixer gain (a) and NF (b) versus IF frequency at LO frequencies of4 GHz and 7 GHz.


0 1 2 3 4 5 6 7 8 9 10 11−40

−30

−20

−10

0

10

LO Frequency (GHz)

P1d

B &

IIP

3 (d

Bm

)

Meas. IIP3Sim. IIP3Meas. P1dBSim. P1dB

(a)

Figure 3.14: P1dB and IIP3 versus LO frequency.

the drop in gain observed at 5 MHz is largely due to the relatively high cut-off frequency

of the off-chip dc blocking capacitor (≈10 MHz).

The linearity performance of the mixer was characterized from 1 GHz to 10 GHz. First,

the measured P1dB and IIP3 are shown in Fig. 3.14. For these measurements, the RF fre-

quency was swept in tandem with the LO frequency, keeping the IF frequency fixed at

250 MHz. The frequency spacing between the two tones for the IIP3 measurement was 10

MHz. The measured P1dB reaches -14 dBm at 3 GHz and remains above -16 dBm out to

9 GHz. The IIP3 peaks to -1 dBm around the center of the band, but drops to about -4.2

dBm towards the edges. To put the measured P1dB and IIP3 performance in perspective, the

simulated results are also shown in Fig. 3.14.

What is more, the sensitivities of IIP3 performance to both IF frequency and two-tone

spacing are measured. Fig. 3.15 shows the results measured at two LO frequencies of 4


0 100 200 300 400 500−3

−1

1

3

IF Frequency (MHz)

IIP3

(dB

m)

4 GHz7 GHz

(a)

0 40 80 120 160 200 240−3

−1

1

3

Two−tone Space (MHz)

IIP3

(dB

m)

4 GHz7 GHz

(b)

Figure 3.15: Sensitivities of IIP3 to (a) IF frequency (b) two-tone spacing at LO frequenciesof 4 GHz and 7 GHz.


0 1 2 3 4 5 6 7 8 9 10 1140

45

50

55

60

65

70

LO Frequency (GHz)

LO−

to−

RF

Isol

atio

n (d

B)

Figure 3.16: Measured LO-to-RF isolation of the mixer.

GHz and 7 GHz. The sensitivities of IIP3 to IF frequency is measured with the two-tone

spacing is fixed at 10 MHz and the IF frequency is swept from 50 MHz to 500 MHz.

Within the whole range, the IIP3 for both 4 and 7 GHz are within -2 dBm to 0.5 dBm. The

sensitivities of IIP3 to two-tone spacing is measured with one tone fixed at IF frequency

of 250 MHz, and the other swept from 260 MHz to 470 MHz. The result shows that IIP3

varies by less than 2 dB within the range.

Fig. 3.16 shows the measured LO-to-RF port isolation. The isolation is around 60 dB

from 1 GHz to 8 GHz, and above 48 dB out to 10 GHz. Table 3.5 summarizes the proposed

mixer’s performance in comparison with other recently reported broadband CMOS mixers.

For comparison, the figure of merit (FOM) commonly used in the literature for broadband


Table 3.5: Summary of the mixer’s performance in comparison with other work

Reference CMOS Chip area DC power Gain Frequency DSB NF OIP3 FOM

process (mm2) (mW) (dB) (GHz) (dB) (dBm) (GHz)

[92] 130 nm 0.315 34.5 17.5 1–5.5 3.9 15.6 6.1

[93] 130 nm 0.13 16.8 14 0.87–3.7 2.7–6.5 4.04 0.5

[95] 180 nm 0.005 1.8 12 1–4 21.5 17 0.2

[99] 130 nm 0.13 20 11 1.0 15.9 16.0 7.0

[100] 180 nm 0.211 25.71 6.9 2–11 12.52 13.44 0.5

This Work 130 nm 0.2 8.3+145 15.5–17.5 1–10 4–5.2 16.5 116

1 Includes on-chip active wideband baluns.2 Estimated as single-sideband (SSB) NF minus 3 dB.3 With pads.4 Calculated as IIP3[dBm] + gain[dB].5 Power consumed by the mixer and the buffer, respectively.6 Mixer core + IF buffer. De-embedding simulated IF buffer data, the mixer core’s FOMis estimated at 26.6.

amplifiers and mixers [101, 102] has been applied:

FOM[GHz] =BW[GHz]×Gain[1]×IIP3[mW]

(NF[1]−1)×PDC[mW]

=BW[GHz]×OIP3[mW]

(NF[1]−1)×PDC[mW](3.8)

where BW [GHz] is the bandwidth in GHz, Gain [1] is the gain in magnitude, IIP3 [mW] is

the input third-order intercept point in mW, OIP3 [mW] is the OIP3 in mW, (NF [1]− 1)

is the excess NF in magnitude, and PDC [mW] is the dc power consumption in mW. FOMs

calculated with the power of mixer core and the whole chip are both provided. As can

3.5. SUMMARY 83

be seen from Table 3.5, the proposed mixer offers competitive performance over a broad

bandwidth while consuming a small amount of power, thus featuring a high FOM compared

to other work calculated in either way.

3.5 Summary

A low-power, low-noise, wideband mixer in 0.13 µm CMOS is presented in this chapter.

Based on STM structure, a transconductor stage with fixed DC operating point is switched

by the ac-coupled LO signal. In this way, only a small LO signal is required to turn the

transconductor on and off and thus a low-power LO buffer can be used to achieve 15.5 –

17.5 dB gain in 1 – 10 GHz bandwidth. As the noise power from LO stage appears in

common mode at the mixer output, low NF of 4 – 5.2 dB is realized, too. The mixer core

consumes a low power of 8.3 mW from 1.5-V supply, and the whole chip consumes 22.3

mW including the IF buffer. The active chip area is less than 0.2 mm2.

84

Chapter 4

A Highly Linear Gilbert Cell Mixer

4.1 Introduction

This chapter presents a feedforward linearization scheme to improve IIP3 of the active

downconversion mixers. In this scheme, IM2 is created and multiplied by the mixer’s out-

put to generate the low-frequency IM3 for the cancellation. Compared to the traditional

method in which IM3 is generated in RF frequency first and then down-converted for the

cancellation, the proposed method is mostly implemented in IF band and thus robust against

parasitic parameters and less power-consuming. What is more, the realization of the pro-

posed technique is largely independent on the mixer configuration, so that it can be applied

to any downconversion mixer configurations.

Ever-more stringent linearity performance is expected of single-chip mobile receivers

as the spectrum is increasingly crowded with interferers. For example in Wideband Code

Division Multiple Access (WCDMA) system, the receiver needs to support multiple bands

simultaneously [103, 104]. If adopting the popular frequency division duplexing (FDD)

and direct-conversion architecture (DCR), the WCDMA receiver also suffers from large

leakage from TX path. Without having the external pre-select or inter-stage filters, the


single-chip receiver must have high linearity to handle the in/out-of-band blockers, i.e. to

prevent the self-generated intermodulations from interfering with the signal of interest. For

the similar reason, in the emerging multi-mode single-chip receiver, rigorous linearity is

also required to deal with the coexistence of multiple radios like cellular and Wireless Local

Area Network (WLAN), where the blockers come from intra-device coupling [103–105].

Since the mixer is the last building block in the receiver front-end before the interferers

can be filtered off, its linearity requirement is the most stringent. Thus, plenty of efforts

have been made to improve the linearity of the mixers, as introduced in Chap. 2. While

they can bring significant improvement to the IIP3 of the mixer, they have drawbacks that

limit the applications under a lot of circumstances.

One method uses IM2 injection into the current source of the differential transconduc-

tance [66, 78]. The IM2 product mixes with the fundamental input signals to generate an

IM3, which cancels the intrinsic IM3 signal in the main path. This cancellation technique

introduces negligible extra NF and very low extra DC power. However, it can be only used

in the circuit where there is a differential pair with tail current source.

Another method uses the concept of derivative superposition (DS). Originally used

primarily for amplifier linearization, DS has also been applied to mixer linearization as

well [60–62, 64, 65, 79–81]. In this method, multiple input transistors with different bias

are designed in parallel. Under different biases, their third-order derivatives cancel with

each other so that a linear transconductance with less third-order distortions is acquired.

However, it is hard to apply this method at frequencies higher than around 1 GHz, because

at high frequencies, the second-order term of the devices will generate new third-order dis-

tortions with the help of the intrinsic feedback of the circuit. This issue is being actively

studied and inspiring results have been reported recently [65, 81].

4.2. PROPOSED LINEARIZATION TECHNIQUE 86

The feedforward technique in [83] is superior because of its use does not rely on the

mixer topology in the main path. In this method, a whole receiver is employed as the auxil-

iary path, in which the IM3 products are generated, down-converted to baseband, digitized,

and processed by an adaptive equalizer for canceling the IF band IM3 of the main path.

Although the dynamic range of the auxiliary path is much smaller compared to the main

path, the adoption of it still increases the power dissipation as well as the complexity of the

system drastically.

Compared to former state-of-art, the proposed method provides robust IIP3 improve-

ment against the parasitics with lower power dissipation and less dependence on mixer

configuration. To testify the proposed method, a 2 GHz current commutating mixer lin-

earized by the proposed technique is designed and demonstrated in this chapter. The lin-

earization technique achieves 12 dB IIP3 improvement to the mixer at the cost of an extra

current of 4.2 mA and 0.2 dB of noise penalty. In the following, the technique is first in-

troduced from the systematic perspective. Then, circuit implementations of key building

blocks are introduced. Furthermore, its application on the mixer are described with design

details, simulation and measurement results.

4.2 Proposed Linearization Technique

Feedforward scheme is capable of suppressing the nonlinearities without affecting the cir-

cuit topology, since it employs an additional parallel auxiliary path to cancel out the non-

linearities of the main path. As illustrated in Fig. 4.1(a), the nonlinear coefficients that

have same values and opposite signs to that of the main path are generated in the auxiliary

path. Through a linear combination, the nonlinear signal components of the two paths are

canceled out and the linear signal is obtained at the output.


A = a1vin + a3vin3

( a )

( b )

vin

A’ = a1’vin_ a3vin

3

vo = (a1 + a1’)vinA

A’

LO

Mixer Combiner

Main Path(Receiver)

Auxiliary Path (Linearization)

IM3

Generator

LO

Main Path(Receiver)

Auxiliary Path (Linearization)

IM3,L = 1- 2

IM3,H = 2- 1

Mixer

1+ LO 2+ LO

RF Band IF Band

IM3,L 1 2 IM3,H

IF Band

1 2

IM3,L IM3,H

IF BandIM3,L+ LO IM3,H+ LO

RF Band

Figure 4.1: Feedforward nonlinearity cancellation technique used (a) in the general case(b) in the case of down-converters


The feedfoward linearization technique can be applied to the downconversion mixer to

suppress its the third-order intermodulation terms, as illustrated in Fig. 4.1(b) [83]. In the

auxiliary path, IM3 around fundamental tones need to be generated for the compensation

first. And then, since the IM3 tones to be canceled at the mixer output are at IF frequencies,

the generated IM3 tones need to be down-converted by a mixer before the cancellation.

The method described above is typically power-inefficient and susceptible to the para-

sitics of the analog circuit. Aiming to solve these two problems, a novel scheme is proposed

in this work, in which the IM3 for the compensation is generated directly in the IF band,

which leads to an robust method against the parasitic parameters.

4.2.1 Proposed Feedforward Linearization

A block diagram of the proposed feedforward scheme is given in Fig. 4.2. As can be seen,

an auxiliary path for linearization is added in parallel to the original receiver. In the aux-

iliary path, a low-frequency IM2 product is generated from fundamental input signal first,

and then mixed with mixer output signal to generate an IF IM3 required for the cancellation

with the intrinsic IF IM3 signal in the main path. The combining of the mixer output and

the canceling IM3 can be achieved through reusing the stage appearing after the mixer in a

typical receiver architecture, for example, an op-amp-based IF amplifier or filter. From the

systematic perspective, the combiner used in the proposed technique does not add an extra

stage in the main path. The detailed operation principle and the spectrum at each node are

described assuming two-tone signal applied at the input.

Node A: Two RF signals are applied to the input of the mixer. For simplicity, the initial

amplitude and phase of the signal are assumed to be A0 and 0. The signal appearing at


Figure 4.2: The diagram of the proposed feedforward technique

node A can be expressed as

vA = A0cos(ω1 + ωLO)t+ A0cos(ω2 + ωLO)t (4.1)

in which the RF frequencies are expressed as the sum of IF and LO signals for the simpli-

fication of the notation.

Node B: The mixer converts the input RF signal to the IF band by an amount of the LO

frequency. Simultaneously, due to the third-order nonlinearities of the mixer, IM3 tones are

produced near the fundamental ones in the IF frequencies at the output of the mixer. The


signals within the band of interest at node B can be expressed as

vB = ACGA0cos(ω1t+ Φ1) + ACGA0cos(ω2t+ Φ2)

+3

4a3A0

3cos(ωIM3,Lt+ Φ3) +3

4a3A0

3cos(ωIM3,Ht+ Φ4)(4.2)

where

ωIM3,L = 2ω1−ω2 (4.3a)

ωIM3,H = 2ω2−ω1 (4.3b)

and ACG and a3 represent the conversion gain and the third-order nonlinear coefficient of

the mixer, respectively; Φ1∼4 represents the additional phase introduced to each tone by the

mixer.

Node C: In the auxiliary path, a low-frequency IM2 tone of the input signal is generated

first at node C, noted as

vC = a2A02cos(ω2 − ω1)t (4.4)

where a2 represents the second-order coefficient of the IM2 generator. As the IM2 tone stays

at low frequency, its phase shift due to parasitic capacitors of the circuit can be ignored here

without losing accuracy. In fact, this phase shift determines the frequency spacing of the

blockers the proposed technique can deal with, which will be discussed in details in next

section.

Node D: The baseband multiplier multiplies the baseband signals at Node B by those at

Node C, generating four third- and four fifth-order tones located around the fundamental

tones of the mixer output. Since the fifth-order products are small and also not related with

IM3 cancellation, they are neglected here and their effects will be discussed later. Here


without losing accuracy, only third-order products at node D are listed, as

vD ≈AIM3cos(ω1t+ Φ2) + AIM3cos(ω2t+ Φ1)

+AIM3cos(ωIM3,Lt+ Φ1) + AIM3cos(ωIM3,Ht+ Φ2)

(4.5)

where

AIM3 = 1/2Kma2ACGA03 (4.6)

and Km is the multiplying gain of the baseband multiplier. The phase shift of this operation

is ignored too since it is also in the IF band.

Node E: Signals at Node D are fed back to the main path and added with the mixer output

through a combining circuit to cancel the IM3 tones. Assuming a unit gain of the combiner,

the signals at Node E can be expressed as

vE = ACGA0cos(ω1t+ Φ1) + AIM3cos(ω1t+ Φ2)

+ACGA0cos(ω2t+ Φ2) + AIM3cos(ω2t+ Φ1)

+3

4a3A0

3cos(ωIM3,Lt+ Φ3) + AIM3cos(ωIM3,Lt+ Φ1)

+3

4a3A0

3cos(ωIM3,Ht+ Φ4) + AIM3cos(ωIM3,Ht+ Φ2)

(4.7)

The condition for complete IM3 cancellation is clear: the corresponding tones at same

frequencies should have the same amplitude and 180 of phase difference. Referring to


(4.7), this requirement can be translated to the following conditions:

a3 = −2

3Kma2ACG (4.8a)

Φ1 = Φ3 (4.8b)

Φ2 = Φ4 (4.8c)

4.2.2 Discussions on cancellation condition

The cancellation condition in (4.8) reveals alignment requirements of two aspects for the

IM3 tones between the main and auxiliary paths: the amplitude and the phase.

The amplitude alignment, expressed by (4.8a), can be fulfilled by adjusting a2 of the

IM2 generator and Km of the multiplier in the auxiliary path, with ACG and a3 regarded

as constants once the mixer in the main path is designed. Since the entire circuits are

implemented in the differential manner, “–” in (4.8a) can be easily realized by reversing

the positive and negative terminals while combining the signals of the two paths. Note that

the original and the canceling IM3 are both in the third order of input amplitude, and all the

parameters in (4.8a) are device-related and have nothing to do with the input amplitude. In

this way, if (4.8a) is fulfilled, the effective cancellation over wide range of input power can

be achieved because the injected signal automatically tracks with the input signal.

The phase alignment requirement consists of two parts. The first part is explicitly ex-

pressed by (4.8b) and (4.8c). The second part is the validation of the assumption used in

the above derivation for many times, i.e. the phase shifts introduced to the signal of interest

by the auxiliary path can be ignored.

The first part expressed by (4.8b) and (4.8c) originates from the intrinsic working prin-

ciple of the proposed method. In this method, fundamental outputs of the mixer are used to


produce IM3 terms for the compensation, along with which their phases shifts (Φ1, Φ2) are

introduced to IM3 terms, too, as explained in (4.5). Thus, from (4.8b) and (4.8c), it appears

that only if the phases of generated IM3 need to be equal to that of their counterpart (Φ3,

Φ4) from the main path, a complete cancellation can be achieved.

Conditions in (4.8b) and (4.8c) can be met spontaneously if the two input tones are

located close to one another. Although Φ1 ∼ Φ4 of the mixer depends on many factors,

such as working frequency, nonlinearities, and the loading effects at the mixer output, the

four tones of the output located at ω1, ω2, ωIM3,L and ωIM3,H experience approximately equal

phase shifts regardless of the circuit topology if the two input tones are located close to

one another, i.e. Φ1 ≈ Φ2 ≈ Φ3 ≈ Φ4. With the increase of two-tone space, the phase

differences among Φ1 ∼ Φ4 start to increase and the IM3 cancellation will thus degrade.

However, the in-band blockers and even the out-of-band blockers are often relatively close

to signal of interest for most of the protocols. Within the required frequency range for these

protocols, the proposed technique are still working effectively.

The second part, i.e. the phase shift assumption, is reasonable because signal of interest

is in the auxiliary path are in the IF band. If the bandwidth of the auxiliary path designed

properly, the phase shift introduced from the auxiliary circuitry to the signal of interest can

be limited to a small range, which does not severely affect the IM3 cancellation. It will be

further described by the circuit description in Section 4.3 and proved by the design example

in Section 4.4.

4.2.3 Effects on Gain and IIP5

While producing IM3 for cancellation, the auxiliary path also generates other tones that

can affect performances of the main path, such as gain and fifth-order input intercept point


1 2IM3,L IM3,H

IM5,L IM5,H

D

E

1 2IM5,L IM5,H

IM3,L = 1 - 2

5th-order Tones

3rd-order Tones

1st-order Tones

IM5,H = 2 - 2 1

IM3,H = 2 - 1

IM5,L = 1 - 2 2

Figure 4.3: The spectrum at Node D with 5th order terms considered

(IIP5). As can be observed from both Fig. 4.2 and (4.5) in Section 4.2.1, two tones located at

ω1 and ω2 are generated along the IM3 for the cancellation. What is more, in the description

of the signals at Node D, only the third-order products related to IM3 cancellation were

included for the simplicity of the discussion. In fact, four fifth-order terms are generated at

the same node simultaneously, which can be expressed as

vD,IM5 = AIM5cos(ω1t+ Φ3) + AIM5cos(ω2t+ Φ4)

+AIM5cos(ωIM5,Lt+ Φ3) + AIM5cos(ωIM5,Ht+ Φ4)

(4.9)

where

AIM5 = 1/2Kma2a3A05 (4.10)

4.3. KEY BLOCKS 95

and

ωIM5,L = 3ω1−2ω2 (4.11a)

ωIM5,H = 3ω2−2ω1 (4.11b)

The spectrum at Node D and Node E are redrawn in Fig. 4.3 with all these terms considered,

As can be observed, both the gain and IIP5 are affected by the adoption of the auxiliary path.

However, the effects on both the conversion gain and IIP5 can be neglected without

losing accuracy. To prove it, a quantitative example is provided here. Suppose a two-tone

input signal of -20 dBm is applied at a baseline mixer with an IIP3 of 0 dBm. Then at

the mixer output, the IM3 is 40 dBc below the fundamental tone. Since the generated IM3

tones are in the same order as the uncompensated IM3 of the main path, the largest effects

of these terms on the fundamental tone is around 0.09 dB. Furthermore, AIM5 is smaller

than AIM3 by the same amount of AIM3 to the amplitude of the fundamental tones, which is

40 dBc, too. Therefore, the effect of the IM5 tones is negligible, too.

4.3 Key Blocks

One advantage of the proposed method is that all the operations required in the proposed

technique can be realized either by the circuit topologies reported in the former state-of-

the-art [66,106,107], or by reusing the existing blocks in the receiver. In the following, the

circuit implementation of the key blocks in the proposed diagram of Fig 4.2 are described,

with the key factors in (4.8a) expressed with the device parameters.

4.3. KEY BLOCKS 96

Figure 4.4: Diagram of IM2 generator: (a) building block (b) circuit schematic

4.3.1 IM2 Generator

Based on (4.4), the IM2 generator needs to produce a low-frequency IM2 tone that is in-

phase with the envelope of the input RF signals and proportional to the square of the input

magnitude. Its signal flow diagram is provided in Fig. 4.4(a). As can be seen, the input

signal first goes through a 2nd-order distorter to produce all the second-order harmonics

and intermodulations, and then through a tone selector to pick out the low-frequency IM2

tone among them.

Although appearing as a separate stage in Fig. 4.4(a), the tone selector can be imple-

mented within the distorter circuit. To explain this, suppose the two-tone RF input signals,

4.3. KEY BLOCKS 97

ω1 and ω2, are located at 2.01 and 2.02 GHz. Consequently, the desired IM2 tone ω2 − ω1

is located at 10 MHz, while other second-order tones, including 2ω1, ω1 +ω2, 2ω2 and DC,

are located at 4.02, 4.03, 4.04 and 0 GHz, which can all be well distinguished from 10

MHz. Obviously, the high frequency second-order tones can be easily filtered out by the

low-pass filter integrated at the load of the distorter, and the DC tone can be eliminated by

the inter-stage bias circuit.

The above numerical example also reveals that the high frequency second-order tones

are typically far apart from the desired IM2 tone. As a result, they can be easily filtered

out without introducing significant phase shift to the tone of interest if proper pole position

of the low-pass filter is selected. Thus, in the following circuit analysis, it can be safely

assumed that no phase shift is introduced to the IM2 tone of interest from filtering.

Based on the above analysis, the IM2 generator circuit is proposed, as shown in Fig. 4.4(b).

As seen, The 2nd-order distorter is implemented by a squaring circuit, which is composed

of M1∼M3, R1 and C1. The drain current of M1 and M2 can be expanded using Taylor

series [66], as

in = g1(vg − vs) + g2(vg − vs)2 + g3(vg − vs)

3 + · · · (4.12)

where gi represnts the ith-order transconductance coefficient of the device, which are given

by

g1 =∂IDS

∂VGS, g2 =

1

2!

∂2IDS

∂V 2GS, g3 =

1

3!

∂3IDS

∂V 3GS. (4.13)

If the differential two-tone input signal, as in (4.1), is appled to the squaring circuit, the

fundamental tones will be canceled at the output while the common-mode second-order

4.3. KEY BLOCKS 98

tones remain and can be expressed as

vout,2nd = (A0cosω1t+ A0cosω2t)2

× (−2g2,M1)× [R1//(sC1)−1]

(4.14)

where gi,Mj represents the ith-order transconductance coefficient of Mj . As already ex-

plained above, with proper design of R1 and C1 as well as the DC block C4, the desired

low-frequency IM2 tone can be selected without phase shift, expressed as

vout,2nd|ω2−ω1 = −2g2,M1R1A20cos(ω2 − ω1)t. (4.15)

Since the squaring circuit produces a single-ended output, an active balun is used to

recast the low-frequency IM2 tone to the differential manner, which is composed of M4,

R2, R3 C2 and C3 in Fig. 4.4(b). As can be seen, to further attenuate the unwanted second-

order tones at RF frequency, RC networks are used at both outputs of the balun, too. The

transfer functions of the balun for the two paths are approximately expressed as

AB+ = − gm,M4R2

1 + gm,M4R3× 1

1 + sR2C2, (4.16a)

AB− =gm,M4R3

1 + gm,M4R3× 1

1 + s R31+gm,M4R3

C3. (4.16b)

To guarantee a balanced differential output, R3 = R2 and C3 = (1 + gm,M4R3)C2 must be

fulfilled. Similar to R1 and C1, with the pole position of the balun designed properly, the

phase shift on the low-frequency IM2 tone can be ignored. Thus, the differential output

signal becomes

vIM2 =4g2,M1gm,M4R1R2

1 + gm,M4R2× A2

0cos(ω2 − ω1)t. (4.17)

4.3. KEY BLOCKS 99

Comparing (4.17) with (4.4), the desired IM2 with an amplitude proportional to A20 is

obtained, and the second-order coefficient of the IM2 generator corresponding to α2 in (4.4)

can be written as

α2 =4g2,M1gm,M4R1R2

1 + gm,M4R2. (4.18)

Note that although phase shift introduced to the desired IM2 tone is negligible with proper

design, it can be large enough to affect the cancellation when the two tone space (ω2 − ω1)

is sufficiently large.

4.3.2 Baseband Multiplier

Based on (4.5), the baseband multiplier multiplies IM2 tones by the mixer output to produce

IM3 for cancellation, which is desired to be proportional to the cubic of the input magnitude

with no extra phase shift introduced during the multiplication.

Fig. 4.5 provides the schematic of the multiplier. As can be seen, this topology uses the

square law of the MOS transistors M1 ∼ M4 to realize multiplication. One set of analog

multiplicator is fed to the gates of squaring transistors directly, while the other is fed to

the sources of same transistors through a pair of source followers consisting of M5 ∼ M8.

Double-balanced structure is used in the multiplier to cancel out all the higher order and

common-mode signals appearing at the output. R1 and R2 converts the output current into

voltage. The multiplying coefficient corresponding to (4.6) can be approximately expressed

as [106, 107]

Km = −µnCox

(W

L

)MiRj (4.19)

in which(WL

)Mi represents the dimension of squaring transistors M1 ∼ M4 and Rj repre-

sents the load resistance R1 and R2.

4.3. KEY BLOCKS 100

Figure 4.5: Circuit schematic of the baseband multiplier

Similar to IM2 generator, the phase shift introduced to the output IM3 tone by the mul-

tiplier can be neglected, too. For the proposed topology, the dominant pole is located at the

output, which consists of the load resistors (R1 and R2) and the parasitic capacitor at the

same node. With sufficient current assigned to the multiplier, dominant pole frequency can

be far from the that of output signal, and thus brings negligible phase shift. This analysis

will be further proven by the simulation results provided in Section 4.4.2.

4.3.3 Signal Combiner

Based on (4.7), the combiner adds output signal of the mixer and that of the auxiliary path

to realize the IM3 cancellation. Because the combiner is subsequent stage of the mixer,

its linearity requirement is rigid to prevent more IM3 terms from being generated during

the signal combination. To quantitatively acquire the linearity requirement, suppose the

proposed technique is applied to a mixer with 10-dB gain and 0-dBm IIP3. Even if the

generated IM3 tones from the auxiliary path are identical in amplitude and 180 out of

4.3. KEY BLOCKS 101

vout+

vout _vx

_

vy _

vx+

vy+

Rf

RfR1

R2

R1

R2

Figure 4.6: Circuit schematic of the signal combiner

phase to the IM3 of the mixer, the combiner still requires an IIP3 of as large as 20 dBm to

achieve an 10-dBm IIP3 improvement for the mixer.

Op-amp-based adder is adopted here to function as the signal combiner, because it

demonstrate superior linearity performance resulting from the use of strong feedback. As

shown in Fig. 4.6, suppose two sets of differential signals, denoted as vx and vy, are applied

at the input, the output of the combiner can be expressed as

vout = −Rf(1

R1vx +

1

R2vy). (4.20)

If Rf = R1 = R2 is fulfilled, the operation expressed in (4.7) is obtained. Obviously, the

weights of vx and vy can be adjusted during combination by controlling the ratio of R1 to

R2.

The fully differential operational amplifier can be realized with the widely-used op amp

circuit shown in Fig. 4.7. As can be seen, it is a two-stage amplifier, with a cascode structure

(M1 - M11) for the first stage and common-source (M12 - M15) as the second. In order to

enlarge the voltage headroom at output, a folded configuration is adopted in the first stage

as well. Miller capacitors C1 and C2 in the second stage are used to compensate the phase

margin for the stability considerations. The common-mode (CM) feedback circuit consists

4.3. KEY BLOCKS 102

V b3

V b2

V b1

V in+

V in-

V out+

V out-

V CM

V dd

V ss

M1

M2

M3

M4M

5

M6

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

R 1 R 2

C3

C4

C1

C2

Figure 4.7: The schematic of the op amp in combiner

4.3. KEY BLOCKS 103

BlockerCW

f

| |Interference

IM3 for Cancellation

Signal

f

Transfer Function

Mixer Output

IM3 for Cancellation

| |

(a)

(b)

Figure 4.8: Transfer function of the combiner illustrated in output spectrum, (a) for two-tone test and (b) for the receiver where IF amplifier/filter is re-used

of a CM level sense circuit (R1, R2, C3 C4) and an active current mirror as the comparator

(M16 - M20).

Although the adoption of op-amp-based adder seems more power-consuming than us-

ing current-mode transconductor-based adder, it is actually power-efficient from systematic

perspective, since the op-amp-based adder can be realized through reusing the subsequent

stage of the mixer in a practical receiver design. In a typical receiver architecture [104], the

mixer is usually followed by IF amplifiers or filters made of op-amp-based circuits, which

can be readily modified to realize the signal combination without affecting their original

functions.

In the above analysis, IIP3 based on two-tone test is the main indicator of the proposed

4.4. CHIP DESIGN DETAILS 104

linearization technique. To get a complete two-tone test result with an accurate IIP3 value,

the combiner needs to demonstrate a flat gain over the frequency covering all the four

output tones, as illustrated in Fig. 4.8(a). As the increase of two-tone space, the bandwidth

requirement of the combiner increases drastically. However, in practical communication

system, the two fundamental tones of the two-tone test actually represent the two blockers,

and the channel of interest is located at where one of the IM3 tone is, as illustrated in

Fig. 4.8(b). Thus, although the IF amplifier/filter in the transceiver re-used as combiner

only covers the band of interest, the proposed scheme is still able to suppress the IM3

tones overlapping on the channel of interest, which is unrelated to the two-tone spacing

frequency.

4.4 Chip Design Details

As a proof of concept, the proposed linearization technique is applied to a 2-GHz Gilbert

mixer to improve its IIP3 performance. The detailed schematic of the proposed circuit is

shown Fig. 4.9.

4.4.1 Mixer Design

The mixer to be linearized adopts a Gilbert cell configuration with its tail current source

omitted, as shown in Fig. 4.9. Although losing some common mode rejection capability due

to the absence of the tail current source, this mixer can work under lower supply voltage,

and is thus widely used in the low voltage applications [42, 108, 109].

This mixer topology is adopted as it is a good example to show the versatility of the

proposed technique. The implementation of many linearization techniques relies on the

configuration of the mixer. For instance, the IM2 injection method [66, 78] needs to inject


Vdd

Vb4

Vb5

Vb0

Vss

v in+

v in

_

Vdd Vss

v LO+

v LO

_

Vb6

Vb6

Vb8

Vb7

Mix

er

Bas

eban

d M

ulti

plie

r

IF A

mpl

ifie

r (C

ombi

ner)

v out

+

v out

_

IM

2G

ener

ator

2nd

-ord

er D

isto

rter

& T

one

Sel

ecto

rA

mpl

itud

e A

djus

tor

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

R33

R35

R7

R8 R9

R17

R18

R19

R20

R21

R23

R22

R24

R25

R26

R10

R11

R12

R14

R13

R16

R15

R27

R28

R29

R30

R31

R32

C7

C8

C9

C10

C11

C12

C14

C13

C15

C16

Vb3

R6

R5C5

C6

Vb2

R4

R3

C3

C4

Vb1

R2

C1

C2

R1

R34

R36

Aux

ilia

ry P

ath

(L

inea

riza

tion

)

Mai

n P

ath

(R

ecei

ver)

Figure 4.9: The circuit implementation of the proposed feedforward technique


IM2 distortion into the tail current source, and thus can be hardly applied to the mixer used

in this work. However, the proposed scheme can be used to linearize this mixer without a

problem, as its application does not depend on the mixer configuration.

The mixer simulates a conversion gain of 8.7 dB and an IIP3 of 2.9 dBm. Translating

these performance specifications to the parameters used in the derivation of Section 4.2.1,

it can be gotten that ACG and a3 are equal to 2.7 and 18.5, respectively.

4.4.2 Linearization Path Design

As shown in Fig. 4.9, the circuit topologies discussed in Sec. 4.3 are adopted to implement

the blocks in the auxiliary path shown in Fig. 4.2. The design target is to generate proper

values for Km and a2 so that (4.8) can be fulfilled. Simultaneously, the phase shift intro-

duced to the signal of interest is desired to be as small as possible over the two-tone space

range from 1 MHz to 20 MHz.

1) IM2 Generator

In addition to the circuit configuration proposed in Section 4.3.1, a variable gain amplifier

(VGA) is supplemented to adjust the amplitude of IM2 tone, forming the IM2 Generator

used in the chip, as can be seen in Fig. 4.9. Two goals are mainly considered during the

design. First, the second-order coefficient of IM2 generator (a2 in Section 4.2.1) with large

tuning range is desired. Second, phase shift introduced to the IM2 tone should be negligible

over a reasonable two-tone spacing frequency.

Before demonstrating the design details, to provide an intuitive illustration of IM2 Gen-

erator’s working principle, the transient waveforms of its input and output are provided in

Fig. 4.10. In this plot, two-tone signals are applied at the input with the tones located at


−0.05

0

0.05(V

)Input differential signal

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16−0.01

−0.005

0

0.005

0.01IM

2 generator output differential signal

time(μs)

(V)

Figure 4.10: Simulated input and output signals of IM2 generator.

2.25 and 2.35 GHz, respectively, both with a strength of -22 dBm. Comparing the input

and output waveforms, it can be observed that the generated IM2 tone is in-phase with the

envelop of input signals.

The second-order coefficient a2 can be adjusted through tuning the bias of squaring

devices (M7, M8) and controlling the gain of VGA. With M7 and M8 designed to be 24-

µm/0.12-µm, g2 versus VGS are plotted in Fig. 4.11. To obtain a wide tuning range for g2,

the transistors are biased at around the middle of slope (0.4 V), at which g2 of around 0.018

A/V 2 is acquired. The VGA, which is realized by a differential common-source amplifier


Figure 4.11: Simulated g2 versus VGS of M7 and M8 in Fig. 4.9.

with resistive source degeneration, provides 8 gain steps from -4.9 dB to 2.8 dB with a step

size of approximately 1.1 dB. Based on these settings, a2 is equal to 4.80 with the gain of

VGA set to -1.6 dB. Taking the tuning capability of the VGA into consideration, a2 ranges

from 3.16 to 8.15.

The phase shift introduced to the desired IM2 tone mainly results from filters used to

attenuate the unwanted IM2 tones at other frequencies. Along with the signal path of IM2

tone in the IM2 generator, there are three first-order low-pass filters located at the load of

each stage (consisting of R7 and C7 , R8,9 and C8,9, R17-20 and the parasitic capacitors at

the same nodes); and three high-pass filters at the biasing circuit of each stage (consisting

of R5 and C5, R10 and C10, R11,12 and C11,12, R13,14 and C13,14). In order to get IF IM2 tone

with negligible in a wide frequency range, the poles of low- and high-pass filters are chosen

to be 1.5 GHz and 30 kHz respectively. Consequently, the phase shift on the IM2 of interest

is less than 10 when the two-tone spacing is in the range of 1 to 50 MHz, as indicated

in Fig. 4.12. At the same time, an attenuation of 9 dB on the unwanted second-order


0 10 20 30 40 50−6

−2

2

6

10

Two−Tone Spacing Frequency (MHz)

Pha

se s

hift

(deg

ree)

Figure 4.12: Simulated phase shifts introduced by the IM2 Generator

harmonics at around 4 GHz can be realized. Obviously, the pole position can be adjusted

to meet the different two-tone bandwidth requirements, which in turn causes changes in

out-of-band suppression and power consumption as a trade off.

In addition, the balance of the active balun in IM2 generator is easy to achieve, because

IM2 tone of interest is located at relatively low frequency. With R8 and R9 designed to be

equal, and C9 to be 30 fF larger than C8, the positive and negative output of the active balun

are well balanced. The amplitude and phase imbalance of the two outputs are plotted in

Fig. 4.13. As can be seen, the amplitude and phase imbalances are limited into 0.005 dB

and 0.15 over the two-tone spacing frequency 0 to 50 MHz. It can be safely assumed that

the two branch are perfectly balanced within the operating bandwidth.

2) Baseband Multiplier

The multiplier used in the chip adopts the exact topology proposed in Section 4.3.2, as

seen in Fig. 4.9. Two goals are mainly considered during the design. First, good linearity


0 10 20 30 40 500.000

0.001

0.002

0.003

0.004

0.005

Two−tone Spacing Frequency (MHz)

Am

plitu

de Im

b. (

dB)

0 10 20 30 40 500

0.03

0.06

0.09

0.12

0.15

0 10 20 30 40 500

0.03

0.06

0.09

0.12

0.15

Pha

se Im

b. (

degr

ee)Amplitude Imbalance

Phase Imbalance

Figure 4.13: Simulated imbalance of the active balun in Fig. 4.9.

is desired to be guaranteed, so that the amplitude of output IM3 tone can be proportional

to the cube of the input RF signal’s amplitude. Second, the phase shift introduced by the

multiplier should be small.

Two measures are taken to enhance the linearity of multiplier. First, proper transistor

sizes are selected to suppress the source of nonlinearity. For the adopted topology, the main

contributor of the nonlinearity is gate-to-source voltage variation of the source followers

when the current of squaring transistors varies. Thus, the transistor sizes of the source fol-

lowers (M17-18) are chosen to be 60-µm/0.12-µm, which are much larger than that of the

squaring circuits (M19-22, 30-µm/0.12-µm). In this way, the gate-to-source voltage variation

of the source followers is less affected by the the current through the squaring transistor.

Second, from systematic perspective, the mixer output signal is attenuated by 12 dB atten-

uation through a voltage divider before arriving at the multiplier, as illustrated in Fig. 4.9,

which prevents the multiplier from being saturated by large blockers at the input.

As a result, the generated IM3 tone is proportional to the cube of the input RF signal’s

amplitude in a large power range. Fig. 4.14 plots the power of IM3 at multiplier output


−30 −25 −20 −15 −10−100

−80

−60

−40

−20

Input RF Power (dBm)

Out

put I

M3 P

ower

(dB

m)

3dB/dB

Input = −13 dBm

Figure 4.14: Power of IM3 at multiplier output versus RF input of the chip

versus RF input of the chip. As can be observed, the output power increases at a slope of

3dB/dB when the input power is in a reasonable range. As the input power keeps increasing,

the curve starts to compress and reach 1 dB compression point eventually when the input

power is up to -13 dBm. However this is already sufficient large for the in-band blockers

in most of the wireless receiver applications.

To guarantee the negligible phase shift, the dominant pole of the multiplier is designed

to be as large as 1050 MHz. The phase shift introduced by the dominant pole of this value

is plotted in Fig. 4.15. As can be seen, the phase shift is less than 6, even when the

output frequency is up to 200 MHz, and only less phase error is thus introduced when the

frequency of output tone is smaller. Thus, phase error from multiplier can barely degrade

the cancellation. Taking 12 dB of attenuation into consideration, the equivalent Km gotten

in this design is around 2.3.


Figure 4.15: Simulated phase shifts introduced by the multiplier

3) Combiner Design

In this work, IIP3 based on two-tone test is the main indicator to demonstrate the effective-

ness of the proposed linearization technique. Thus, to get an accurate two-tone test result,

the combiner needs to demonstrate a flat gain over the frequency that covers all four output

tones. Here, two-tone test result are expected to be observed for a two-tone space from 1

to 20 MHz. With the IF set at 25 MHz for the mixer, a flat gain of the combiner from 1

MHz to 65 MHz is needed. To meet this requirement, a fully differential, two-stage op amp

configuration is adopted. A DC gain of 55 dB and a GBW of 430 MHz is designed for the

op amp. With R27-32 all set to 4 kΩ, a unit gain is achieved with less than 0.2-dB drop up

to 80 MHz.

4.4.3 Simulated IIP3 Improvement on PVT Variation

While a considerable IIP3 improvement is achieved by the design described above, the

extent of the improvement can be affected by the PVT variations.


Table 4.1: IIP3 Improvement versus Process Corners

TT SS FF FS SF

∆IIP3 (dB) w/o calibration 12.0 9.1 6.7 7.7 10.0

∆IIP3 (dB) w/ calibration 12.0 15.8 12.2 13.2 14.9

(VGA control bits) (011) (100) (010) (010) (100)

Simulations are conducted to examine the effects of PVT variations, and the results

are summarized in Tables 4.1 and 4.2. In each table, IIP3 improvements with the VGA

configured for the optimal performance of the nominal condition (TT corner and 27C)

are listed first. Then the results with VGA tuned to calibrate the chip are demonstrated

to explore the best possible performance under different conditions. In these simulations,

current mirrors with the temperature-independent constant reference current sources are

used to bias all the building blocks in the chip.

As revealed by the amplitude alignment condition expressed in (4.8a) as well as (4.18),

the proposed technique relies on the I-V characteristics of the active devices and their

derivatives gm, g2 and g3. For SS and FF corners, Vth drifts around ±20mV from its typical

value of 420 mV, which causes inaccuracies of the values for the corresponding I , gm, g2

and g3 . As a consequence, the amplitude alignment and the IIP3 improvement degraded, as

shown in Tables 4.1. However, at least 6.7 dB of IIP3 improvement can still be achieved un-

der different corners. What is more, with the assistance of the VGA, the IIP3 improvement

can be brought back to above 10 dB.

The variations in the resistor and the capacitor would inevitably cause both phase and

amplitude variations on the IM3 tones and thus degrade the IIP3 improvements.

First, the amplitude alignment is affected by the variations in the load resistors of each


Table 4.2: IIP3 Improvement versus Temperature

−40C 0C 27C 50C 80C

∆IIP3 (dB) w/o calibration 0.0 4.0 12.0 7.5 4.7

∆IIP3 (dB) w/ calibration 3.2 12.3 12.0 14.1 19.0

(VGA control bits) (000) (000) (011) (101) (111)

building blocks. Simulations are conducted with the resistors adjusted to +3σ, which corre-

sponds to 11% variation from their typical values. The results shows that with the two-tone

spacing located at the 4 MHz, i.e. the middle band of the auxiliary path (effects of the

resistors to the phase alignment can be neglected), the IIP3 improvements degrades from

12 dB to 11 dB. Small degradation is observed since the resistors are adopted as the load

for the circuits in both the main and the auxiliary path, and the effects from the resistor

variations can cancel to each other to some degree.

Second, the phase alignment is also affected by the variations of both the resistors and

the capacitors. Simulation shows that with both the resistors and mimcaps adjusted to

+3σ(corresponding to about 11% variation from their typical value), the simulated optimal

two-tone spacing for the IIP3 improvement shifts from 4 MHz to 2 MHz. Additionally, at

the two-tone spacing of 1 MHz, the IIP3 improvement increases by from 9.7 to 11.6 dB,

while at 20 MHz, it decreases from 10.5 dB to 9.7 dB.

In the 0.13µm process used in this design, the temperature coefficient of the poly resis-

tors is around−1.17e-3, and |Vth| for the active MOSFET changes from 420 mV to 480 mV

from 27C to 80C. The IIP3 improvements as a function of the temperature are listed in

Tables 4.2. As can be observed, the IIP3 improvements degrades as the temperature moves


Figure 4.16: Die micrograph of the mixer

to extremes. However, with the calibrated of the VGA, the IIP3 improvements degrada-

tion can be brought back. The corresponding control bits of the VGA used under different

temperatures are listed, too.


The mixer was fabricated in a standard 0.13µm CMOS process. The whole chip occupies

an area of 1.2 × 2 mm2, in which the active area is 0.3 × 1.4 mm2. The micrograph of the

chip is shown in Fig. 4.16.

For comparison, the auxiliary path is turned on and off to enable and disable the can-

cellation. In both on and off mode, the IF amplifier (combiner) is in series to the mixer. As

the IF amplifier is an unit-gain amplifier with a simulated IIP3 of above 35 dBm, its effects

to the gain and IIP3 of the mixer in both cases are negligible during the measurement.

The mixer is measured with an LO of -2 dBm located at 2 GHz. The mixer and the IF


−20 −15 −10 −5 0 5 10 15−80

−60

−40

−20

0

20

40

Input Power (dBm)

Out

put P

ower

(dB

m)

Fundamental Tone

Before Linearization

After Linearization

Measured IM3

Simulated IM3

Figure 4.17: Measured and simulated IIP3 of the mixer. (Dashed curves are simulatedresults)

amplifier consume 4 mA and 4.4 mA under 1.2V voltage, separately, and the auxiliary path

consumes 4.2 mA when it is turned on.

With two RF signals located at 2.025 GHz and 2.035 GHz applied, a conversion gain

of 8.5 dB is obtained and almost unchanged when the linearization part turns on and off.

As can be seen in Fig. 4.17, the IIP3 of the mixer is 2.5 dBm and the proposed linearization

technique can improve it by 12 dB. As the input power is increased beyond -15 dBm, the

IM3 suppression becomes less effective. However, this typically is not a big concern as

-15 dBm input power is sufficiently large for the mixers in most of the wireless receiver

applications. The simulation results are provided in the same plot, indicating a good match

between the simulation and measurement results.

Fig. 4.18 provides the output spectrum of the mixer before and after linearization, which

shows the IM3 suppression evidently. Additionally, the spectrum also shows that the gain


(a)

(b)

Figure 4.18: Output spectrum of the mixer (a) before and (b) after linearization


Figure 4.19: IIP3 improvement versus two-tone spacing for the mixer

is not affected by the linearization technique. With the aforementioned frequency setting,

the IM2 tone of the mixer output lies left to down-converted IF by 5 MHz, as shown at the

leftmost of the spectrum in Fig. 4.18. As can be seen, the proposed method does not affect

the amplitude of IM2 tone. What is more, it does not interfere other linearization technique

to suppress the IM2 tone either.

Fig. 4.19 shows the IIP3 of the linearized mixer as a function of two-tone spacing with

the input power at −25 dBm. The simulation results are also provided as comparison in

the same plot. As can be seen, the optimal point is shifted from 4 MHz in simulation to 7

MHz in measurement. After the optimal point the IIP3 improvement slowly degrades as the

two-tone spacing increases. Nevertheless, over a large two-tone space range from 1 MHz

to 22 MHz, the IIP3 improvement is approximately above 10 dBm.

The linearization technique only introduces small amount of the NF to the system. The

noise figure of the mixer alone is simulated to be 7.9 dB at the IF of 25 MHz, and the mixer


Table 4.3: Performance Summary and Comparison Table

Parameter Unit This Work [42] [78]1 [66]2 [110] [61]

Publication JSSC TCAS JSSC MWCL JSSC

Year 2013 2013 2008 2008 2004

Process µm 0.13 0.16 0.18 0.18 0.18 0.18

Frequency GHz 2.0 0.9 2.1 0.9 2.4 2.4

IIP3/∆IIP3 dBm 14.5/+12.0 11.8/+10.0 15.0/+10.5 0.2/+10.6 15.0/+10.0 9.0/+6.5

Gain/∆Gain dB 8.5/0.0 17.6/+5.0 15.0/0.0 22.0/0.0 11.2/−1.8 16.5/+0.5

NF/∆NF dB 17.9/+0.23 10.1/+0.1 14.0/0.0 5.3/0.0 13.8/+1.3 14.2/+0.9

Voltage V 1.2 1.8 1.8 1.5 2.0 1.8

Current/∆Current mA 12.6/+4.24 10.9/+1.7 4.5/+0.5 13.0/+0.3 7.4/0.0 3.0/+0.1

FOM V−1 3.10 2.88 3.09 1.81 1.61 1.82

1 Simulation results.2 The results are that of the front-end, including an LNA and a mixer.3 The NF of the mixer and the IF amplifier as a whole is measured.4 The mixer, IF amplifier and linearization circuits consume 4 mA, 4.4 mA and 4.2 mA, respectively.

in series to combiner is measured to be 17.7 dB when the linearization circuitry is turned

off. When the auxiliary path is turned on, the noise figure only increases by 0.2 dB.

Table 4.3 summarizes the measured performance of the mixer in both unlinearized and

linearized cases. A performance comparison with other state-of-the-art linearization tech-

niques are also demonstrated in the same table. Considering that both gain and linearity

performances are partially determined by the power supply voltage, a linearity figure of

merit (FOM) is adopted here to provide a fair comparison among works developed under

4.6. SUMMARY 120

different supply voltage, defined as:

FOM[V−1

]=

Gain[1]×IIP3[V]

V2DD[V2]

=OIP3[V]

V2DD[V2]

where Gain [1] is the conversion gain in magnitude, IIP3 [V] is the input third-order in-

tercept point in V, OIP3 [V] is the output third-order intercept point in V, and VDD [V] is

the power supply voltage in V. As can be seen from Table 4.3, the proposed mixer offers

competitive linearity performance under a normalized supply voltage, thus featuring a high

FOM compared to other works.

4.6 Summary

A feedforward linearization scheme to cancel the IM3 terms of the mixer is proposed,

which is indifferent to mixer topology at the cost of small amount of extra DC power

and NF deterioration. Unlike the linearization technique in the former state of art, where

an extra full receiver is used to generate IM3, IM3 for cancellation is generated through

the multiplication of low-frequency IM2 signals generated from a squaring circuit and the

IF fundamental signal of the mixer output. Consequently, the power consumption of the

circuitry in the auxiliary path is low and the cancellation through auxiliary path are immune

to the parasitics of the circuit. A IIP3 improvement of 10 dB over a large two-tone space is

demonstrated with negligible noise and gain degradation and small amount of extra current.

121

Chapter 5

A Wideband Transformer-Coupled Mixer

5.1 Introduction

In this chapter, a low-power, wideband current commutating mixer with on-chip balun is

presented. The mixer adopts a folded structure with its transconductor and the switch-

ing stages coupled by a balun, which is made of an on-chip multifilament transformer.

With this balun integrated, the single-ended-to-differential conversion is realized within

the mixer block. Since the transformer is located at the conjunction of the transconductor

and the switching stages, its bandwidth determines the bandwidth of the mixer. The trans-

former network is designed to work at over-coupling state, so that a wide bandwidth can be

achieved. A tunable resistive feedback is used in the transconductance stage to adjust for

the wideband response as well as the wideband input matching.

A balun is usually needed between the LNA and the mixer in a typical wireless receiver

architecture [111,112]. The differential structure is used for the mixer topology to suppress

the even-order nonlinearities, RF/LO feedthroughs as well as the common-mode noise. On


the other hand, most LNA designs reported are single-ended to accommodate the singled-

ended antennas. Thus, a balun is desired between the two blocks to realize the singled-

ended-to-differential signal conversion, which characterizes the balanced amplitude and

phase.

Realizing the balun with good performance in a wideband manner is particularly chal-

lenging, as the gain and phase balances are hard to be maintained in a wide frequency

range. Among all the reported works, there are two distinct types of baluns, i.e., passive

and active baluns.

The active balun is appealing in the circuit design because of its compact size. There

are several types of active balun topologies: single FET circuits, differential amplifier cir-

cuits and common-gate cascaded with common-source (CG-CS) circuits. As the simplest

configuration, the single-FET types generate the differential output signal at the drain and

the source of the FET when the input signal is applied at the gate. Examples can be found

in [113] and [114] with operation frequency up to 2 GHz. However, the parasitic capaci-

tance of the FET makes this type difficult to achieve the required phase balance for ultra

wideband and high-frequency application.

The second type, the differential amplifier balun circuit, usually has poor amplitude and

phase balance because the current source becomes an imperfect open circuit at the high fre-

quency. The leakage signal to the current source will cause the phase and gain imbalances.

One former work utilized this type to implement a balun with very wide frequency range

from 0.2 to 22 GHz, however it consumes a large power of 166 mW [115]. The third type of

the balun is the CG-CS circuit, which demonstrates relatively low power consumption and

adequate isolation. However, it also suffers from parasitic effects when the operating fre-

quency is high. An active phase splitter made in InGaP HBT process adopts this structure,

5.2. MIXER DESIGN 123

which exhibits a maximum amplitude error and a phase error up to 1.3 dB and 8, respec-

tively, in a band of 1850 to 1910 MHz [116]. To improve the performance at high frequency

and wideband applications, the cascode CG can be used in the CG-CS structure [117].

On the other hand, passive on-chip transformers have also been extensively used as

the balun because of their superior common mode rejection ratio (CMRR) and zero power

consumption [118,119]. In the former uses, the transformer is usually tuned to work in res-

onance [118,120]. Although the high signal-to-noise ratio and current gain can be achieved

in this way, the operation bandwidth is narrow.

In this chapter, a mixer with an in-circuit balun is designed. The balun, which is made

of a passive transformer, is tuned to work as an over-coupled resonator to achieve wide

operating band. In the following, the mixer design details with component selection as well

as implementation of transformer is described first. Then measurement results showing the

wideband operation and the balanced output are demonstrated to prove the concept.

5.2 Mixer Design

As shown in Fig. 5.1, the proposed mixer is a folded current commutating mixer with its

transconductance stage and the switching stage coupled by the balun T1. The transcon-

ductance stage is built with a single-ended cascode combined with a resistive feedback

network. The switching stage is fully differential, so is the IF load, which is made of

self-biased current source.

The balun is implemented fully on chip in a standard CMOS 1P8M process. As shown

in Fig. 5.2, stacked structure is adopted for high coupling factor, i.e. the primary spiral is

built in the top metal layer and secondary spiral in the second from the top layer. Fig. 5.3

demonstrates both the top view and the side view of the balun. As can be observed, the


Figure 5.1: Proposed broadband mixer configuration.

primary and the secondary spirals are both octagonal and center-tapped symmetric, and the

primary and secondary windings are interlacing to decrease the overlapping capacitance

between the spirals. The turns ratio is 4:2:2, and the diameters of the spirals are 170 µm.

The conversion gain of the current commutating mixer can be generalized as

AV,mixer =2

πgmH(jω)ZL (5.1)

H(jω) stands for the portion of the RF current fed into the switching stage, and it deter-

mines the frequency response of the conversion gain. In this work, a wideband response of

H(jω) is obtained through elaborately designing the network around the transformer.


Figure 5.2: Stacked monolithic balun configurations.

Figure 5.3: Top and side views of the balun


Figure 5.4: Simplified balun circuit model of one branch.

Since the balun is fully symmetric, the same equivalent circuit configurations are cho-

sen for the noninverting and inverting branches without losing accuracy. The equivalent

circuit is depicted in Fig. 5.4. In this circuit, Lm represents the mutual inductance between

the spirals while Lp−Lm and Ls−Lm represent the leakage inductance of each side, respec-

tively. Cp and Cs represent the capacitance at primary and secondary terminals. A Norton

equivalent circuit is used to represent the transconductance stage, andRl represent the input

impedance of the switches. Cf models the effect of the parasitic capacitors between the two

spirals. All the component values are identical for the circuits of noninverting and inverting

branches, except that Cf is positive in the non-inverting branch and negative in the inverting

one.

In circuit, H(jω) of (5.1) is the transfer function from current source Gm ∗ Vin to the

current going through Rl. In the following transfer function analysis, the effect of Cf is

ignored and will be discussed later when imbalance of the balun is addressed.

The circuit in Fig. 5.4 are two resonators (Lp, Cp) and (Ls, Cs) coupled by Lm. There


0 5 10 15 20 25 30−10

−5

0

5

10

15

20

LO Frequency (GHz)

Con

vers

ion

Gai

n (d

B)

Rf=200Rf=120Rf=80

Figure 5.5: Simulated frequency response with different Rf .

are two peaks in the response, and it’s the detach of the two peaks that forms the wide

passband. The position of the two peaks are given in (5.2) [121].

ω1,2 =

√(LpCp + LsCs)±

√(LpCp − LsCs)2 + 4CpCsL2

m

2(LpLsCpCs − CpCsL2m)

(5.2)

Through properly choosing Rgm and Rl, the Q of the resonators are small so that a flat

response over the passband can be achieved. In the mixer design, Rl is determined by the

switch transistor size, and Rgm can be tuned by the feedback resistor Rf. In this work,

NMOS of 16µm/0.12µm is used for the switch. With an LO power of -5 dBm and the IF

frequency kept at 110 MHz, the frequency response of the mixer is simulated with different

Rf, as shown in Fig. 5.5. As can be observed, proper switch size is chosen so that the second

peak located around 15 GHz is moderate. With the increase of the feedback resistor, the

first peak is flattened, and up to 12 GHz bandwidth can be achieved. Meanwhile, the peak

gain drops because the effective transconductance decreases with the increase of Rf .

The feedback resistance affects other performances of the mixer, too. The OIP3 and


Table 5.1: Specifications with different feedback resistors

Rf (ohms) 200 120 80

Noise Figure (dB) 9.6 13.3 15.0

OIP3 (dBm) 15.5 18.3 20.5

0 5 10 15 20 25 30−40

−30

−20

−10

0

Frequency (GHz)

Tra

nsm

issi

on C

oeffi

cien

t (dB

)

Cf2Cf3Cfnonivertinginverting

Figure 5.6: Magnitude response of the balun’s circuit model with different Cf .

noise figure at the peak frequency with different feedback resistors are given in Table 5.1.

The variation tendency of OIP3 and the noise figure accords to the prediction, as the feed-

back decreases the effective transconductance while suppresses the distortion of the input

transistor. In this work, Rf of 120 ohms is chosen to trade some bandwidth for lower noise

figure. As shown in Fig. 5.5, although the passband of 4 GHz to 10 GHz is around the first

peak, the existence of the second peak prevents the response from rolling off drastically.

The balance of the balun is another important specification. For a balun made of

multifilament-transformer, imbalances can originate from the parasitic capacitor between


the two overlapping spirals [122], which manifests itself as Cf in the circuit model in

Fig. 5.4. Due to the sign of the transfer ratio, Cf is positive in the noninverting branch

and negative in the inverting one. The positive Cf adds a notch in the frequency response

of noninverting branch, which is absent in its inverting counterpart. In this manner, the

frequency responses for the two branches are different from each other, and imbalance is

generated even though the spirals are symmetric.

To verify this behavior, the transmission coefficient of the equivalent circuit extracted

from the balun are simulated, as shown in Fig. 5.6. In the simulation, extra Cf is added

to the circuit to manifest its influence to the frequency response. As can be observed,

with the increase of Cf, the notch frequency of the noninverting branch decreases while the

response of inverting branch does not change much. Consequently, the balance between the

two branches tend to deteriorate. Thus, in order to improve the balance, the stacked spirals

are designed to interlace with one another for the least overlapping, as can be observed

from both Fig. 5.2 and Fig. 5.3.


The mixer is fabricated in IBM’s CMOS 130µm technology and a photograph of the IC is

shown in Fig. 5.7. It occupies a die area of 800×920 µm2. The circuit consumes only 5.6

mW of dc power from a 1.2 V voltage supply.

The mixer IC is measured directly on-wafer using 40 GHz CPW probes and dc probes.

A 45 GHz Keysight spectrum analyzer (E4446A) with the NF measurement personality

software is used for gain, NF and linearity measurements, and a 50 GHz Keysight network

analyzer (8510C) is used for input reflection coefficient measurement. At the LO input,

an external 180 hybrid is necessary to provide differential signals from the single-ended


Figure 5.7: The microphotograph of the chip.

source. And at the IF output, an off-chip differential-to-single-ended buffer with a high

input impedance and unity voltage-gain is employed, too, for the convenience of measure-

ments.

Fig. 5.8 shows the measured conversion gain, DSB NF and the reflection coefficient

versus RF frequency. In these measurements, the RF frequency is swept in tandem with the

LO frequency, keeping the IF frequency fixed at 110 MHz, and the LO power is fixed at

-5 dBm. As can be observed, the conversion gain reaches its peak of 13.5 dB at 6.5 GHz,

and is 11.1 dB and 10.6 dB at 4 GHz and 10 GHz, respectively, ensuring the gain drop

less than 3 dB across the band. The DSB NF curve has a reciprocal shape compared to the

conversion gain curve, i.e. at the frequency where the peak gain is achieved, the NF reaches

the minimum value, while at two edges of the band where conversion gain is lower, higher

NF is obtained. The minimum NF achieved is 14.06 dB at 6.5 GHz. Due to the resistive


4 5 6 7 8 9 10−25

−20

−15

−10

−5

0

5

10

15

20

25

LO Frequency (GHz)

CG

& R

efle

ctio

n C

oeffi

cien

t (dB

)

4 5 6 7 8 9 10−5

0

5

10

15

20

25

30

35

40

45CG NF S11

4 5 6 7 8 9 10−5

0

5

10

15

20

25

30

35

40

45

NF

(dB

)

Figure 5.8: Conversion gain, reflection coefficient and noise figure.

4 5 6 7 8 9 100.3

0.4

0.5

0.6

0.7

0.8

0.9

RF Frequency (GHz)

Am

plitu

de Im

bala

nce

(dB

)

4 5 6 7 8 9 10−1

−0.5

0

0.5

1

1.5

2

Amplitude ImbalancePhase Imbalance

4 5 6 7 8 9 10−1

−0.5

0

0.5

1

1.5

2

Pha

se Im

bala

nce

(deg

ree)

Figure 5.9: Simulated amplitude and phase imbalance.


Table 5.2: Performance comparison

Reference this work [123] [124] [125]

Process 0.13µmCMOS

0.18µmCMOS

0.18µmCMOS

2µmGaInp/GaAs

Freq. (GHz) 4∼10 0.5∼5.7 2∼11 1.5∼14

CG (dB) 13.5 5.44∼17.05 8.4 20

IIP3 (dBm) 4 -9.95∼5.83 6.5 -3

DSB NF (dB) 14.06 13.4∼21.9 12.5 23

Pdis. (mW) 5.6 6.2 25.7 43.5

Amp. Imbal.∗(dB) 0.9 2 2 -

Phase Imbal.∗() ±2 3 4 -∗ The amplitude and phase imbalances are simulation results.

feedback at the transconductance stage, the mixer also provides a good input matching to

50 ohms. VNA measurement result shows that S11 of the chip is below -13 dB across the

entire frequency range.

Both IIP3 and P1dB are measured to evaluate the linearity performance of the mixer. The

IIP3 is 3.98 dBm and input referred P1dB is -7.96 dBm. The good linearity performance

results from two aspects of the mixer configuration. One is the large voltage headroom

at mixer output due to the folded structure, and the other one is the distortion suppression

of the resistive feedback in the transconductance stage. In addition, simulation results

in Fig. 5.9 show that the amplitude and the phase imbalance is within 0.9 dB and ±2,

respectively, from 4 GHz to 10 GHz. The performance of this work is compared with other

mixers with on-chip balun in Table 5.2.

5.4. SUMMARY 133

5.4 Summary

This chapter presents a low-power, wideband, on-chip balun based current commutating

mixer. A tunable resistive feedback is used at the transconductance stage for wideband

frequency response and input matching. The measurement results show that 13.5 dB con-

version gain is achieved, with a high IIP3 of 4 dBm and noise figure of 14 dB. The amplitude

and phase imbalance is within 0.9 dB and ±2.

134

Chapter 6

Summary and Conclusions

6.1 Thesis Summary and Contributions

A downconversion mixer is an essential element in the wireless receiver ICs. Among all

the options to realize downconversion mixer, active mixer, especially current commutating

mixer, is appealing because of its high gain and low requirements in input LO power. With

the increasing demand in performance of wireless devices, circuit topology innovations are

desired to enhance the performance of the active mixer to meet the ever-stringent require-

ments in bandwidth, block tolerance capability, and noise. The focus of this thesis is to

explore novel techniques to enhance the performance of active mixers.

The investigation of the active mixer starts by proposing a novel switched transcon-

ductor mixer with low power, low noise and ultra-broad band. The circuit analysis on

the traditional switched transconductor mixer is conducted first. The analysis reveals that,

although STM demonstrates superior noise performance, it requires a power-consuming

driver when applying in wideband circumstances. To overcome this drawback, MSTM is

proposed, in which the transconductor stage with fixed DC operating point is switched by

the ac-coupled LO signal to realized mixing. In this way, only a small LO signal is required

6.1. THESIS SUMMARY AND CONTRIBUTIONS 135

to turn the transconductor on and off and thus a low-power LO buffer can be used to achieve

wideband down-conversion. As the noise power from LO stage appears in common mode

at the mixer output, good noise performance is realized, too. Measurement results show

that 15.5 – 17.5 dB gain and 4 – 5.2 dB NF are achieved in 1 – 10 GHz bandwidth, at cost

of a power consumption of only 8.3 mW for the mixer core.

To meet the requirements on block tolerating capability which arises as the bandwidth

expands, a novel feedforward linearization technique to improve IIP3 of the mixer is pro-

posed. In the feedforward signal path, the low-frequency second-order intermodulation

tone (IM2) is created and multiplied by the mixer’s output to directly generate the low-

frequency IM3 for the cancellation. In such a manner, most of the canceling operations

are accomplished in IF band, so that the technique can improves third-order input intercept

point (IIP3) of the mixer regardless of the mixer topology and robust again parasitic param-

eters and process variations. To prove the concept, a 2-GHz Gilbert mixer is designed with

the proposed scheme applied. Measurement results show a 12-dB IIP3 improvement to the

mixer for the input signals as large as -15 dBm with a negligible gain reduction and less

than 0.2 dB of noise penalty. This technique can be also applied on any other active mixers.

Last but not the least, a low-power, wideband current commutating mixer with an on-

chip balun is presented. Inspired by double-tuned amplifier, this work explores for the first

time to design the on-chip transformer work in over-coupling state so that wide bandwidth

can be achieved. Meanwhile, with this balun integrated, the single-ended-to-differential

conversion is realized within the mixer block. A tunable resistive feedback is used in the

transconductance stage to adjust for the wideband response as well as the wideband input

matching. Measurement results show that a conversion gain of 13.5 dB, an IIP3 of 4 dBm

and a noise figure of 14 dB are achieved over 4 – 10 GHz at cost of 5.6 mW. The simulated

6.2. FUTURE WORK 136

amplitude and phase imbalance is within 0.9 dB and ±2 over the band.

6.2 Future Work

There are several potential directions for future work to continue the research of this thesis.

First, the proposed linearization technique can be applied to the more active mixer topolo-

gies to testify its feasibility. As discussed in Chap. 4, the proposed scheme can work on any

active mixers regardless of its circuit topology. For instance, it can be applied on wideband

mixer with low flicker noise. If this design is successfully implemented, an active mixer

suitable for SAWless direct-conversion receiver can be achieved, because low flicker noise

and the tolerance to blockers are realized simultaneously.

What’s more, the feedforward scheme in Chap. 4 can also be used for IIP2 improvement.

In this scheme, the IM2 tone is already generated in the auxiliary path. With an extra

variable gain amplifier (VGA) added to adjust its amplitude, this tone can be readily fed

into the summation circuit to cancel IM2 tone of the mixer itself. Because the IM2 is in

the IF band, the added VGA does need a wide bandwidth. Thus, very little extra power

consumption is needed to achieve it.

In addition, the feedforward scheme can be also applied in the microwave systems.

In the cases where linearity of the mixer needs to be improved to meet the systematic

requirements, instead of replacing the mixer, the proposed feedforward scheme can be

adopted. With only several transistors added to implement the proposed auxiliary path, the

replacing of mixer is avoided and cost of the design can be reduced drastically.

Last, but not the least, a wideband receiver can be designed using the proposed low-

power, low-noise, wideband MSTM. The inductive peaking circuit at the gate of MSTM’s

input transistors should be redesigned so that it can form a wideband network with the load

6.2. FUTURE WORK 137

of its preceding stage. With the VCO and LO buffers designed and optimized, the overall

power consumption of the wideband receiver can be much lower than its counterparts which

adopt other wideband mixer topologies.

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