a four-antenna receiver in 90-nm cmos for beam forming and spatial diversity

8/8/2019 A Four-Antenna Receiver in 90-Nm CMOS for Beam Forming and Spatial Diversity

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005 2515

A Four-Antenna Receiver in 90-nm CMOS forBeamforming and Spatial Diversity

Jeyanandh Paramesh , Member, IEEE, Ralph Bishop, K. Soumyanath , Member, IEEE, andDavid J. Allstot, Fellow, IEEE

AbstractA fully integrated four-channel multi-antenna re-ceiver intended for beamforming and spatial diversity applicationsis presented. It can also be used as a low-power area-efficient rangeextender for spatially multiplexed multi-antenna systems that arepoised to become mainstream in the near future. Implemented in a90-nm CMOS technology, each channel weights its input signal bya complex weight with full 360 phase shift programmability usingvector combinations of variable-gain amplifiers, thus obviatingthe need for expensive phase shifters. The chip consumes 140 mWfrom a single 1.4-V supply and achieves 12 dB of array gain withall four channels activated and 20 dB direction-of-arrival-de-

pendent interference rejection.

Index TermsCMOS integrated circuits, diversity methods,MIMO systems, phased arrays, radio receivers.

I. INTRODUCTION

THE last decade has witnessed the deployment of wireless

local area networks (LANs) such as those governed by

the IEEE 802.11a standard that operates at a peak data rate of

54 Mb/s over 20-MHz channels located in the 5.155.35- and

5.7255.825-GHz bands. A simplistic approach to further en-

hance data rates would be to increase spectral efficiency or band-

width, or both. Paulraj et al. [1] argue that in practical cell reuseschemes, the realizable signal-to-interference-plus-noise ratio

(SINR) is capped at about 20 dB with a peak spectral efficiency

of about 46 b/s/Hz. Furthermore, aggressive increases in band-

width are impractical because of the unavailability of spectrum

below 6 GHz and excessive signal attenuation above 6 GHz.

MIMO systems promise to break this deadlock in the quest for

gigabit wireless through the use of multiple antennas at either

the transmitter or receiver or both. This potential has spurred

the inclusion of MIMO systems into upcoming wireless stan-

dards such as IEEE 802.11n and IEEE 802.16, which envision

replacement of hitherto wireline communication links by wire-

less ones. Excellent overviews of the state-of-the-art in MIMO

systems appear in [1] and [2].

Manuscript received April 26, 2005; revised July 15, 2005. This work wassupported by the National Science Foundation under Contract CCR-0086032and Contract CCR-0120255 and by the Semiconductor Research Corporationunder Contract 2001-HJ-926 and Contract 2003-TJ-1093.

J. Paramesh was with Intel Corporation, Hillsboro, OR 97124 USA. He isnow with the Department of Electrical Engineering, University of Washington,Seattle, WA 98105 USA (e-mail: [email protected]).

R. Bishop and K. Soumyanath are with Intel Corporation, Hillsboro, OR97124 USA (e-mail: [email protected]).

D. J. Allstot is with the Department of Electrical Engineering, University ofWashington, Seattle, WA 98105 USA (e-mail: [email protected]).

Digital Object Identifier 10.1109/JSSC.2005.857416

MIMO systems were originally conceived in the late

1930s and early 1940s with application to radar. Multiple-an-

tenna-based radar systems were proposed to enhance reception

of weak signals, enable direction finding, and increase immu-

nity to jamming. The basis for such an application was the

realization that an array of omnidirectional antenna elements

in conjunction with programmable delay elements or phase

shifters could mimic a directional antenna with a controllable

variable radiation pattern. Such a system, known as a phased

array or beamformer, often requires a priori knowledge of thesignal field. This basic concept was later extended to adaptive

or smart antenna systems wherein some aspect of signal

quality (e.g., SNR or SINR) could be optimized based on

real-time channel estimation. Extensive research has produced

a rich variety of optimization algorithms with different goals

and tradeoffs [3]. These approaches have found widespread

application in the areas of navigational aids, ground mapping,

weather detection, and, most notably, military applications.

The same concepts have also found application in wireless

communication with the goals of increased data rates, network

capacity, and quality of service. Typical wireless channels suffer

from fading, delay spread, and cochannel interference that ulti-

mately limit achievable data rates. Here again, antenna arrays

have played a key role in boosting signal quality through spa-

tial diversity [4], interference mitigation via spatial filtering, and

data rates with spatial multiplexing.

In this paper, a fully integrated four-channel beamforming/

spatial diversity receiver in a 90-nm CMOS technology is

presented. The remainder of this paper is organized as follows:

Section II gives a brief overview of MIMO systems including

their system-level benefits and implications for efficient fully

integrated CMOS implementations. Section III presents the

Cartesian combiner, which is the key circuit block required

for MIMO receivers for beamforming or spatial diversity ap-

plications. Section IV describes the CMOS implementation ofthe four-channel prototype, and Section V provides measure-

ment results that quantify the array gain, SNR enhancement,

and interference mitigation properties of the multiple-antenna

receiver.

II. OVERVIEW OF MIMO SYSTEMS

A. Spatial Multiplexing [5], [6]

The most general MIMO system that uses antennas at

the transmitter and antennas at the receiver can be used to

transmit multiple independent data streams concurrently over

the same physical channel. This is referred to as an

0018-9200/$20.00 2005 IEEE


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2516 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

Fig. 1. Beamformer theory. (a) Simple array. (b) Phased array using beamsteering. Theoretical array patterns with (c) no beam steering and (d) for a 30look-angle.

spatially multiplexed MIMO system. In principle, distinct data

streams are transmitted from each transmit antenna, and conse-

quently, each antenna in the receive array receives signals from

all transmit antennas. When the channel is rich in multipath,

and when the line-of-sight factor between transmit and receive

arrays is small (such as in a typical office or home environment

where there is a large number of clustered scatterers), the data

streams may be separated at the receiver. In theory, then, a 2

2 MIMO system can double the data rate over a single-antenna

system with the same bandwidth. In practice, however, data rates

are lower than this upper bound when robustness issues associ-

ated with a specific implementation are considered [5].

B. Receive Spatial Diversity [4], [7]

Diversity receivers use multiple antennas at the receiver to

enhance signal quality in a multipath fading environment. The

receive antenna array consists of widely spaced elements so that

the fading at each element is uncorrelated to that at the other el-

ements. In a narrowband diversity receiver, complex weighting

circuits are inserted in each antenna path and programmed

via channel estimation hardware to an optimal set of weights

that maximizes SNR. This is called maximal-ratio combining

(MRC) in which the bit error rate (BER) at the receiver im-

proves as BER BER compared to the single-antenna case;

this corresponds to a logarithmic increase in channel capacity.

C. Receive Beamforming [8]

Fig. 1(a) shows an antenna array with isotropic ele-ments separated by a distance from each other. A plane wave

impinges on array element 1

at an angle (the look-angle) relative to the array normal. The

signal at the array element is then given by

, where is the relative time of flight be-

tween two adjacent elements, is the incident angle, and is the

propagation velocity of the wave. In a beamforming application,

the element spacing is often limited to a fraction of the car-rier wavelength, i.e., . For a narrowband signal with

bandwidth , the array output for the system in Fig. 1(a)

can be expressed as

(1)

Finally, using the definition , the complex enve-lope of the array output is derived as

(2)

The variable can be interpreted as equivalent to an elec-

trical envelope phase shift for each antenna input. Clearly, the

lowpass complex envelope of the array output is the product of

the complex envelope of the array input and an equivalent

array gain

(3)

Beam Steering: In the system of Fig. 1(b), programmable

phase shifts have been introduced in each channel such that the

envelope of the signal received by each array element is electri-

cally phase shifted by an angle relative to the previous adja-

cent element. The envelope of the array output can be expressed

as

(4)

i.e., the beam pattern rotates byan angle . This angle is equiv-

alent to a spatial angle . Thus, the

beam pattern now has a peak in the direction of the look-angle

. The relative spacing between the nulls remains the same as

before, but it is offset by an angle . Fig. 1(c) and (d) shows

the simulated array patterns (normalized to unity) for a four-el-

ement beamformer for two different cases. Notice that the array

pattern has a main lobe in the direction of the look-angle corre-

sponding to coherent signal addition and smaller side lobes in

other directions where the signals combine noncoherently. With

receive antennas, perfect cancellation occurs for signals in-cident at specific angles. Thus, we can use this spa-


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PARAMESH et al.: FOUR-ANTENNA RECEIVER IN 90-nm CMOS FOR BEAMFORMING AND SPATIAL DIVERSITY 2517

tial filtering property of antenna arrays to achieve interference

mitigation.

D. System Benefits

1) SNR Enhancement [9]: The elements in the antenna

array for a receive beamforming application are closely spaced

(typically ) so that the received signals are tightlycorrelated in amplitude with well-defined time delays between

adjacent elements. In a beamforming receiver, programmable

delays (or programmable phase shifts for narrowband signals)

are inserted and the resultant coherent signals are summed.

Thus, the signals add in amplitude and any uncorrelated noise

signals from the different channels add in power. Consequently,

for every doubling in the number of antenna elements, up to

3 dB improvement in SNR is achieved when the additive noise

sources are uncorrelated.

2) Interference Cancellation [3]: The second key benefit of

multiple-antenna receivers is their ability to cancel cochannel

interference through the spatial filtering property. The simplestcase is when the signal field consists of a desired signal

and a cochannel interferer incident on the antenna array

at different angles and that are known a priori. The

antenna weights and can then be determined such that

the desired signals combine constructively (in-phase) and the

interferers combine destructively (out-of-phase). This can be

accomplished by solving (please refer to the Appendix for

details)

(5)

where .

It has been shown [3] that interference cancellation can be

achieved when only the direction of arrival (DOA) of the desired

signal is known. In principle, the DOA can be approximated

during channel estimation. Furthermore, with antennas in the

receive array, up to interferers may be cancelled without

having to estimate their DOAs.

E. Power Considerations in CMOS Implementations

The antenna weights for spatial diversity or beamforming ap-

plications are complex-valued scalars for narrowband signals.

Therefore, the signal processing required for each additional

antenna consists of the introduction of a programmable gain

and a programmable phase shift. The relative simplicity of the

required computation motivates the search for power-efficient

techniques that do not require an analog-to-digital converter

(ADC) for each antenna/receiver combination. Clearly, the so-

lution would be to implement the antenna weights as close as

possible to the antenna, i.e., at RF. This is in contrast to spatial

multiplexing systems that require complex digital processing

and, hence, the duplication of the ADC for each data stream.

The proposed RF combining technique can also be used as apower-efficient range extender for spatial multiplexing systems

Fig. 2. (a)Usingvectoradditionto obtain digitally programmable phase shifts.(b) Examples offirstquadrant phase shifts. (c) Examples of third quadrant phaseshifts.

where more diversity antennas are added without requiring ad-

ditional ADCs.

III. CARTESIAN-COMBINING TECHNIQUE

The weighting function in multiple-antenna receivers can be

implemented either through signal shifting or local oscillator

(LO) shifting. Phase shifters that are used in signal-shifting re-

ceivers are expensive to implement in silicon [11] since they

generally occupy a large area, are lossy due to their passive na-

ture, and often do not achieve a full 360 phase-shift range. On

the other hand, LO-shifting architectures can be implemented

either with phase shifters in the LO path [12] or with multi-

phase oscillators in conjunction with phase selectors [9], [10].

The LO-shifting approach is attractive because it does not intro-

duce extra loss in the signal path. However, potential disadvan-

tages include the challenges of building high-performance phaseshifters in silicon and the resolution of the phase selectors.

In this section, the Cartesian combiner [13] that introduces

the antenna weight in the signal path by means of vector combi-

nations of variable-gain amplifier (VGA) outputs is described.

The development of the Cartesian combiner is depicted in Fig. 2

The complex weight in the channel could be

realized in its Cartesian form by means of VGAs

and a 90 phase-shift block. For example, to add a phase shift

corresponding to the first quadrant, the normalized gain of the

real amplifier is set to 1 with that of the imaginary amplifier

set to 1/2. When the outputs of these two amplifiers are added

in a vector fashion using a 90 phase shift, a phase-shift angle

of 26.5 is obtained. Similarly, to realize a phase shift in thethird quadrant, the gain of the real amplifier is programmed


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Fig. 3. Implementation of a phase-shifting downconverter.

Fig. 4. Architectural modification using signal-path linearity enablescombining the signals from two channels.

at 1/2and thatof the imaginary amplifier at 1;uponvector

addition through a 90 phase shift, a phase-shift angle of 243

is realized. Thus, we can synthesize arbitrary phase shifts in all

quadrants using VGAs whose gains can be sign inverted. How-

ever, 90 phase shifters that are realized using polyphase fil-

ters or lumped-element microwave couplers pose disadvantages

similar to those of conventional variable phase shifters. To over-

come these problems, we realize the 90 phase shift function in

the form of a complex downconversion. The signal processing

functions depicted in Fig. 2 are expressed as

(6)

which indicates that the each complex weight can be realized

using two VGAs followed by a quadrature downconversion.

The resultant architecture for this phase-shifting downconverter

is shown in Fig. 3. The magnitude and phase of the weight

are given by and ,

respectively.The weighted signals from two antenna elements may be

combined as shown in Fig. 4. A major simplification is obtained

by observing that the complex downconversion is linear in the

signal path. Hence, signal combining may be implemented by

appropriately summing the VGA outputs prior to mixing. Since

there are now only four mixers overall (as opposed to four

mixers per channel if combining is performed after the mixing),

the routing and buffering of the LO signals to the mixers is

vastly simplified.

The overall Cartesian combiner for two antennas is shown in

Fig. 5. Note that the core of the combiner in each channel is

preceded with a variable-gain low-noise amplifier (VG-LNA).

Each VG-LNA performs two functions. 1) It decouples the pro-grammability of the magnitude of each complex weight from

Fig. 5. Cartesian combiner illustrated for a two-channel receiver.

Fig. 6. (a) Simplified schematic of the VG-LNA. (b) Measured S-parameters.

the programmability of its phase shift. 2) Note that for some

values of phase shift, the gain of one of the two VGAs can be

zero. However, the noise contribution of that VGA is nonzero.

The VG-LNA serves to absorb the variation in noise figure (NF)

with programmability in phase shifts. From a systems perspec-

tive, the VG-LNA has additional functions. For example, in a

beamformer application, the array pattern may be tailored by ap-plying weights of different magnitudes to each antenna element.


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Fig. 7. (a) Simplified schematic of the weight amplifiers. (b) Gain-controlDAC-associated bias circuits.

Fig. 8. Simplified schematic of the Cartesian combiner on the real path. Asimilar structure is used on the imaginary path.

In a diversity application using MRC, the optimum weight for anarrowband signal requires programmable magnitudes.

There are several advantages to the Cartesian-combining ap-

proach. First, it is a simple method of extending single-antenna

receivers to diversity or beamforming receivers. The overhead

with respect to a single-antenna receiver is one VG-LNA and

two weight amplifiers (VGAs) per additional channel and two

extra mixers overall. This translates to an incremental increase

in die area and power consumption. Second, because the VGAs

are inherently broadband circuits, a full 360 phase shift can, in

principle, be achieved at any frequency [14]. Furthermore, the

accuracy of the phase shift is limited only by the accuracy of the

variable gains. Finally, as mentioned earlier, the routing of LO

signals remains simple because the combining occurs before themixers.

Fig. 9. 211 transformer.

Fig. 10. Die microphotograph in a 90-nm CMOS technology.

Fig. 11. Array pattern measurement setup.

IV. PROTOTYPE DESIGN

A. Variable-Gain Low-Noise Amplifier

The VG-LNA (Fig. 6) is implemented using a differential in-

ductively source-degenerated structure. The variable gain func-

tionality is realized using differential pairs instead of a cascode

device. The gain can be controlled by applying a differentialvoltage across these differential pairs to divert some of the signal


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Fig. 12. Measured array patterns for (a) broadside (0 ), (b) 30 , and (c) 90 incidence angles.

current to the power supply. The gain control is achieved using

a 6-bit digital-to-analog converter (DAC) and can be varied lin-

early over a 40-dB range with respect to the control code. An

unbuffered standalone VG-LNA without gate tuning was mea-

sured on a probe station with the addition of a simulated gate-

tuning inductor in the vector network analyzer. The gain of theVG-LNA was 12.2 dB at 4.93 GHz [Fig. 6(b)] and NF was

estimated to be about 2 dB; the equivalent gain of a buffered

VG-LNA is 23 dB.

B. Weight Amplifiers and Gain Control

The weight amplifiers are also implemented using differen-

tial pairs as shown in Fig. 7(a). Because the gain of each am-

plifier must be invertible in sign, the variable gain feature is im-

plemented using a cross-coupled quad. The differential control

voltage is also generated through 6-bit DACs. Each DAC is a

segmented current-steering type with four thermometer-coded

most significant bits (MSBs) and two binary-coded least signif-icant bits (LSBs). The reference current for each DAC is gen-

TABLE IPERFORMANCE SUMMARY

erated by means of an op-amp-based current source that uses aresistor identical to the load resistor in the DAC [Fig. 7(b)].


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Fig. 13. Measured SNR improvement when a second channel is enabled.

C. Cartesian Combiner Core

Fig. 8 shows the implementation of one half of the Cartesian

combiner. The weighted currents from the real amplifiers are

summed in the current domain and fed into the primary winding

of a three-winding transformer. The secondary windings of the

transformer are fed to two Gilbert cells that are controlled by

quadrature phases of the local oscillator. An identical structure

is used to combine the imaginary path signals, and the outputs

of the Gilbert cells are summed in the current domain. This cur-

rent is then converted into a differential voltage by PMOS loads

whose common-mode voltage is controlled by a Miller-com-

pensated feedback loop. The 211 transformer shown in Fig. 9

consists of a four-turn primary and two symmetrical two-turn

secondary windings. The primary winding uses four turns of the

top metal layer M7 and each secondary winding consists of twoturns of M5 strapped with M4.

A four-channel prototype of the chip (Fig. 10) was fabricated

in a 90-nm CMOS process [15]. Each channel consisting of a

VG-LNA and a pair of weighting amplifiers is oriented symmet-

rically around the summing inputs to the core of the combiner

that is located at the center of the die. The entire receiver draws

140 mW from a single 1.4-V power supply.

V. MEASUREMENTS

The prototype was wafer-probed using a Cascade Microtech

membrane with 88 pads. The measurements focus on two areasthat demonstrate the major motivations for using beamforming

or diversity multi-antenna receivers; namely, array gain and in-

terference cancellation. To demonstrate array gain and the as-

sociated benefits of SNR enhancement, off-chip variable phaseshifters were used at the input of each channel (Fig. 11) to

mimic a plane wave impinging on an antenna array with a pro-

grammable DOA. In all measurements, we imitate a linear array

with omnidirectional elements and spacing . The

weight controls on the receiver are then swept to measure the

array gain, which shows the measured array patterns for 0 ,

30 , and 90 angles of incidence with all four channels enabled

(Fig. 12). It is observed that the main lobe has a peak in the

look direction and the nulls appear in the locations predicted

by simple theory in accordance with (2). For example, at 30

incidence, two nulls appear at 0 and 90 ; the first null is due to

signal cancellation between antenna pairs (1, 3) and (2, 4) andthe other null is due to cancellation between antenna pairs (1, 2)

and (3, 4). The total array gain due to all four channels is mea-

sured at 12 dB as expected from theory (Table I).

To demonstrate the SNR enhancement property, modulated

signals were input to the receiver using a vector signal gener-

ator. A vector signal analyzer (VSA) is used to demodulate the

downconverted signals from the output of the receiver. Because

the VSA has a priori knowledge of the input bit-stream, it is

able to calculate the output SNR based on an internal BER cal-

culation. Fig. 13 shows the results of this measurement for a

64-quadrature amplitude modulation modulated signal incident

at 30 ; the SNR improves from 24.1 dB to about 30 dB whenall four channels are enabled.


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Fig. 14. Measured interference cancellation when a second channel is enabled.

To demonstrate interference cancellation, a desired

64-QAM modulated signal, along with a multitone interfererseparated by 5 MHz at 30 incidence relative to the desired

signal, is inputted to the receiver. The in-phase and quadrature

( ) output from the receiver is measured using a VSA

whose measurement bandwidth is set equal to the span; that is,

filtering is not performed to further attenuate the interferer prior

to demodulation. The weights on the receiver are adjusted so as

to cause signal addition for the desired signal and cancellation

of the interferer. This has the effect of attenuating the interferer

by more than 20 dB (Fig. 14) and boosting the desired signal by

6 dB. This interference cancellation property may be extended

to include cancellation of three interferers concurrently with

four-way in-phase signal addition by using all four channels.In principle, any interferer that remains static during a given

packet interval may be attenuated as long as its angle of arrival

is different from that of the desired signal; this can include

cochannel interference or an image signal. Computation of the

required gain settings ( , ) is typically performed during

the preamble of most wireless LAN (WLAN) standards.

VI. CONCLUSION

The feasibility of fully integrated multi-antenna receivers in

a deep-submicron CMOS technology has been demonstrated.

Primarily intended for beamforming or spatial diversity appli-cations, this receiver can potentially be used as a low-power

range extender to spatial-multiplexing MIMO systems. The

Cartesian-combining technique that utilizes vector combina-tions of variable-gain elements realizes the antenna weights in

a compact power-efficient manner. Experimental results from

a four-channel prototype show an array gain of 12 dB with

a peak-to-null ratio of 20 dB and an SNR improvement of

6 dB over a single-antenna receiver. This receiver also achieves

a full 360 look-angle coverage. The ability of multi-antenna

receivers to achieve interference cancellation is a key advantage

over their single-antenna counterparts. It is also demonstrated

that an interferer may be attenuated by more than 20 dB with

two operational antennas. While this is strictly true only for

cochannel interferers, the multi-antenna receiver is also able

to reject signals over a small fractional bandwidth around the

desired channel.

APPENDIX

WEIGHT CALCULATIONS FOR INTERFERENCE CANCELLATION

This appendix describes the method used to calculate the an-

tenna weights for cancellation of an interferer incident at

a different angle from a desired signal . While this anal-

ysis is strictly valid only for cochannel interference (

below), it can be extended for an interferer at a small offset fre-

quency with respect to the desired signal. Let and denotethe angle of incidence of the desired signal and the interferer,


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respectively. We consider the case when only two channels are

operational. The total input signal at the two antennas is

(A1)

and

(A2)

where . Let and denote the com-

plex weights in the two antenna paths. The complex interme-

diate frequency (IF) signal may then be written as

(A3)

The goal is to determine the antenna weights such that the

desired signal combines constructively without distortion and

the interferer combines destructively; this is accomplished by

solving

(A4)

This cancellation assumes that the desired signal and the in-

terferer are incident at different angles.

ACKNOWLEDGMENT

The authors would like to thank C. Le, D. Martin, D. Trammo,

P. Hack, R. Hoelle, D. Ackelson, and M. Dibbattista of Intel

Corporation for their contributions. They would also like to

thank the staffs at the System-on-Chip Laboratory at UW and

the Communication Circuits Laboratory at Intel. J. Paramesh

is grateful to D. Somasekhar of Intel Corporation for helpful

technical discussions throughout this project.

REFERENCES

[1] A. J.Paulraj, D. A.Gore, R. U. Nabar, and H.Bolcskei, An overview ofMIMO communicationsA key to gigabit wireless, Proc. IEEE, vol.92, no. 2, pp. 198218, Feb. 2004.

[2] D. Gesbert, M. Shafi, D.-S. Shiu, P. J. Smith, and A. Naguib, Fromtheory to practice: An overview of MIMO space-time coded wirelesssystems, IEEE J. Sel. Areas Commun., vol. 21, no. 3, pp. 281302, Apr.2003.

[3] B. Widrow, P. E. Mantey, L. J. Griffiths, and B. B. Goode, Adaptive an-tenna systems, Proc. IEEE, vol. 55, no. 12, pp. 21432159, Dec. 1967.

[4] D. G. Brennan, Linear diversity combining techniques, Proc. IEEE,vol. 91, no. 2, pp. 331356, Feb. 2003.

[5] G. J. Foschini, Layered spacetime architecture for wireless communi-cation in a fading environment when using multiple antennas,Bell LabsTech. J., vol. 1, no. 2, pp. 4159, Autumn 1996.

[6] E. Telatar, Capacity of multi-antenna Gaussian channels, in Bell LabsTechnical Memorandum, Jun. 1995.

[7] S. Sandhu and M. Ho, Analog combining of multiple receive antennaswith OFDM, in Proc. IEEE Int. Conf. Communications, Anchorage,AK, 2003, pp. 34283432.

[8] D. Parker and D. C. Zimmermann, Phased arraysPart I: Theory andarchitectures, IEEE Trans. Microw. Theory Tech., vol. 50, no. 3, pp.678687, Mar. 2002.

[9] X. Guan, H. Hashemi, and A. Hajimiri, A fully integrated 24-GHzeight-element phased-array receiver in silicon, IEEE J. Solid-State Cir-cuits, vol. 39, no. 12, pp. 23112320, Dec. 2004.

[10] A. Natarajan, A. Komijani, and A. Hajimiri, A 24 GHz phased-arraytransmitter in 0.18

m CMOS, in Proc. IEEE Int. Solid-State CircuitsConf., San Francisco, CA, 2005, pp. 212213.

[11] H. Zarei and D. J. Allstot, A low-loss phase-shifter in 180 nm CMOSfor multiple-antenna receivers, in Proc. IEEE Int. Solid-State CircuitsConf., San Francisco, CA, 2004, pp. 392534.

[12] T. Yamaji, D. Kurose, O. Watanabe, S. Obayashi, and T. Itakura, Afour-input beam-forming downconverter for adaptive antennas, IEEE

J. Solid-State Circuits, vol. 38, no. 10, pp. 16191625, Oct. 2003.[13] J. Paramesh, R. Bishop, K. Soumyanath, and D. J. Allstot, A 1.4 V

5 GHz four-antenna Cartesian-combining receiver in 90 nm CMOSfor beamforming and spatial diversity applications, in Proc. IEEE Int.Solid-State Circuits Conf., San Francisco, CA, 2005, pp. 210211.

[14] L. Griffiths, A comparison of quadrature and single-channel receiverprocessing in adaptive beamforming, IEEE Trans. Antennas Propag.,vol. 25, no. 2, pp. 209218, Mar. 1977.

[15] K. Kuhn et al., A 90 nm communication technology featuring SiGeHBT transistors, RF CMOS, precision R-L-C RF elements and 1 m6-T SRAM cell, in Proc. IEEE Int. Electron Devices Meeting, San Fran-cisco, CA, 2002, pp. 7376.

Jeyanandh Paramesh (M98) received the B.Tech.degree from the Indian Institute of Technology,Madras, India, in 1996, and the M.S. degree fromOregon State University, Corvallis, in 1998, bothin electrical engineering. He is currently workingtoward the Ph.D. degree at the University of Wash-ington, Seattle.

He was employed at AKM Semiconductor(Analog Devices), San Diego, CA, and Motorola,Austin, TX. He is currently with the University ofWashington. His research interests include MIMO

transceivers and sigmadelta data converters in addition to circuit design ofother kinds. He has also been employed as a Graduate Student Researcher withthe Communication Technology Laboratories, Intel Corporation, Hillsboro,

OR.Mr. Parameshwas a recipientof theChevron Engineering Scholarship (1997),

the Intel Foundation Doctoral Fellowship (20032004), and the Analog DevicesOutstanding Student Designer Award (2005).

Ralph Bishop received the associate degree from the

Oregon Institute of Technology and has also attendedOregon State University, Corvallis.

He is the Lead Technician in the CommunicationCircuits Laboratory, Intel Corporation, Hillsboro,OR.


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K. Soumyanath (M93) received the B.E. degreein electronics and communication engineering fromthe Regional Engineering College, Tiruchirappalli,India, in 1979, the M.S. degree in electronics fromthe Indian Institute of Science, Bangalore, India,in 1985, and the Ph.D. degree in computer sciencefrom the University of Nebraska at Lincoln in 1993.

Since 1996, he has been with Intel Corporation,

Hillsboro, OR, where he is a Senior Principal Engi-neer and is the Director of the Communications Cir-cuits Laboratory. He has published over 40 papers in

VLSI circuits and related areas and has 30 patents issued with several pending.

David J. Allstot (S72M72SM83F92) re-ceived the B.S. degree from the University ofPortland, Portland, OR, the M.S. degree fromOregon State University, Corvallis, and the Ph.D.degree from the University of California, Berkeley.

He has held several industrial and academicpositions and has been the BoeingEgtvedt ChairProfessor of Engineering at the University of Wash-

ington, Seattle, since 1999; he is currently Chair ofthe Department of Electrical Engineering. He hasadvised approximately 80 M.S. and Ph.D. graduates

and published more than 225 papers.Dr. Allstot was the recipient of several outstanding teaching and advising

awards. His awards include the IEEE W. R. G. Baker Prize Paper Award in1978, the IEEE Circuits and Systems Society Darlington Best Paper Award in1995, the IEEE International Solid-State Circuits Conference Beatrice WinnerAward in 1998, the IEEE Circuits and Systems Society Golden Jubilee Medalin 1999, the Technical Achievement Award of the IEEE Circuits and SystemsSociety in 2004, and the Aristotle Award of the Semiconductor Research Cor-poration in 2005. His professional service includes Associate Editor for theIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITALSIGNAL PROCESSING from 1990 to 1993, Editor of the IEEE TRANSACTIONS ONCIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING from1993 to 1995, a member of the Technical Program Committee of the IEEECustom IC Conference from 1990 to 1993, a member of the Board of Gov-

ernors of the IEEE Circuits and Systems Society from 1992 to 1995, a memberof the Technical Program Committee of the IEEE International Solid-State Cir-cuits Conference from 1994 to 2004, Executive Committee Member and ShortCourse Chair of the IEEE International Solid-State Circuits Conference from1996 to 2000, Distinguished Lecturer of the IEEE Circuits and Systems Societyfrom 2000 to 2001, and Co-General Chair of the IEEE International Sympo-sium on Circuits and Systems in 2002. He is a member of Eta Kappa Nu andSigma Xi.

a four-antenna receiver in 90-nm cmos for beam forming and spatial diversity

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