a new architecture of test response analyzer based on the berlekamp–massey algorithm for bist

3168 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 12, DECEMBER 2010

A New Architecture of Test Response AnalyzerBased on the Berlekamp–Massey

Algorithm for BISTCleonilson Protásio de Souza, Member, IEEE, Francisco Marcos de Assis, and

Raimundo Carlos Silvério Freire, Member, IEEE

Abstract—Lately, built-in self-test (BIST) has been of greatimportance in the manufacture of very large scale integration(VLSI) circuits. Most BIST schemes compress the test responseinto a compact signature using space and/or time compaction. Afundamental problem associated with response compaction is er-ror masking or aliasing. In this paper, an alternative zero-aliasingtest response evaluation scheme for BIST is presented. The mainconceptual ingredient utilized to build the proposed scheme isthe application of the Berlekamp–Massey algorithm (BMA). TheBMA provides a general solution for synthesizing the shortestlinear feedback shift register (LFSR) capable of generating agiven finite sequence. Basically, on the BIST design stage andconsidering the fault-free test response sequence, the BMA is usedto synthesize an LFSR capable of generating this sequence in aneconomical way. The BIST testing stage consists in comparing theobtained test response sequence of the circuit under test (CUT)with the fault-free test response sequence generated by the LFSRpreviously designed. This way, a testing of the CUT can be made.It is observed that there is no aliasing using the proposed scheme.The key to make this scheme attractive is to keep the LFSRlength as small as possible. Based on it, two derived schemes,called Simple-LFSR and Multi-LFSR, are shown to try to solvethis problem. Experimental results are shown for some ISCAS85benchmarks.

Index Terms—Berlekamp–Massey algorithm (BMA), built-inself-test (BIST), linear feedback shift register (LFSR), outputresponse analyzer, zero aliasing.

I. INTRODUCTION

BUILT-IN self-test (BIST) is rapidly becoming an industry-wide standard test technique [1]. In the BIST setup,

both test pattern generation and output data evaluation areperformed with on-chip hardware [2]. A test pattern generator(TPG) is used to apply a test sequence �T = (T1, T2, . . . , Tn),represented by the polynomial T (x), into the circuit undertest (CUT), as shown in Fig. 1, where n is the test length.The test response sequence �R = (R1, R2, . . . , Rn), represented

Manuscript received January 28, 2009; revised March 13, 2009; acceptedMarch 15, 2009. Date of publication June 28, 2010; date of current versionNovember 10, 2010. The Associate Editor coordinating the review process forthis paper was Dr. Reza Zoughi.

C. P. de Souza is with the Department of Electrical Engineering, FederalUniversity of Paraíba, 58051-900 João Pessoa-PB, Brazil (e-mail: [email protected]).

F. M. de Assis and R. C. S. Freire are with the Department of ElectricalEngineering, Federal University of Campina Grande, 58109-970 CampinaGrande-PB, Brazil (e-mail: [email protected]; [email protected]).

Digital Object Identifier 10.1109/TIM.2010.2047171

Fig. 1. BIST setup.

by the polynomial R(x), is applied into the compressor thatcompresses R(x) into a compact signature, i.e., a few bit word.Signature analysis is a method based on polynomial-division-based linear compression [3]. The circuit evaluation consists incomparing the obtained CUT signature �s with the precomputedfault-free circuit signature �s∗ at the end of testing [2]. If �s �= �s∗,then the CUT is consider faulty. Due to the information loss thatcan be caused by the compression, the CUT might be declaredfault free, i.e., �s = �s∗, although the CUT is actually faulty, i.e.,�R �= �R∗, where �R∗ is the fault-free circuit response sequence.Such error masking is called aliasing [3]. Clearly, if the CUTevaluation consists of element-by-element comparison withoutany compression, then zero aliasing is achieved. Unfortunately,in general, this approach requires a large hardware overhead;thus, any approach that conciliates light enough hardware over-head along no compression requirements is worthwhile.

In this paper, an alternative zero-aliasing test response ana-lyzer scheme for BIST is proposed. This new scheme provides“graceful” adjusting during the BIST design stage of maximumcoverage aside an admissible hardware overhead. The mainconceptual ingredient used to build this scheme is the appli-cation of the Berlekamp–Massey algorithm (BMA).

Although the BMA was initially proposed to find error loca-tions in a context-based communication system [4], it actuallyprovides a general solution on synthesizing the shortest linearfeedback shift register (LFSR), designed over GF(2q), capableof generating a given finite sequence R∗(x) =

∑ni=1 R∗

ixi,

where R∗i ∈ GF(2q) [5]. In addition, given a sequence, the

LFSR length1 synthesized by the BMA is defined as the linearcomplexity of the sequence [6, pp. 108].

In a general way, the proposed test response analyzer basedon the BMA is described as follows: Consider that the fault-free circuit responses are given by the sequence R∗(x) =∑n

i=1 R∗ix

i, where R∗i = [r1, . . . , rq]′, q is the number of cir-

cuit outputs, and n is the number of test patterns applied. Apply-ing R∗(x) into the BMA, it is applied to synthesize the shortestLFSR capable of generating it. As a result, this LFSR is capable

1The LFSR length is equal to the number of memory stages of the LFSR.

0018-9456/$26.00 © 2010 IEEE

DE SOUZA et al.: NEW ARCHITECTURE OF A TEST RESPONSE ANALYZER BASED ON THE BMA FOR A BIST 3169

Fig. 2. Proposed basic test response analyzer. © is a comparator.

Fig. 3. LFSR.

of generating the legitimate fault-free circuit response sequenceR∗(x). Based on this, the proposed test response analyzerscheme is shown in Fig. 2, where, while each element Ri ofthe CUT test response sequence is output to the comparator, theBMA-based LSFR generates each correspondent element R∗

i ofthe fault-free response sequence. Then, in the first discrepancy,i.e., Ri �= R∗

i , the CUT is declared faulty. On the contrary, atthe end of the test, the CUT is declared fault free. The key tomake this scheme attractive is to keep the LFSR length as smallas possible.

It is important to notice that the BMA-synthesized LFSRlength depends on the linear complexity of the applied se-quence, i.e., the smaller the linear complexity of the sequence,the shorter the LFSR length. This way, direct control of theLFSR is not always possible. In consequence, two alterna-tive configurations are proposed to try to solve this problem.The first configuration is called the Single-LFSR scheme [7],whereas the second configuration is called the Multi-LFSRscheme. In addition, a space compaction (SC) method used toincrease the performance of these schemes is proposed.

This paper is organized as follows: Section II summarizesthe relevant background and definitions used in this paper.Section III describes the details of the proposed basic testingscheme. Sections IV and V describe the alternative configu-rations, namely, the Single- and Multi-LFSR schemes, respec-tively. The SC method is shown in Section VI. Experimentalresults are given in Section VII for some ISCAS85 benchmarks.Conclusions are given in Section VIII.

II. BACKGROUND AND DEFINITIONS

A. Signature Analysis

Let GF(2q)[x] be a ring of polynomials with coefficients inGalois field GF(2q). In [1], the LFSR is defined by a feedbackpolynomial, and it is used as a compressor for signature gener-ation. The LFSR feedback polynomial is given by

Φ(x) = Φmxm + Φm−1xm−1 + · · · + Φ2x

2 + Φ1x + Φ0

(1)

where all its coefficients Φi are over GF(2q) and represent thefeedback connections, i.e., the ith coefficient Φi defines themultiplier for the ith feedback connection, as shown in Fig. 3.

Fig. 4. LFSR-based sequence generator.

Let �R = (R0, R1, . . . , Rn) be a vector with Ri ∈ GF(2q),where Ri is the q-bit test response of the CUT (interpretedas an element of GF(2q)). Define the polynomial R(x) =∑n

i=0 Rixi. The signature is calculated as the unique remainder

S(x) according to the long-division algorithm, given as

R(x) = Q(x)Φ(x) + S(x). (2)

The signature S(x) obtained in (2) is compared with thepredetermined fault-free circuit signature S∗(x) given by

R∗(x) = Q∗(x)Φ(x) + S∗(x) (3)

where R∗(x) represents the fault-free circuit response.The main problem with the signature analysis is that one can

have S(x) = S∗(x), although R(x) �= R∗(x). This results in afaulty CUT being accepted as a fault-free circuit and aliasingoccurs. Some techniques for reducing the aliasing probability ofsignature analyzers have been studied, but none can reduce thealiasing to zero, except for an element-by-element comparisonof R(x) with R∗(x) [1].

B. Sequence Generator Based on the LFSR

It is well known that an LFSR of length L can be used togenerate a finite sequence over GF(2q), as shown in Fig. 4,where a cascade of L stages is organized to form a linearcombination of the stage contents, which serves as the inputto the first stage. The output of this LFSR is assumed to betaken from the last stage. The initial contents R0, R1, . . . , RL−1

of the L stages coincide with the first L output elements, andthe remaining output elements are uniquely determined by therecursion

Rj =L∑

i=1

ΦiRj−i, j = L,L + 1, L + 2, . . . . (4)

Therefore, this LFSR generates the sequence

R0, R1, . . . , RL−1, RL, RL+1, . . . .

C. BMA

The BMA provides a general solution for synthesizing theshortest LFSR capable of generating a given finite sequence�R = (Ri), Ri ∈ GF(2q) [4], [5]. The BMA is reproducedin Table I. The input of the BMA is the sequence �R∗ =R∗

0, R∗1, . . . , R

∗n−1 of elements from GF(2q). The output is the

set of coefficients of the connection polynomial Φ(x) of theshortest LFSR capable of generating �R∗.


TABLE IBMA (LFSR SYNTHESIS ALGORITHM)

Example 1: Consider a single-output circuit with a fault-freeresponse sequence given by

R∗13, R

∗12, . . . , R

∗1, R

∗0 = 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0

corresponding to a given test pattern sequence. ApplyingR∗

13, . . . , R∗0 to the BMA, we obtain the connection polynomial

Φ(x) = x4 + x3 + x2 + 1 that specifies the minimal LFSRcapable of generating the fault-free circuit output responsesequence.

Example 2: Consider a four-binary output circuit with afault-free response sequence in GF(24) given by

R∗14, R

∗13, . . . , R

∗1, R

∗0 = (0100, 0010, 0001, 1100, 0110, 0011,

1101, 1010, 0101, 1110, 0111, 1111, 1011, 1001, 1000)

corresponding to a given test pattern sequence. ApplyingR∗

14, . . . , R∗0 to the BMA, the connection polynomial Φ(x) =

x + α ∈ GF(24)[x] is obtained. Here, α is the root of theprimitive polynomial p(x) = x4 + x + 1. As before, the Φ(x)-based LFSR is capable of generating the entire fault-free circuitoutput response sequence.

III. PROPOSED BASIC TESTING SCHEME

If a test pattern sequence T (x) is applied to the inputs ofa fault-free circuit, then a fault-free test response sequenceR∗(x) over GF(2q) (where q is the output number of thecircuit) is obtained. In the design stage, the basic testing schemeconsists of applying R(x)∗ to the BMA and, after processing,obtaining the synthesis of the shortest LFSR represented by theconnection polynomial Φ(x), which is capable of generatingR(x)∗.

Using the testing setup shown in Fig. 5, applying T (x) intothe CUT, a test response sequence R(x) is obtained and is

Fig. 5. BMA-based testing scheme.

Fig. 6. Modified testing scheme.

concomitantly compared with R∗(x) generated by the BMA-synthesized LFSR. It is noticed that an element-by-elementcomparison occurs and that zero aliasing is achieved.

As the length of the BMA-synthesized LFSR depends on thelinear complexity of the input sequence applied to the BMA,in the following, a modified version of the BMA is shownthat allows the designer to choose a desired LFSR length. Thislength parameter is clearly related to the hardware overhead thatthe designer is able to pay for. With this choice, it is possiblethat the final fault coverage will be reduced to a fraction of thetotal fault coverage.

IV. SINGLE-LFSR SCHEME

Consider that, to obtain an appropriate hardware overhead fora given design, we define a length Ld of the maximum LSFRsize.

Suppose that a test pattern sequence �T = (T0, T1, . . . , Tn−1)achieves a fault coverage FC. Let FC0 be the fault cover-age of the test pattern T0, FC1 be the fault coverage ofthe subsequence (T0, T1), FC2 be the fault coverage of thesubsequence (T0, T1, T2), . . ., and FCn−1 be the fault cover-age of (T0, T1, . . . , Tn−1). Then, FCi ≤ FCj for i < j andFCn−1 = FC.

A slight modification in the BMA, called modBMA, is neces-sary to find an LFSR (denoted by LFSR(Ld)) of length Ld that

generates the subsequence �R∗m = (R∗

0, R∗1, . . . , R

∗m−1), repre-

sented by the polynomial R∗m(x), where m ≤ n. Since �R∗

m

corresponds to �Tm = (T0, T1, . . . , Tm−1), the fault coverageof the testing procedure, as shown in Fig. 6, is FCm, whereFCm ≤ FC.

The proposed modified BMA (see the modification inStep 5) is shown in Table II. Running the modified BMA, ifm �= 0, then Φd(x) contains the connection polynomial of theLFSR(Ld) that generates �R∗

m, as shown in Fig. 7.Example 3: Consider the c17 ISCAS85 circuit [8], which

has five inputs, two outputs, and 22 faults, and an LFSR-basedTPG with feedback polynomial p(x) = x5 + x3 + 1 that gener-ates T (x), as shown in the column labeled Ti in Table III. Usinga fault simulation program, named FSCAN and developed inthis research, and simulating the fault-free c17 circuit, weobtain the following: the corresponding fault-free test response


TABLE IIMODIFIED BMA (modBMA)

Fig. 7. Ld-length BMA-synthesized LFSR.

TABLE IIIDATA OF EXAMPLE 3

R∗i , the fault coverage FCi achieved by T (x), and the LFSR of

length L during the execution of the modified BMA, as shownin Table III.

Using the basic testing scheme, a BMA-synthesizedLFSR with connection polynomial Φ(x) = 1 + x + x2 +αx6 ∈ GF(2)[x] and length 6 has been obtained, and it providesa fault coverage of 100%.

In the previous case, supposing that the hardware overheadis not appropriate and that the appropriate LFSR length isLd = 1, then applying R∗(x) in the modBMA, an LFSR with

Fig. 8. Multi-LFSR scheme.

connection polynomial Φ(x) = 1 + βx is obtained, where β ∈GF(2), with length = 1. It generates the first six elements ofR∗(x). Thus, using this LFSR(Ld=1) in the testing procedure, afault coverage of 86.363% is achieved.

V. MULTI-LFSR SCHEME

It is noticed that, in the Single-LFSR scheme, the hardwareoverhead is decreased, but the achieved fault coverage may bereduced. If this is not suitable for the design, a scheme namedMulti-LFSR is presented in this section to solve such a problem.

The general idea is as follows: Given a fault-free responsesequence R∗(x), which is split in n subsequences, synthesizen LFSRs to generate each of these subsequences. To savehardware overhead, the summation of lengths of these LFSRshas to be smaller than the length of the only synthesized LFSRable to generate R∗(x). This can be performed consideringsubsequences with low linear complexity, if possible.

Considering Example 3 in the previous section, the LFSRable to generate all elements of R∗(x) has length equal to 6.Partitioning R∗(x) into two subsequences, i.e., (R∗

0, . . . , R∗5)

and (R∗6, . . . , R

∗8), then two LFSRs are necessary. This way,

as it was previously shown, the first LFSR with connectionpolynomial Φ(x) = 1 + βx is capable of generating the firstsix elements of R∗(x), i.e., (R∗

0, . . . , R∗5). Next, applying in the

BMA the last three elements of R∗(x), i.e., (R∗6, . . . , R

∗8), then

an LFSR with connection polynomial Φ(x) = 1 and length 1is obtained. This way, these two length-1 LFSRs are used togenerate R∗(x), and consequently, the fault coverage achieves100%. It is noticed that the sum of lengths of these twoLFSRs is smaller than the length of the synthesized LFSR thatgenerates R∗(x), i.e., 6.

In general, given a desired Ld, the modified BMA synthe-sizes an Ld-length LFSR (called LFSR1) that generates thelongest possible subsequence of R∗(x). The remaining subse-quence may pass through the same process, and the modifiedBMA is used to synthesize another LFSR (LFSR2), and so on,as shown in Fig. 8. As a result, each LFSRi is associated with acorrespondent fault coverage FCi. The association of these FCi

results in the fault coverage FC of the proposed Multi-LFSRscheme.

VI. PROPOSED SCHEMES USING SC

To save hardware overhead, we propose the use of a well-known response compaction technique, called parity bit check-ing [9], which is based on generating a 1-bit fault-free outputsequence by XORing the q-bit fault-free circuit output sequence,


Fig. 9. Proposed schemes using parity bit checking. (a) Applied to the basicscheme. (b) Applied to the Single-LFSR scheme. (c) Applied to the Multi-LFSRscheme.

TABLE IVUTILIZED ISCAS85 BENCHMARK CIRCUITS

as shown in Fig. 9(a). Applying this 1-bit sequence into theBMA, we obtain the shortest LFSR, which is characterizedby Φ(x), that generates it. This way, as Φ(x) is defined overGF(2)[x], then each storage and connection element of theLFSR is over GF(2), and thus, this approach considerably saveshardware overhead. A drawback using this SC scheme is that aloss of fault coverage can occur. Fig. 9(b) and (c) shows theSingle- and Multi-LFSR schemes when SC is used.

VII. EXPERIMENTAL RESULTS

The experimental simulations have been implemented in afault simulation program, named FSCAN, which was devel-oped in this research. An LFSR was used as the TPG, andthe experimental simulation results were obtained on someISCAS85 benchmarks [8], as shown in Table IV.

Table V shows the number of test patterns (Column 2),the length L of the BMA-synthesized LFSR (Column 3) thatgenerates the entire fault-free response sequence, and the fault

TABLE VEXPERIMENTAL SIMULATION RESULTS OF THE BASIC SCHEME

TABLE VIFAULT COVERAGE USING THE Single-LFSR SCHEME

coverage (Column 4) achieved when the basic scheme withoutSC is used.

Using the basic scheme with SC, Column 5 shows the lengthL of the BMA-synthesized LFSR that generates the entire fault-free response parity sequence, and Column 6 shows the faultcoverage considering the loss due to SC. It is important to noticethat, for instance, for the c432 circuit, both schemes (withand without SC) get 68-length LFSRs, but for each instanceof the corresponding LFSR, the SC-based scheme has only1 memory element, whereas the non-SC-based scheme has136 memory element (the primary output number of the cir-cuit). Thus, clearly, the proposed SC-based scheme is moreattractive in terms of hardware overhead.

It is also important to notice that no technique to increase thefault coverage of the TPG was used in the experiments. Thisway, the fault coverage values shown in the results are not due tothe proposed schemes but due to the used pseudorandom TPG.

Using the same previous configuration for each circuit,Table VI shows the results when the Single-LFSR schemeis used. Columns labeled Non-SC show the fault coverageFCLd

when the length Ld is fixed to 32, 16, and 8, respec-tively. Using the Single-LFSR scheme with SC, the results areshown in Columns labeled SC for each corresponding length,respectively.

Table VII shows the results when the Multi-LFSR schemewithout SC is used. Columns labeled FCN show the faultcoverage when the possible maximum number (the columnlabeled N ) of LFSRs is used and the length Ld is fixed to32, 16, and 8, respectively. For each corresponding setup as inTable VII, Table VIII shows the results when the Multi-LFSRscheme with SC is used.


TABLE VIIEXPERIMENTAL RESULTS OF THE Multi-LFSR SCHEME WITHOUT SC.

N IS THE POSSIBLE MAXIMUM NUMBER OF LFSRs, AND

FCN IS THE FAULT COVERAGE ACHIEVED

TABLE VIIIEXPERIMENTAL RESULTS OF THE Multi-LFSR SCHEME WITH SC.

N IS THE POSSIBLE MAXIMUM NUMBER OF LFSRs, AND

FCN IS THE FAULT COVERAGE ACHIEVED

VIII. CONCLUSION

In this paper, a BIST scheme based on the BMA has beenintroduced. It was shown that the proposed scheme achieveszero aliasing. According to the linear complexity of the fault-free response sequence, the basic testing scheme may increasethe hardware overhead. Thus, two alternative configurationsand an SC scheme were proposed to try to solve this problem.The first configuration was called the Single-LFSR scheme, andthe second configuration was called the Multi-LFSR scheme,which limit the BMA-based LFSR length. The SC scheme isbased on the fault-free response parity sequence. Using theSingle-LFSR scheme, the LFSR length parameter is clearlyrelated with the hardware overhead the designer is able to payfor. With this choice, the final fault coverage will be reducedto a fraction of the total fault coverage related most of thetime, as shown in the experimental results. However, the faultcoverage may considerably be increased by using the Multi-LFSR scheme, and the hardware overhead may considerablybe reduced by using schemes with SC. Related to the proposedSC method, it was shown that it obtains low hardware overheadwith little loss of fault coverage.

REFERENCES

[1] D. K. Pradhan and S. K. Gupta, “A new framework for designing andanalyzing BIST techniques and zero aliasing compression,” IEEE Trans.Comput., vol. 40, no. 6, pp. 743–763, Jun. 1991.

[2] Y. Wu and A. Ivanov, “Reducing hardware with fuzzy multiple signatureanalysis,” IEEE Des. Test Comput., vol. 12, no. 1, pp. 68–74, Spring 1995.

[3] S. K. Gupta, D. K. Pradhan, and S. M. Reddy, “Zero aliasing compression,”in Proc. Fault Tolerant Comput. Symp., 1990, pp. 254–263.

[4] S. B. Wicker, Error Control Systems for Digital Communication andStorage. Englewood Cliffs, NJ: Prentice-Hall, 1995.

[5] R. E. Blahut, Theory and Practice of Error Control Codes. Owego, NY:Addison-Wesley, 1983.

[6] A. Vardy, Ed., Codes, Curves, and Signals, Common Threads in Communi-cations. Erewhon, NC: Kluwer, 1998.

[7] C. P. Souza, R. C. S. Freire, and F. M. Assis, “Test response analyzer basedon Berlekamp–Massey algorithm for BIST,” in Proc. 5th IEEE LATW,Mar. 8–10, 2004, pp. 88–93.

[8] F. Brglez and H. Fujiwara, “A neutral list of 10 combinational benchmarkcircuits and a target translator in FORTRAN,” in Proc. Int. Symp. CircuitsSyst., Jun. 1985, pp. 663–698.

[9] S. R. Das, M. Sudarma, M. H. Assaf, E. M. Petriu, W. Jone, K. Chakrabarty,and M. Sahinoglu, “Parity bit signature in response data compaction andbuilt-in self-testing of VLSI circuits with nonexhaustive test sets,” IEEETrans. Instrum. Meas., vol. 32, no. 3, pp. 1363–1380, Oct. 2003.

Cleonilson Protásio de Souza (M’09) receivedthe B.Sc. and M.Sc. degrees in electrical engi-neering from the Federal University of Maranhão,Maranhão, Brazil, in 1989 and 2001, respectively,and the Ph.D. degree from the Federal University ofCampina Grande, Campina Grande, Brazil, in 2005.

He is currently a Professor with the FederalUniversity of Paraíba, João Pessoa, Brazil. His re-search interests include VLSI testing and intelligentsystems.

Francisco Marcos de Assis received the B.Sc. andM.Sc. degrees in electrical engineering from theMilitary Institute of Engineering, Rio de Janeiro,Brazil, in 1984 and 1992, respectively, and the Ph.D.degree from Pontifical Catholic University of Rio deJaneiro, Rio de Janeiro, in 1994.

He is currently a Professor with the Federal Uni-versity of Campina Grande, Campina Grande, Brazil.His research interests include coding and informa-tion theory.

Raimundo Carlos Silvério Freire (M’07) receivedthe B.Sc. degree in electrical engineering from theFederal University of Maranhão, Maranhão, Brazil,in 1979, the M.Sc. degree from the Federal Uni-versity of Paraíba, Paraíba, Brazil, in 1982, and thePh.D. degree from the Institute Nationale Polytech-nique de Loraine, Nancy, France, in 1988.

He is currently a Professor with the Federal Uni-versity of Campina Grande, Campina Grande, Brazil.His research interests include VLSI, and analogand digital circuit design for use in biomedical and

communications.

a new architecture of test response analyzer based on the berlekamp–massey algorithm for bist

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