Jan 6-10th, 2007 VLSI Design 2007 1

A Reduced Complexity Algorithm for A Reduced Complexity Algorithm for Minimizing Minimizing NN-Detect Tests-Detect Tests

Kalyana R. KantipudiVishwani D. Agrawal

Department of Electrical and Computer EngineeringAuburn University, AL 36849 USA

20th Intl Conf. on VLSI Design, Bangalore, Jan 6-10th, 2006

Jan 6-10th, 2007 VLSI Design 2007 2

Motivation for This Work

• Ability of N-detect tests to improve the defect coverage.

• Easy assimilation of N-detect tests into the normal test generation strategy.

• Main limitation of N-detect tests is their size.

• Inability of ILP based method to produce a time-bound optimal solution.

• Inability of previous test minimization strategies in finding minimal tests for c6288 benchmark.

Jan 6-10th, 2007 VLSI Design 2007 3

Outline

• ILP based N-detect test minimization

• Previous LP based methods

• Recursive rounding based approach

• The 3V3F example

• Minimal tests for c6288

• Results

• Conclusions

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ILP-Based N-Detect Test Minimization [1]

• Use any N-detect test generation approach to obtain a set of k vectors which detect every fault at least N times.

• Use diagnostic fault simulation to get the vector subset Tj for each fault j.

• Assign integer variable ti to ith vector such that,

• ti = 1 if ith vector is included in the minimal set.

• ti = 0 if ith vector is not included.

[1] K. R. Kantipudi and V. D. Agrawal, “On the Size and Generation of Minimal N-Detection Tests,” Proc. VLSI Design’06.

Jan 6-10th, 2007 VLSI Design 2007 5

Objective and Constraints of ILP

jfaultsNt

t minimize

jTvectori

k

1ii

ji

,:sConstraint

:Objective

Where, Nj is the multiplicity of detection for the jth fault.

Nj can be selected for each individual fault based on some criticality criteria or on the capability of the initial vector set.

ILP always generates an optimal solution for the given set of test vectors.

Jan 6-10th, 2007 VLSI Design 2007 6

A Linear Programming Approach

• Though ILP guarantees an optimal solution, it takes exponential time to generate the solution.

• Time bounded ILP solutions deviate from optimality.

• LP takes polynomial time (sometimes in linear time) to generate a solution.

• Redefining the variables tis as real variables in the range [0.0,1.0] converts the ILP problem into a linear one.

• The problem now remains to convert it into an ILP solution.

The optimal value of the relaxed-LP of the ILP minimization The optimal value of the relaxed-LP of the ILP minimization problem is a lower bound on the value of the optimal integer problem is a lower bound on the value of the optimal integer solution to the problem.solution to the problem.

Jan 6-10th, 2007 VLSI Design 2007 7

Previous Solutions (Randomized rounding)

• The real variables are treated as probabilities.

• A random number xi uniformly distributed over the range [0.0,1.0] is generated for each variable ti.

• If ti ≥ xi then ti is rounded to 1, otherwise rounded to 0.

• If the rounded variables satisfy the constraints, then the rounded solution is accepted.

• Otherwise, rounding is again performed starting from the original LP solution.

Jan 6-10th, 2007 VLSI Design 2007 8

Limitations of Randomized Rounding• Consider three faults f1,f2 and f3, and three vectors.

• We assign a real variable ti to vector i.

• Now the single detection problem is specified as:Minimize t1 + t2 + t3

Subject to constraints,f1 : t1 + t2 ≥ 1

f2 : t2 + t3 ≥ 1

f3 : t3 + t1 ≥ 1

• The number of tests is much larger

than the size of the minimal test set.

• The randomized rounding becomes a random search.

t3

LP Solution (0.5,0.5,0.5)

t1

t20

1

1

1

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Recursive Rounding (New Method)

• Step 1: Obtain an LP solution.

Stop if each ti is either 0.0 or 1.0• Step 2: Round the largest ti and fix its value to 1.0

If several ti’s have the largest value, arbitrarily set only one to 1.0. Go to Step 1.

Maximum number of LP runs is bounded by the final Maximum number of LP runs is bounded by the final minimized test set size.minimized test set size.

Final set is guaranteed to cover all faults. This method takes polynomial time even in the worst case.This method takes polynomial time even in the worst case. LP provides a lower bound on solution.

Lower Bound ≤ exact ILP solution ≤ recursive LP solution

Absolute optimality is not guaranteed.

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The 3V3F Example• Step 1:

LP gives t1 = t2 = t3 = 0.5

• Step 2:

We arbitrarily set t1 = 1.0

• Step 1:

Gives t2 = 1, t3 = 0 ■

or t2 = 0, t3 = 1 ■

or t2 = t3 = 0.5

• Step 2: (last case)

We arbitrarily set t2 = 1.0

• Step 1: Gives t3 = 0

t3

t2

t1

LP Solution (0.5,0.5,0.5)

0

1

1

1

Non-optimum solution

ILP solutions (optimum)

Step 1

Step 2

Jan 6-10th, 2007 VLSI Design 2007 11

Minimal Tests for Array Multipliers

• There exists a huge difference between its theoretical lower bound of six and its practically achieved test set of size 12.

• A 15 x 16 matrix of full-adders (FA) and half-adders (HA).

• To make use of its recursive

structure and apply

linear programming

techniques.

HA

HA

HA

FA

FA

FA

FA

FA

FA

FA

HA

FA

A0B0A1B0A2B0B0An-1

An-1B1

B2An-1

Bn-1An-1

P2n-1P2n-2 Pn

P0

P1

P2

P3

Pn+1

A0B1

B2

A0

A0B3

11

n-21

21n-2

2

n-2 133

Jan 6-10th, 2007 VLSI Design 2007 12

Tests for c6288: 16-Bit Multiplier

• Known results (Hamzaoglu and Patel, IEEE-TCAD, 2000):

• Theoretical lower bound = 6 vectors

• Smallest known set = 12 vectors, 306 CPU s

• Our results:• Up to four-bit multipliers need six vectors

• Five-bit multiplier requires seven vectors

• c6288– 900 vectors constructed from optimized vector sets of smaller

multipliers– ILP, 10 vectors in two days of CPU time– Recursive LP, lower bound = 7, optimized set = 12, in 301 CPU

s

Jan 6-10th, 2007 VLSI Design 2007 13

Comparison of ILP and Recursive LP

0

20

40

60

80

100

120

140

160

180

3 4 5 6 7 8 9 10 11 12

Bit Multiplier (Bits)

CP

U S

econ

ds

3

6

9

12

15

18

21

24

Test Set S

ize (Vectors)

LP CPUSecs

ILP CPUSecs

LP Set size

ILP Setsize

Timebound ILPSet size1000 sec

Jan 6-10th, 2007 VLSI Design 2007 14

Sizes of 5-Detect Tests for ISCAS85 Circuits

Jan 6-10th, 2007 VLSI Design 2007 15

CPU Time to Minimize 5-Detect Tests

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Optimized 15-detect Tests

Circuit Name

Unopti.Vecs

LP/recursive Rounding

ILP [1] Heuristic[2]

L.B.

Vect. CPU s Vect. CPU s Vect. CPU s

c432 14882 430 83.5 430 444.8 505 292.1 405

c499 1850 780 17.8 780 24.9 793 153.2 780

c880 4976 322 94.5 321 521.4 338 229.6 195

c1355 2341 1260 41.2 1260 52.1 1274 5674.6 1260

c1908 6609 1590 150.4 1590 191 1648 1563.9 1590

c2670 8767 1248 380.6 1248 607.8* 962 9357.6 660

c3540 4782 1407 239.6 1411 1223.7 - - 1200

c5315 4318 924 494.3 924 1368.4* - - 555

c6288 731 134 250.5 134 1206.3 144 1813.8 90

c7552 6995 2371 359.1 2370 346.1** - - 975[1] K R Kantipudi and V D Agrawal, Proc. VLSI Design, 2006

[2] Lee, Cobb, Dworak, Grimaila and Mercer, Proc. DATE, 2002

Jan 6-10th, 2007 VLSI Design 2007 17

Conclusion

• Single and N-detection tests can be efficiently minimized by the new procedure.

• The quality of the result from recursive rounding LP is close to that of ILP.

• The 10 vector test set for c6288 signifies the shortcomings of present test set minimization techniques.

• The recursive rounding LP method has numerous other applications where ILP is traditionally used and is found to be expensive.

Jan 6-10th, 2007 VLSI Design 2007 18

Thank You . . .