a semantic model for vhdl-ams (charme '97)

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A semantic model for VHDL-AMS

Natividad Martınez Madrid, Peter T. Breuer, Carlos Delgado Kloos

Universidad Carlos III de Madrid

<nmadrid,ptb,cdk>@it.uc3m.es

CHARME ’97, Montreal, Canada - October 1997 1

Objectives ?

• explain behaviour of VHDL-AMS processes

– not a detailed syntactic mapping

– provide sufficient primitives

• present an underlying model that . . .

– extends existing model for VHDL


Content of the talk ?

• Introduction

• A process algebraic analysis

• Semantics

• The analog solver with example


Main idea ?

VHDL semantics analog extension

imperative

discrete-event

diff. equations

real time domain

declarative

continuous-time

ց ւ

INTEGRATION


Name space division & Properties ?

VARIABLES assigned

instantaneously

not scheduled

SIGNALS at least δ-delayed preemptively

scheduled

QUANTITIES assigned

instantaneously

governed by diff. eqns.

PROCESSES invariant invariant


Semantics of assignment ?

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Semantic Domains ?

WorldLine = T ime → State

State = Id → V alue

VHDL Statements

Semantics = (WorldLine, T ime) ↔ (WorldLine, T ime)T ime = Int

VHDL-AMS Statements

Semantics = (EqnSet,WorldLine, T ime) ↔ (EqnSet,WorldLine, T ime)T ime = Real


Parallel decomposition ?

LRM view of basic VHDL compositionality:

• processes in parallel (+ kernel)

• process body loops continuously

• imperative commands in process body run sequentially

Our view:

• no kernel


VHDL-AMS: integer time → real time

Analog Solver

Process algebraic analysis ?

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Process algebraic analysis (II) ?

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Denotational semantics ?

S[a; b] = S[a];S[b]

P[a; b] = P[a] ∪ S[a];P[b]

S[while(true)do a end] = { }

P[while(true)do a end] = P[a] ∪ S[a];P[while(true)do a end]

= µR : Semantics .R = P[a] ∪ S[a];R

S[a||b] = S[a] ∩ S[b]

P[a||b] = P[a] ∩ P[b]


Wait & Assignment semantics ?

Wait Semantics

(e, w0, t0)S[wait until p](e, w1, t1) = w0 = w1

∧ wt1 |= p ∧ ∀t ∈ [t0, t1) . wt 6|= p

(e, w0, t0)P[wait until p](e, w1, t1) = w0 = w1

∧ ∀t ∈ [t0, t1] . wt 6|= p

Assignment Semantics

(e, w0, t0)S[x⇐ y after τ ](e, w1, t1) = t0 = t1

∧ w1 = relax(e, t0)(force assign(w0))

P[x⇐ y after τ ] = { }


Wait semantics ?

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Generalized Wait

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wait until a = 1

on signals -> discrete time

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wait until x >= 2/3

on quantities -> continuous time


Sequential composition ?

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. v =x. a

= v wait until x >= 2/3wait until x >= 2/3wait until x >= 2/3a <= 1 after 4


Analog solution ?

Bouncing ball example

dsdt

= v

dvdt

= −g ± av2

Local approximations(t) = 1v(t) = −gt

origin ats = 1v = 0t = 0

Linear approximation (s, v) = (s0, v0) + (t− t0)(v0,−g ± av20)

Recursion

(s, v)(t0,s0,v0)(t) ∼

(s0, v0) + (t− t0)(v0,−g ± av20) t ∈ [t0, t1)

(s, v)(t1,s1,v1)(t)

s1 = s0 + v0∆t

v1 = v0 + (−g ± av20)∆tt1 = t0 +∆t


Example ?proc [qty s := 1.0, v := 0.0, g := 9.8, a := 0.1 ]

ds/dt == v;

dv/dt == -g + if v<0 then a else -a end * v * v;

begin

wait until s < 0;

v := -v;

s := 0 ;

end

∆t = 0.02


Example Cont. ?proc [qty s := 1.0, v := 0.0, g := 9.8, a := 0.1 ]

ds/dt == v;

dv/dt == -g + if v<0 then a else -a end * v * v;

begin

wait until s < 0;

v := 1.4142 * (g * s + 0.5 * v * v)**0.5 ;

s := 0 ;

end

g ∗ 0+ v′2

2 =

g ∗ s+ v2

2

∆t = 0.06CHARME ’97, Montreal, Canada - October 1997 17

Example Cont. (II) ?

Height

Speed

∆t = 0.06


Unresolved areas ?

• Implementation of the parallel composition of pro-

cesses if quantities are shared between processes

• Errors in the analog solver may require us to rewrite

our program

• The proper execution of the analog solver in δ time

when the processes are in parallel


Conclusion ?

• What? Extension of our VHDL semantics to cover

VHDL-AMS

• How? Embedding of the VHDL semantics in a bigger,

continuous time domain, which contains an oracular

analog solver

• Why? Clarify the draft standard document


a semantic model for vhdl-ams (charme '97)

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