a study of design tool - xilinx - vidyarthiplus
TRANSCRIPT
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A STUDY OF DESIGN TOOL - XILINX
1. Open Xilinx Project Navigator from Start Menu Xilinx ISE Opens-up
2. Opening a New ProjectSelect New Project from File Menu—The below window opens-
up—Enter the Project Name -> Click Next
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3. Enter the device details as follows - > Click Next
4. Click on New Source Tab
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5. Select Verilog Module and Enter a name for the module Click Next
6. Define the Input and Output Port for the module being designed
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7. Finish the Yes
8. Click Next Next Finish. The new Project opens-up in the ISE - IDE
9. Enter the program Code Save the file Select Check Syntax by collapsing
Synthesize XST
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10. Once Check Syntax is Successful Simulate the design using ModelSim
Change the source for dropdown to Behavioral Simulation
To Create TestBench
Select the project from Sources window Right Click Select New Source
11. Select Test Bench Waveform and give a file name for the testbench being created
Click Next Verify the Association Next Finish
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12. Select Combinational or Sequential as per the simulation and enter the clock details
13. Assigning Values to input and output
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14. Entering Values
15. Save the test bench & Select Simulate Behavioral model from processes window by
collapsing ModelSim Simulator. The Simulated output for the testbench being created
appears in ModelSim
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Check Syntax & Synthesis
User Constraint ->Floorplan I/O -> Click YES
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Enter PIN Details-> SAVE Click OK
RUN IMPLEMENT DesignRUN Generate Program file
RUN Configure Target device Manage configuration project IMPACT Window opens
up
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After Clicking Finish ->Assign New Configuration File Dialog Opens up Click Bypass
After Clicking Bypass ->Assign New Configuration File Dialog Opens up Select bit file
Click open
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In below dialog - > Select Apply Click OK
Right Click the second IC and select Program
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Click on Apply OK
Check the output in KIT
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SUMMARY
Check Syntax &Behavioral Simulation
Synthesis
User Constraint ->Floorplan I/O -> Click YES
Enter PIN Details-> SAVE Click OK
RUN IMPLEMENT Design
RUN Generate Program file
Configure Target device Manage configuration project
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CIRCUIT DIAGRAM
LOGIC GATES AND ITS TRUTH TABLES
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Ex.No: 1 LOGIC GATES
AIM:
To design Logic gates using Verilog HDL, verify its function by simulating in Xilinx
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. Verify the output waveform as obtained.
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SIMULATION OUTPUT:
ANDGATE
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VERILOG CODE:
STRUCTURAL MODELLING
moduleAndgate (i1, i2,out);
input i1, i2;
output out;
and (out,i1,i2);
endmodule
TESTBENCH
moduletestAndgate;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Andgateuut (
.i1(i1),
.i2(i2),
.out(out)
);
initial begin
// Initialize Inputs
i1 = 0;
i2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100 i1=1'b1; i2=1'b0;
#100 i1=1'b0; i2=1'b1;
#100 i1=1'b1; i2=1'b1;
end
endmodule
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OR- GATE
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VERILOG CODE
STRUCTURAL MODELLING
moduleOrgate (i1, i2,out);
input i1, i2;
output out;
or (out,i1,i2);
endmodule
TESTBENCH
module testOr;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Orgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial begin
// Initialize Inputs
i1 = 0;
i2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100 i1=1'b1; i2=1'b0;
#100 i1=1'b0; i2=1'b1;
#100 i1=1'b1; i2=1'b1;
end
endmodule
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NAND GATE
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VERILOG CODE
DATAFLOW MODELLING
moduleNandgate (i1, i2,out);
input i1, i2;
output out;
assign out = ~ ( i1 & i2);
endmodule
TESTBENCH
moduletestNand;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Nandgateuut (
.i1(i1),
.i2(i2),
.out(out)
);
initial begin
// Initialize Inputs
i1 = 0;
i2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100 i1=1'b1; i2=1'b0;
#100 i1=1'b0; i2=1'b1;
#100 i1=1'b1; i2=1'b1;
end
endmodule
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XOR GATE
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VERILOG CODE
DATAFLOW MODELLING
moduleXorgate ( i1,out);
input i1;
output out;
assign out = ( i1 ^ i2);
endmodule
TESTBENCH
moduletestxor;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Xorgateuut (
.i1(i1),
.i2(i2),
.out(out)
);
initial begin
// Initialize Inputs
i1 = 0;
i2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100 i1=1'b1; i2=1'b0;
#100 i1=1'b0; i2=1'b1;
#100 i1=1'b1; i2=1'b1;
end
endmodule
RESULT:
Thus the various logic gates were designed and corresponding outputs verified.
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CIRCUIT DIAGRAM
HALF ADDER:
FULL ADDER
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Ex.No:2 ADDERS
AIM:
To design half adder and full adder using Verilog HDL, verify its function by simulating
in Xilinx
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. Verify the output waveform as obtained.
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SIMULATION OUTPUT:
HALFADDER
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VERILOG CODE:
HALF ADDER
Structural:
module ha(sum,c_out,i1,i2);
input i1,i2;
outputsum,c_out;
xor (sum,i1,i2);
and (c_out,i1,i2);
endmodule
Dataflow:
module ha(s,c,a,b);
inputa,b;
outputs,c;
assign s = a ^ b;
assign c = a & b;
endmodule
TESTBENCH
moduletestHA;
// Inputs
reg a;
reg b;
// Outputs
wire s;
wire c;
// Instantiate the Unit Under Test (UUT)
hauut (.s(s), .c(c), .a(a), .b(b) );
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100 a=1'b1; b=1'b0;
#100 a=1'b0; b=1'b1;
#100 a=1'b1; b=1'b1;
end
endmodule
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SIMULATION OUTPUT:
FULL ADDER
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FULL ADDER
Structural :
modulefull_adder_structural(i1,i2, c_in, sum, c_out);
input i1,i2c_in;
output sum, c_out;
wire s1, c1, c2, c3;
xor xor_s1(s1, i1, i2); // compute sum.
xor xor_s2(sum, s1, c_in);
and and_c1(c1, i1,i2); // compute carry out.
and and_c2(c2, i1, c_in);
and and_c3(c3, i2, c_in);
oror_cout(c_out, c1, c2, c3);
endmodule
Dataflow
modulefull_adder_structural(x, y, c_in, s, c_out);
input x, y, c_in;
output s, c_out;
assign s = x ^ y ^ z; // compute sum.
assignc_out = (a&b) | (b&c) | (c&a); // compute carry out.
endmodule
TESTBENCH
moduletestFA;
// Inputs
reg i1; reg i2; regc_in;
// Outputs
wiresum;wirec_out;
// Instantiate the Unit Under Test (UUT)
full_adder_structuraluut (.i1(i1), .i2(i2), .c_in(c_in), .sum(sum), .c_out(c_out));
initial begin
// Initialize Inputs
i1 = 0; i2 = 0; c_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100i1 = 0;i2 = 0;c_in = 0;
#100 i1 = 0;i2 = 0;c_in = 0;
#100 i1 = 0;i2 = 0;c_in = 1;
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#100 i1 = 0;i2 = 1;c_in = 0;
#100 i1 = 0;i2 = 1;c_in = 1;
#100 i1 = 1;i2 = 0;c_in = 0;
#100 i1 = 1;i2 = 0;c_in = 1;
#100 i1 = 1;i2 = 1;c_in = 0;
#100 i1 = 1;i2 = 1;c_in = 1;
#200 $stop;
end
endmodule
RESULT:
Thus the design and implementation of adders is performed using Verilog HDL and
Xilinx tool
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CIRCUIT DIAGRAM
HALF SUBTRACTORTRUTH TABLE
FULL SUBTRACTORTRUTH TABLE
I1 I2 BR DIFF
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 1
I1 I2 CIN BR DIFF
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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Ex.No:3 SUBTRACTORS
AIM:
To design a half subtractor and full subtractor using Verilog HDL, verify its function, by
simulating in Xilinx
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. Verify the output waveform as obtained.
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SIMULATION OUTPUT:
HALF SUBTRACTOR
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VERILOG CODE - HALF SUBTRACTOR
STRUCTURAL
modulehalf_Sub(i1,i2,dif,bor);
outputdif,bor;
input i1,i2;
wire w;
xor (dif,i1,i2);
not(w,i1);
and(bor,w,i2);
endmodule
DATAFLOW
module half_subtractor (i1,i2 ,dif ,bor );
output dif ;
output bor ;
input i1,i2 ;
assign dif = i1 ^ i2;
assign bor = (~i1) &i2;
endmodule
TESTBENCH
moduletestHS;
// Inputs
reg i1;
reg i2;
// Outputs
wiredif;
wirebor;
// Instantiate the Unit Under Test (UUT)
half_subtractoruut (.i1(i1), .i2(i2), .dif(dif), .bor(bor));
initial begin
// Initialize Inputs
i1 = 0;
i2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
i1=1'b0; i2=1'b0;
#100 i2=1'b1;
#100 i1=1'b1; i2=1'b0;
#100 i1=1'b1; i2=1'b1;
#100
$stop;
end
endmodule
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SIMULATION OUTPUT:
FULL SUBTRACTOR
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VERILOG CODE - FULL SUBTRACTOR
STRUCTURAL
modulefull_sub(i1,i2,b_in,dif,b_out);
outputdif,b_out;
input i1,i2,b_in;
wire w,w1,w2,w3;
xor(dif,i1,i2,b_in);
not(w,i1);
and(w1,i2,b_in);
and(w2,i2,w);
and(w3,b_in,w);
or(b_out,w1,w2,w3);
endmodule
DATAFLOW
module full_subtractor ( i1,i2,b_in ,dif ,b_out );
output dif;
output b_out ;
input i1,i2,b_in;
assign diff = i1 ^ i2 ^ b_in;
assign borrow = ((~i1) &i2) | (i2&b_in) | (b_in& (~i1));
endmodule
TEST BENCH
moduletestFS;
// Inputs
reg i1; reg i2; regb_in;
// Outputs
wiredif;wireb_out;
// Instantiate the Unit Under Test (UUT)
full_subtractoruut (.i1(i1), .i2(i2), .b_in(b_in), .dif(dif), .b_out(b_out));
initial begin
// Initialize Inputs
i1 = 0; i2 = 0; b_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100 b_in = 0;i1 = 0;i2 = 0;
#100 b_in = 0;i1 = 0;i2 = 0;
#100 b_in = 0;i1 = 0;i2 = 1;
#100 b_in = 0;i1 = 1;i2 = 0;
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#100 b_in = 0;i1 = 1;i2 = 1;
#100 b_in = 1;i1 = 0;i2 = 0;
#100 b_in = 1;i1 = 0;i2 = 1;
#100 b_in = 1;i1 = 1;i2 = 0;
#100 b_in = 1;i1 = 1;i2 = 1;
end
endmodule
RESULT
Thus the design and implementation of subtractors is performed and results verified using
Verilog HDL.
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CIRCUIT DIAGRAM
MULTIPLEXER (4X1)TRUTH TABLE
DEMULTIPLEXER (1X4) TRUTH TABLE
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Ex.No:4 MULTIPLEXER AND DEMULTIPLEXER
AIM:
To design a 4X1 multiplexer and Demultiplexer using Verilog HDL, verify its function,
by simulating in Xilinx
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. Verify the output waveform as obtained.
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SIMULATION OUTPUT:
MULTIPLEXER
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VERILOG CODE: - MULTIPLEXER
STRUCTURAL
module Mux4to1(i0, i1, i2, i3, s0, s1, out);
input i0, i1, i2, i3, s0, s1;
output out;
wire s1n,s0n;
wire y0,y1,y2,y3;
not (s1n,s1);
not (s0n,s0);
and (y0,i0,s1n,s0n);
and (y1,i1,s1n,s0);
and (y2,i2,s1,s0n);
and (y3,i3,s1,s0);
or (out,y0,y1,y2,y3);
endmodule
DATAFLOW
module multiplexer4_1 ( din ,sel ,dout );
output dout ;
input [3:0] din ;
input [1:0] sel ;
assign dout = (sel==2'b00) ? din[3] :
(sel==2'b01) ? din[2] :
(sel==2'b10) ? din[1] :
din[0];
endmodule
BEHAVIOURAL
module mux4(mux_out, data_3,data_2, data_1, data_0,select,enable);
output [3:0] mux_out;
input [3:0] data_3,data_2,data_1,data_0;
input [1:0] select;
input enable;
reg [3:0] mux_int;
assignmux_out=enable? mux_int:4'bz;
always@(data_3 or data_2 or data_1 or data_0 or select)
case(select)
0: mux_int=data_0;
1: mux_int=data_1;
2: mux_int=data_2;
3: mux_int=data_3;
default:mux_int=4'bx; //May execute in simulation
endcase
endmodule
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TEST BENCH
moduletestMux;
// Inputs
reg [3:0] data_3;
reg [3:0] data_2;
reg [3:0] data_1;
reg [3:0] data_0;
reg [1:0] select;
reg enable;
// Outputs
wire [3:0] mux_out;
// Instantiate the Unit Under Test (UUT)
mux4uut (.mux_out(mux_out), .data_3(data_3), .data_2(data_2), .data_1(data_1),
.data_0(data_0), .select(select), .enable(enable));
initial begin
// Initialize Inputs
data_3 = 0;data_2 = 0;data_1 = 0;data_0 = 0;select = 0;enable = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
enable = 1;
data_3 = 4'b1010;
data_2 = 4'b1000;
data_1 = 4'b1100;
data_0 = 4'b0110;
#100 select= 2'b00;
#100 select= 2'b01;
#100 select= 2'b10;
#100 select= 2'b11;
#1 $stop;
end
endmodule
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SIMULATION OUTPUT:
DEMULTIPLEXER
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DEMULTIPLEXER
STRUCTURAL
module Dux1to4(in, s0, s1, out0, out1, out2, out3);
input in, s0, s1;
output out0, out1, out2,out3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and (out0,in,s1n,s0n);
and (out1,in,s1n,s0);
and (out2,in,s1,s0n);
and (out3,in,s1,s0);
endmodule
DATAFLOW
module demultiplexer4_1 ( din ,sel ,dout );
output [3:0] dout ;
input din ;
input [1:0] sel ;
assign dout[3] = (sel==2'b00) ? din : 1'b0;
assign dout[2] = (sel==2'b01) ? din : 1'b0;
assign dout[1] = (sel==2'b10) ? din : 1'b0;
assign dout[0] = (sel==2'b11) ? din : 1'b0;
endmodule
BEHAVIOURAL
module 1x4demux(input wire a, //inputs declaration
input wire[1:0] sel,
outputreg y1, //outputs declaration
outputreg y2,
outputreg y3,
outputreg y4);
//logic for 1x4demux
always@(sel or a)
case(sel)
2’b00:begin
y1=a;y2=1’b0;y3=1’b0;y4=1’b0;
end
2’b01:begin
y1=1’b0;y2=a;y3=1’b0;y4=1’b0;
end
2’b10:begin
y1=1’b0;y2=1’b0;y3=a;y4=1’b0;
end
2’b11:begin
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y1=1’b0;y2=1’b0;y3=1’b0;y4=a;
end
endcase
endmodule
TESTBENCH
moduletestdemux;
// Inputs
reg din;reg [1:0] sel;
// Outputs
wire [3:0] dout;
// Instantiate the Unit Under Test (UUT)
demultiplexer4_1uut (.din(din), .sel(sel), .dout(dout));
initial begin
// Initialize Inputs
din = 0;sel = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
din = 1;
#100 sel= 2'b00;
#100 sel= 2'b01;
#100 sel= 2'b10;
#100 sel= 2'b11;
end
endmodule
RESULT
Thus a 4x1 Multiplexer and Demultiplexerare designed using Verilog HDL and
its functioning is verified
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CIRCUIT DIAGRAM
ENCODER
DECODER
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Ex.No:5 ENCODER AND DECODER
AIM
To design an encoder and decoder using Verilog HDL, verify their function, by
simulating in Xilinx
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. Verify the output waveform as obtained.
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ENCODER – TRUTH TABLE
INPUTS OUTPUT
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 E0 E1 E2
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
SIMULATION OUTPUT
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VERILOG CODE: - ENCODER
Structural
Module encoder_structural(y0,y1,y2,y3,y4,y5,y6,y7, e0,e1,e2);
input y0,y1,y2,y3,y4,y5,y6,y7;
output e0,e1,e2;
wire w1,w2,w3,w4,w5,w6;
or or1(w1, y7, y6);
or or2(w2,y5,y4);
or or3(e0,w1,w2);
or or4(w3, y7, y6);
or or5(w4,y3,y2);
or or6(e1,w3,w4);
or or7(w5, y7, y5);
or or8(w6,y1,y3);
or or9(e2,w5,w6);
endmodule
Dataflow
Module encoder_behavioral(y0,y1,y2,y3,y4,y5,y6,y7, e0,e1,e2);
input y0,y1,y2,y3,y4,y5,y6,y7;
output e0,e1,e2;
assign e0 = (y7 | y6 | y5 | y4);
assign e1 = (y7 | y6 | y3 | y2);
assign e2 = (y7 | y5 | y3 | y1);
endmodule
Behavioral
Module encoder_4to2_behavioral(y0,y1,y2,y3, e0,e1);
input y0,y1,y2,y3,y4;
output e0,e1;
if (y0 ==1 & y1 == 0 & y2 ==0 & y3== 0) then
begin e0=0; e1=0; end
else if (y0 ==0 & y1 == 1 & y2 ==0 & y3== 0) then
begin e0=1; e1=0; end
else if(y0 ==1 & y1 == 0 & y2 ==0 & y3== 0);
begin e0=0; e1=1; end
else
begin e0=1; e1=1; end
endif
endmodule
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TESTBENCH
moduletestentt;
// Inputs
reg y0, y1, y2, y3;
// Outputs
wire e0, e1;
// Instantiate the Unit Under Test (UUT)
encoder_behavioraluut (.y0(y0), .y1(y1), .y2(y2), .y3(y3), ..e0(e0), .e1(e1));
initial begin
// Initialize Inputs
y0 = 0; y1 = 0; y2 = 0; y3 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
y0 = 1;y1 = 0; y2 = 0;y3 = 0;
#100 y0 = 0;y1 = 1; y2 = 0;y3 = 0;
end
endmodule
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DECODER – TRUTH TABLE
INPUTS OUTPUTS
E0 E1 E2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
SIMULATION OUTPUT:
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DECODER
moduledec(Data, Code);
output [7:0] Data;
input [2:0] Code;
reg [7:0] Data;
always @ (Code)
begin
if(Code==0) Data=8'b00000001;else
if(Code==1) Data=8'b00000010;else
if(Code==2) Data=8'b00000100;else
if(Code==3) Data=8'b00001000;else
if(Code==4) Data=8'b00010000;else
if(Code==5) Data=8'b00100000;else
if(Code==6) Data=8'b01000000;else
if(Code==7) Data=8'b10000000;else
Data=8'bx;
end
endmodule
RESULT: Thus an encoder and decoder are designed using Verilog HDL and its functioning is
verified
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CIRCUIT DIAGRAM
D-FLIP FLOPS
EXCITATION TABLE
SET RESET D CLK Q Qbar
0 1 - - 1 0
1 0 - - 0 1
0 0 - - 1 0
1 1 1 rising 1 0
1 1 0 rising 0 1
JK-FLIP FLOPS
EXCITATION TABLE
J K Q(t+1)
0 0 Q(t) no
change
0 1 0(reset to 0)
1 0 1(set to 1)
1 1 Qbar(t)
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59
Ex.No:6 FLIP FLOPS
AIM:
To design the basic sequential element flipflopusing Verilog HDL, verify its function, by
simulating in Xilinx
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. verify the output waveform as obtained.
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SIMULATION OUTPUT:
D-FLIPFLOP
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VERILOG CODE:
D- FLIPFLOP
moduleD_ff( q,d,Clock,Reset);
output q;
inputd,Clock,Reset;
reg q;
always @(posedge Clock or negedge Reset)
if (Reset == 0)
q<=1'b0;
else
q<=d;
endmodule
TESTBENCH
moduleTestDff;
// Inputs
reg d; reg Clock; reg Reset;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
D_ffuut (.q(q), .d(d), .Clock(Clock), .Reset(Reset) );
initial begin
// Initialize Inputs
d = 0; Clock = 0; Reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#50 Reset=0;d=1;
#50 d=0;
#50 Reset=1; d=1;
#50 d=0; #50 d=1;
#50 Reset=0; d=0;
#50; // Gap for display.
#50 $stop;
end
always #50 Clock = ~Clock;
endmodule
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SIMULATION OUTPUT:
JK FLIPFLOP
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JK FLIPFLOP modulejkflop(j,k,clk,rst,q);
inputj,k,clk,rst;output q;reg q;
always @(posedgeclk or posedgerst)begin
if (rst == 1) begin
q <= 0;
end
else if(j==1 & k==1 &rst==0)begin
q <=~q; //Toggles
end
else if(j==1 & k==0 &rst==0)begin
q <= 1; //Set
end
else if(j==0 & k==1)begin
q <= 0; //Cleared
end
end
endmodule
TESTBENCH moduletestJk;
reg j; reg k; regclk;regrst;wire q;
// Instantiate the Unit Under Test (UUT)
jkflopuut (.j(j), .k(k), .clk(clk), .rst(rst), .q(q));
initial begin
// Initialize Inputs
j = 0;k = 0;clk = 0;rst = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#2 j=0; k=1;
#2 j=1; k=0;
#2 j=1; k=1;
#2 rst=0;j=0; k=0;
#2 j=0; k=1;
#2 j=1; k=0;
#2 j=1; k=1;
#2 rst=1; j=0; k=0;
#1; #2 $stop;end
always #1 clk=~clk;
endmodule
RESULT
Thus, the sequential elements D-Flipflop , JK – Flipflop were designed implemented and their
outputs verified.
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CIRCUIT DIAGRAM
2-BIT COUNTER
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Ex.No:7A 2_BIT COUNTER
AIM:
To design a 2 bit counter using Verilog HDL, verify its function, by simulating in Xilinx
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. Verify the output waveform as obtained.
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SIMULATION OUTPUT
2 BIT COUNTER
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VERILOG CODE
module Count2Bit(Clock, Clear, out);
input Clock, Clear;
output [1:0] out;
reg [1:0]out;
always@(posedge Clock, negedge Clear)
if((~Clear) || (out>=4))
out=2'b00;
else
out=out+1;
endmodule
TEST BENCH
moduletestcount;
// Inputs
regClock;reg Clear;
// Outputs
wire [1:0] out;
// Instantiate the Unit Under Test (UUT)
Count2Bit uut (.Clock(Clock), .Clear(Clear), .out(out));
initial begin
// Initialize Inputs
Clock = 0;Clear = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#10 Clear=1;
#18 Clear=0;
#2 $stop;
end
always #1 Clock=~Clock;
endmodule
RESULT
Thus a 2 bit counter is designed using Verilog HDL and its functioning is verified using
Xilinx tool.
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CIRCUIT DIAGRAM:
UP-DOWN COUNTER
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69
Ex.No:7B UP/DOWN COUNTER
AIM:
To design an up/down counter using Verilog HDL, verify its function, by simulating in
Xilinx.
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. verify the output waveform as obtained.
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SIMULATION OUTPUT
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VERILOG CODE:
module count1(count, up_dwn, clock, reset_);
output [2:0] count;
input [1:0] up_dwn;
input clock,reset_;
reg [2:0] count;
always @(negedge clock or negedge reset_)
if(reset_ == 0) count <= 3'b0;else
if(up_dwn == 2'b00 || up_dwn == 2'b11) count<=count; else
if(up_dwn == 2'b01) count<=count+1;else
if(up_dwn == 2'b10) count<=count-1;
endmodule
TESTBENCH
moduletestUDCount;
// Inputs
reg [1:0] up_dwn; reg clock; reg reset_;
// Outputs
wire [2:0] count;
// Instantiate the Unit Under Test (UUT)
count1uut (.count(count), .up_dwn(up_dwn), .clock(clock), .reset_(reset_) );
initial begin
// Initialize Inputs
up_dwn = 0; clock = 0; reset_ = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset_=0;
#30 reset_=1; up_dwn = 2'b01;
#10 up_dwn = 2'b00;
#10 up_dwn = 2'b10;
#10 up_dwn = 2'b11;
#10 reset_=0;
#2 $stop;
end
always #1 clock=~clock;
endmodule
RESULT:
Thus a Up-Down counter is designed using Verilog HDL and its functions verified in
Xilinx and FPGA Kit.
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CIRCUIT DIAGRAM
MOD 7 COUNTER
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Ex.No:7C MOD 7 COUNTER
AIM
To design a mod 7 counter using Verilog HDL, verify its function, by simulating in
Xilinx
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. Verify the output waveform as obtained.
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SIMULATION OUTPUT
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VERILOG CODE
module counter_mod7 ( clk ,reset ,dout );
output [2:0] dout ;
reg [2:0] dout ;
inputclk ;wire clk ;input reset ;wire reset ;
initialdout = 0;
always @ (posedge (clk)) begin
if (reset)
dout<= 0;
else if (dout<6)
dout<= dout + 1;
else
dout<= 0;
end
endmodule
TESTBENCH
module testmod7;
// Inputs
regclk;reg reset;
// Outputs
wire [2:0] dout;
// Instantiate the Unit Under Test (UUT)
counter_mod7uut (.clk(clk), .reset(reset), .dout(dout));
initial begin
// Initialize Inputs
clk = 0;reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset =1;
#10 reset = 0;
#100 $stop;
end
always #1 clk=~clk;
endmodule
RESULT
Thus a Mod 7 counter is designed using verilog HDL and verified in FPGA after
implementation with the help of Xilinx.
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CIRCUIT DIAGRAM
SHIFT REGISTERS - SIPO
SHIFT REGISTERS – PISO
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Ex.No:8 SHIFT REGISTER
AIM
To design a SIPO and PISO shift register using Verilog HDL, verify its function, by
simulating in Xilinx
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. Verify the output waveform as obtained.
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SIMULATION OUTPUT
SIPO
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VERILOG CODE:
SIPO
module SIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;wire [3:0] dout ;
inputdin,clk,reset;
wiredin,clk,reset;
reg [3:0]s;
always @ (posedge (clk)) begin
if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end
assigndout = s;
endmodule
TESTBENCH
moduletestSIPO;
// Inputs
reg din;regclk;reg reset;
// Outputs
wire [3:0] dout;
// Instantiate the Unit Under Test (UUT)
SIPO uut (.din(din), .clk(clk), .reset(reset), .dout(dout));
initial begin
// Initialize Inputs
din = 0;clk = 0;reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1;
#100 reset =0 ;din=1;
#10 din = 0;
#10 din = 1;
#20 din = 1;
end
always #1 clk = ~clk;
endmodule
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SIMULATION OUTPUT
PISO
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PISO
moduleparallel_in_serial_out ( din ,clk ,reset ,load ,dout );
outputdout ;regdout ;
input [3:0] din ;input clk,reset,load ;
wire [3:0] din ;wire clk,reset,load ;
reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
temp<= 1;
else if (load)
temp<= din;
else begin
dout<= temp[3];
temp<= {temp[2:0],1'b0};
end
end
endmodule
TESTBENCH
moduletestPISO;
// Inputs
reg [3:0] din;
regclk, reset, load;
// Outputs
wiredout;
// Instantiate the Unit Under Test (UUT)
parallel_in_serial_outuut (.din(din), .clk(clk), .reset(reset), .load(load),
.dout(dout));
initial begin
// Initialize Inputs
din = 0;clk = 0;reset = 0;load = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset=1;
#10 reset = 0;
#10 load = 1; din=4'b1000;
#10 load = 0;
end
always #1 clk = ~clk;
endmodule
RESULTS
Thus SISO and PISO shift registers are designed using Verilog and functionally verified
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BLOCK DIAGRAM:
PRBS GENERATOR
ACCUMULATOR :
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Ex.No: 9 PRBS GENERATOR AND ACCUMULATOR
AIM
To design a PRBS generator and accumulator using Verilog HDL, verify its function, in
Xilinx,
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. verify the output waveform as obtained.
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SIMULATION RESULT- ACCUMULATOR
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VERILOG CODE
moduleupaccm(clk,reset,q,d);
input reset;input clk;input [5:0]d;output reg [5:0]q;
//reg [3:0]temp;
always @(posedgeclk or negedge reset)
begin
if(~reset)
q=4'b0000;
else
q=q+d;
end
//assign q=temp;
endmodule
TESTBENCH
moduletestaccum;
// Inputs
regclk;reg reset;reg [5:0] d;
// Outputs
wire [5:0] q;
// Instantiate the Unit Under Test (UUT)
upaccmuut ( .clk(clk), .reset(reset), .q(q), .d(d));
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
d = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1;
# 50 d=4'b0010;
#200 reset = 0;
#50 reset = 1;
end
always #50 clk = ~clk;
endmodule
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SIMULATION OUTPUT- PRBS GENERATOR
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VERILOG CODE:
moduleprbsGenerator(rand,clk,reset);
inputclk,reset;output rand;wire rand;reg[3:0]temp;
always@(posedge reset)
temp<=4'hf;
always@(posedgeclk)
begin
if(~reset)
temp<={temp[0]^temp[1],temp[3],temp[2],temp[1]};
end
assign rand=temp[0];
endmodule
TESTBENCH
modulemainprbs;
regclk,reset;wire rand;
prbsGeneratorpr(rand,clk,reset);
initial begin
forever begin
forever begin
clk<=0;#5clk<=1;#5clk<=0;
end
end
end
initial begin
reset=1;#12reset=0;#90reset=1;#12reset=0;
end
endmodule
RESULT:
Thus a PRBS Generator and Accumulator are designed using Verilog HDL and verified
by simulation in Xiinx and implementation in FPGA.
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BLOCK DIAGRAM
RCA ADDER – 4BIT
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Ex.No:10A 8 BIT ADDER
AIM:
To design an 8 bit adder using Verilog HDL, verify its function, by simulating in Xilinx.
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. Verify the output waveform as obtained.
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VERILOG CODE
module add_RCA_8(sum,c_out,a,b,c_in);
output[7:0] sum;
outputc_out;
input[7:0] a,b;
inputc_in;
wire c_in2, c_in3, c_in4, c_in5, c_in6, c_in7,c_in8;
Add_fullM1(sum[0],c_in2,a[0],b[0],c_in);
Add_fullM2(sum[1],c_in3,a[1],b[1],c_in2);
Add_fullM3(sum[2],c_in4,a[2],b[2],c_in3);
Add_fullM4(sum[3],c_in5,a[3],b[3],c_in4);
Add_fullM5(sum[4],c_in6,a[4],b[4],c_in5);
Add_fullM6(sum[5],c_in7,a[5],b[5],c_in6);
Add_fullM7(sum[6],c_in8,a[6],b[6],c_in7);
Add_fullM8(sum[7],c_out,a[7],b[7],c_in8);
endmodule
moduleAdd_full(sum,c_out,a,b,c_in);
outputsum,c_out;
inputa,b,c_in;
wire w1,w2,w3;
Add_halfM1(w1,w2,a,b);
Add_halfM2(sum,w3,w1,c_in);
or M3(c_out,w2,w3);
endmodule
moduleAdd_half(sum,c_out,a,b);
outputsum,c_out;
inputa,b;
xor M1(sum,a,b);
and M2(c_out,a,b);
endmodule
DATAFLOW
module adder(a,b, s,c);
input [7:0] a,b;
output [7:0] s,c;
assign {c,s} = a + b;
endmodule
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SIMULATION OUTPUT
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TESTBENCH
moduleTestRCA;
// Inputs
reg [7:0] a;reg [7:0] b;
// Outputs
wire [7:0] s; wire [7:0] c;
// Instantiate the Unit Under Test (UUT)
adderuut (.a(a), .b(b), .s(s), .c(c));
initial begin
// Initialize Inputs
a = 0; b = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a=8'b00000001;b=8'b00000001;
#100 a=8'b01000001;b=8'b01001001;
end
endmodule
RESULT:
Thus a 8 bit adder is designed using Verilog HDL and its functioning is verified in Xilinx
and FPGA kit.
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BLOCK DIAGRAM
MULTIPLIER
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Ex.No:10B 4 BIT MULTIPLIER
AIM:
To design a 4 bit multiplier using Verilog HDL, verify its function, by simulating in
Xilinx
APPARATUS REQUIRED:
1. Xilinx ISE 8.1i
2. ModelSim SE Plus 5.7g
3. XC3S400 FPGA Kit, Manual
4. Power Supply
PROCEDURE
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. Verify the output waveform as obtained.
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VERILOG CODE
STRUCTURAL
module HA(sout,cout,a,b);
outputsout,cout;
inputa,b;
assignsout=a^b;
assigncout=(a&b);
endmodule
module FA(sout,cout,a,b,cin);
outputsout,cout;
inputa,b,cin;
assignsout=(a^b^cin);
assigncout=((a&b)|(a&cin)|(b&cin));
endmodule
module multiply4bits(product,inp1,inp2);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
assign product[0]=(inp1[0]&inp2[0]);
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule
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SIMULATION RESULT
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DATAFLOW
module multi(a,b, c);
input [3:0] a,b;
output [7:0] c;
assign c = a * b;
endmodule
TESTBENCH
moduleTestMulti;
// Inputs
reg [3:0] a;reg [3:0] b;
// Outputs
wire [7:0] c;
// Instantiate the Unit Under Test (UUT)
multiuut (.a(a), .b(b), .c(c));
initial begin
// Initialize Inputs
a = 0;b = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a=4'b0001;b=4'b0010;
#100; a=4'b0101;b=4'b0010;
end
endmodule
RESULT:
Thus a 4 bit multiplier is designed using Verilog HDL and its functioning verified in
Xilinx and FPGA kit
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