advanced micro 2

7/31/2019 Advanced Micro 2

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8086 has a

In a maximum mode 8086 system, the8086 operates in maximum mode bystrapping its MN/MX pin to-8088 has a

In 8086

Which Flags can be set or reset bythe programmer and also used tocontrol the operation of theprocessor?What physical address correspondsto SI:103Fh if DS=94D0hMaximum clock frequency in 8086-

What are the names of the 4 segmentregisters?

BUS HIGH ENABLE of 8086microprocessor signal is used tointerface theIn 8086 microprocessor one of thefollowing statements is not true.

8088 microprocessor differs with8086 microprocessor in

An overflow flag is set if foraddition

When Direction flag is set

How much memory space does the8086 have?

The segment that holds programsand procedures used by programsRefer figure 10

Refer figure 11

The queue status lines QS1=1,QS0=0 indicates

Qstn

4 bytes queue

logic 1

4 bytes queue

Address/ Datalines aremultiplexed

Overflow Flag

103Fh

5 MHz

Data, Index,Code, Stack

Even bankmemory

Coprocessoris interfacedin MAX mode

Data width onthe output

There is nocarry intoMSB & nocarry out of

MSB

The string isprocessedfrom thehigheraddresstowards thelower address

4 MB ofmemory

Code segment

Minimum mode

Read memory

No operation

A

6 bytesqueuelogic 0

6 bytesqueueAddress/Data,Address/Status linesaremultiplexed

Carry Flag

94D0h

3 MHz

Stack,Index,Extra, Code

Odd bankmemory

Coprocessorisinterfacedin MIN modeAddresscapability

There iscarry intoMSB & carryout of MSB

The stringisprocessedfrom theloweraddresstowards thehigheraddress

2 MB ofmemory

DatasegmentMaximummodeWritememoryFirst byteof opcodefrom thequeue

B

8 bytesqueueNC

8 bytesqueueAddress/Status,Address/Controllines aremultiplexedInterruptFlag

95D3Fh

10 MHz

Stack,Data,Base,Counter

I/O

I/O can beinterfacedin MAX /MIN modeSupport ofcoprocessorThere is acarry intoMSB & nocarry out

of MSB &vice-versaThe stringisprocessedfrom itsbeginningwith thefirstelementhaving thelowestaddress1 MB ofmemory

ExtrasegmentReal mode

Read I/OportEmptyqueue

C

16 bytqueueNone

16 bytqueueAddresntrol,Addresatue laremultipdSign F

95D00h

None

Stack,Extra,Code,

DMA

Supporpipeli

SupporMAX / modeNone othese

None othese

64 KB memory

StacksegmenProtecmodeWrite portSubseqbyte fthe qu

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One of the following pin is notavailable in maximum modeOne of the following pin is notavailable in minimum modeHow many bits wide is the addressbus on the 8086 Processor?The 8086 has 4 segment registers

The 8086/8088 architecture dividedinto two processing units whichwere known as:

The 8086 is ------ bit processor?

Refer figure 19

In 8086 microprocessor one of thefollowing statements is not true.


The stack pointer stores

If Bus high enable pin is at logic0 then the ------ memory bank isselected.For string instructions DI alwaysaddresses data in the ----------segment8088 has a

When direction flag is set

The queue status lines QS1=1,QS0=0indicates

The 8086/8088 architecture dividedinto two processing units whichwere known as:


If bus high enable pin is at logic0 then the ----------memory bank is

Qstn

Refer Figure13ARefer Figure14A8-bits

Data, Index,Code, Stack

Left andRight Units

4-bit

Even bankmemoryCoprocessoris interfacedin MAX mode


the addressof the stackin memory

Even

Data

4 byte queue

The string isprocessedfrom higheraddresstowards thelower address

No operation

left & rightunits


Even

A

ReferFigure 13BReferFigure 14B16-bits

Stack,Index,Extra, Code

Segment andOffsetUnits

8-bit

Odd bankmemoryCoprocessorisinterfacedin MIN modeAddresscapability

address ofthe lastitem pushedon thestack

odd

Stack

6 bytes

queueThe stringisprocessedfrom loweraddresstowards thehigheraddress

First byteof opcodefrom queue

segment &offset unit

Addresscapability

odd

B

ReferFigure 13CReferFigure 14C20-bits

Stack,Data,Base,CounterALU andControlUnit

16-bit

I/O

I/O can beinterfacedin MAX /MIN modeSupport ofcoprocessor

theaddress ofthe nextfree stacklocation

both

Code

8 bytes

queueThe stringisprocessedfrom itsbeginningwith thefirstelementhavinglowestaddressEmptyqueue

ALU &controlunits

Support ofCoprocessorboth

C

QS0

ALE

24-bit

Stack,Extra,Code,

BusInterfUnit aExecutUnit32-bit

DMA

Supporpipeli

SupporMAX / mode

theaddresthe laitempoppedfrom tstacknone

Extra

16 byt

queueNone othese

subseqbyte fthe qu

Businterfunit &executunitSupporMAX/MImodeNone

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selected

A 20-bit address bus allows accessto a memory of capacityHow many bits wide is the addressbus on the 8086 Processor?How many transistors does the 8086have?The 8086/8088 used two processoringunits which were known as:

The read/write line :

Calculate the beginning and endingaddress of the data segmentassuming register DS= E000HIf (cs)=123A and (IP)=341B thenphysical address of instruction is8086 uses ------ register as I/Oaddress pointer and can addressupto ---- devices.The control flag register of 8086

consists of following flags.Physical memory of 8086 is dividedinto ----- segments and eachsegment size is ------In 8086, the size of ALU is ------size of Flag register is -----After performing the addition of5439H + 456AH, the flags would be

If (CS)=123A and (IP)=341B, thenthe physical address of instructionisLOOP instruction loops to thespecified label until

What is the output of the followingcodeAL=00110101 BL= 39HSUB AL, BLAASWhat is the output of the followingcode?CF =0, BH = 179RCL BH, 1Which is the flag manipulationinstruction?Which is the unconditional branchinstruction?For the instruction LOOPE/LOOPZ,what should be condition for exit?

IDIV and DIV instructions performthe same operations for?

The conditional branch instructionJNS performs the operations when-To repeat a string in structionwhile particular condition is zerouse the instructionThe instruction MOV AX,[BX][SI] is

Qstn

1MB

8-Bits

10,000

Left andRight Units

belongs tothe data bus

E00000,EFFFF.

46550

DX,64K

CY,Z,T

32,64K

32,26

SF=0,ZF=0,PF=0,CF=0,AF=,0OF=046550

DX=0

AL= 00000100,CF=1

CF=0, OF= 1,BH= 01100101

TEST

JLE/JNC

CX=0

Unsignednumber

ZF =0

REP

Register

A

2 MB

16-Bits

29,000

Segment andOffsetUnits

belongs tothe controlbus

E10000,EEFFF.

123A0

AX,64K

O,D,I

16,16K

16,16

SF=1,ZF=0,PF=1,CF=0,AF=1,OF=1123A0

BX=0

BL=00000100, CF=0

CF=1, OF=1,BH=01100110

AND

CALL/RET

ZF=0

Signednumber

SF=0

REPE

Indexed

B

32MB

20-Bits

110,000

Bus UnitandExecution

InterfaceUnitbelongs totheaddressbus00000,FFFFF.

157BB

CX,64K

O,T,S

16,64K

32,32

SF=1,ZF=0,PF=1,CF=0,AF=1,OF=0157BB

AX=0

AL=11111100 CF=1

CF=1, OF=0, BH=01001101

STD

JP/JPE

CX=1 orZF=1

Signednumber &UnsignednumberPF=0

REPZ

Direct

C

64 MB

24-Bit

129,00

ALU anControUnit

CPU bu

E0000,F.

341B0

AX,32K

D,I,T

32,32K

16,32

SF=1,ZPF=1,CAF=1,O341B0

CX=0

BL=0000, CF=

CF=0,OF=0,BH=0010None

JO

CX=0 oZF=0

None oabove

CF=0

C & B

Based

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an example of

Which of following is an illegalinstructionLOOP instruction loops to thespecified label untillEND assembler directive used to

DIV instruction

In 8086 microprocessor one of thefollowing instructions is executedbefore an arithmetic operationNEG instruction

In MUL instruction the result isstored in

IN Instruction

OUT Instruction

DIV Instruction

IDIV Instruction

DT assembler directive used to

END assembler directive used to

Qstn

indirectaddressingMOV AX,30000

DX=0

End program

Divide anunsigned wordby byte orunsigneddouble wordby word

AAM

Replaces thenumber in adestinationwith the 2scomplement of

that number

AX or DX-AXregister

Copy datafrom memorylocation toaccumulator

Copy datafrom memorylocation toaccumulator

Divide anunsigned wordby a byte orunsigneddouble wordby a word

Divide anunsigned wordby a byte or

unsigneddouble wordby a word

DefineDoublewordEnd Program

A

adddressing

INC AL

BX=0

EndprocedureDivide anunsignedword byword orunsigneddouble wordby doubleword

AAD

Replacesthe numberin adestinationwith the

1scomplementof thatnumberAX or CX-AXregister

Copy datafromaccumulatorto memory

Copy datafromaccumulatorto memory

Divide anunsignedword by aword orunsigneddouble wordby a doubleword

Divide anunsignedword by a

word orunsigneddouble wordby a doubleword

Define QuadwordEndProcedure

B

addressing

AND BX,DX

AX=0

EndsegmentDivide asignedword bybyte orsigneddoubleword byword

DAS

Replacesthe numberin adestination with the

9scomplementof thatnumberAX or CX-AXregisterCopy datafrom aport toaccumulatorCopy datafrom aport toaccumulatorDivide ansignedword by abyte orsigneddoubleword by aword

Divide ansignedword by a

byte orsigneddoubleword by aword

Define TenbytesEndSegment

C

IndexeaddresADD AX

CX=0

None otheseDividesignedword bword osigneddoubleword bdoublewordDAA

None othese

None othese

Copy dfromaccumur to aportCopy dfromaccumur to aportDividesignedword bword osigneddoubleword bdoublewordDividesignedword b

word osigneddoubleword bdoublewordDefinewordsNone othese

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Which of the following instructionused to complement the contents ofcarry flagCMC instruction

INC instruction

What is opcode

Which of the following is anillegal instructionAn interrupt instruction

The program counter

The call instruction is used to

The instruction MOV AX, [BX] is anexample of

The instruction MOV AX, [BX] [SI]is an example of

The call instruction stores thereturn address for a subprogram

The instruction JE label is anexample ofThe 8086 LOOP instructiondecrements register ------- andtest it for 0 to decide if

jump occurs.The last executable instruction inprocedure is ---------MOV AX, [BX][SI] denotes which typeof addressing mode of 8086?FSTENV instruction means

The instruction MOV AX, DATA movesthe ________address of DATA in AX.To repeat a string instructionswhile particular condition is zerouse the instructionThe conditional branch instructionJNS performs the operations when__Consider CF=0

MOV CL, 02

Qstn

STC

Complementsaccumulator

One byteinstruction

Theinstructionthat is to beexecutedMOV AX,30000

causes anunconditionaltransfer ofcontrolstores theaddress oftheinstructionthat iscurrently

beingexecutedaccesssubprogramRegisterindirectaddressingRegisterindirectaddressingon the stack

indirectaddressingAX

IRET

Relativebased indexedStore evennumbervariables

Offset

REP

ZF =0

DX=D652 HCF=1

A

CTC

Complementscarry

Two byteinstruction

The valuein which anoperationacts uponINC AL

causes aconditionaltransfer ofcontrolstores thenextinstructionto beexecuted

accessmemoryindexedaddressing

indexedaddressing

in thememoryaddressregister

indexedaddressingBX

RET

Indexed

Storeenvironments

E.A.

REPE

SF=0

DX=D652 HCF=0

B

CMC

ComparesaccumulatorThree byteinstructionA mnemonicthatdefines adata sizeAND BX,DXmodifiesthe statusregister

stores theaddress ofthe nextinstruction to beexecuted

performI/ODirectaddressing

directaddressing

in theprogramcounter

RelativeaddressingCX

JUMP

BasedIndexedFloatingpointstorenumber

Base

REPZ

PF=0

DX=EB29HCF=0

C

CLI

Comparcarry

Four binstrunThecompilassembcodeADD AX

is an instrun

storesinstrun thatbeingcurrenexecut

accessstackbasedindexeaddresbasedindexeaddresdoes ninvolvusing returnaddresDirectaddresDX

CALL

RegistRelatiStore number

segmen

c& d

CF=0

DX=EB2CF=1

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HMOV DX, ACA5H

SAR DX, CL What is the

resultConsider CF=1, BL=00111000 RCR BL,1 What is the result afterexecution of this instructionGiven that (BX)=0158 H, (DI)=10A5H, Displacement=1B57 H, and(DS)=2100 H, the effective address& physical address produced byregister indirect addressing modeis (Assume register BX)If AL=09H, BL=08 H Instructionsequence MULBL , AAM will store ----- in AX.Consider MOV AL, 59(BCD)MOV BL, 35(BCD)ADD AL, BLDAAWhat are the contents of AL afterexecution of these instructions ?What is the output of the followingcode-

AL= 00110100 BL= 00111000ADD AL, BLAAATo look up particular item in 256byte table use ________register asindex and ______ register topoint to the base of the tableWhat is the output of the followingcodeAL= -28 decimal, BL=59 decimalIMUL BLAX=? , MSB=?What is the output of the followingcodeAL= 49 BCD, BH= 72 BCDSUB AL, BHDASConsider CF=1,BL=00111000 RCR BL,1What is the result after executionof this instructionThe contents of different registersare given below. Form Effectiveaddresses for addressing modesgiven below :Offset = 5000H[AX]- 1000H, [BX]- 2000H, [SI]-3000H, [DI]- 4000H, [BP]- 5000H,[SP]- 6000H, [CS]- 0000H, [DS]-1000H, [SS]- 2000H, [IP]- 7000H

MOV AX, 5000H [BX] [SI]Given that the BL registercontains 1111 0000, the effect ofthe following instruction

OR BL, 0000 1111 istoGiven that AX=3F0F H and theinstruction XOR AX, 0098 Hexecuted. What is the resultWhat is the output of the following

Qstn

CF=1,BL=10011100

EA=1B57 HPhysicalAddress=22B57

0072

AL=8E H

AL = 6CH

SI, BX

AX= F98CH,MSB=1

AL=D7, CF=1.

CF=1,BL=10011100

20000H

Clear BL

AX=1100 H

0101110011010

A

CF=1,BL=00011100

EA=0158 HPhysicalAddress=21158

0702

AL=94 BCD

12

AL, DX

AX= 1652,MSB=1

AL=7D,CF=1.

CF=1,BL=00011100

1A000H

Store 11111111 in BL

AX=3F96 H

11010011010

B

CF=0,BL=00011100EA=1CAFHPhysicalAddress=22CAF

0207

AL=9E H

12H

AL, BX

BX F9C8H,MSB=1

AL=77,CF=1

CF=0,BL=00011100

1A00H

Store 00001111 in BL

AX=3F97 H

0110100010

C

CF=0,BL=1000None othese

48

None othese

C6H

CL, DX

BX= 16MSB=1

None

CF=0,B011100

None

Leave unchan

Ax=2E9

101110

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codeBX=23763 CL=8ROL BX, CLGiven that (BX)=0158 H ,(DI)=10A5H , Displacement=1B57 H , and(DS)=2100 H, the effective address& physical address produced bydirect addressing mode isThe call instruction is used to

To copy the hexadecimal number A tothe bh register you writeThe effect of the followinginstructions

mov ah, 2hint 21h is to

The effect of the followinginstructions

mov ah, 1hint 21h

is toWhich of the following is an

illegal 8086 instructionThe read/write line is

The call instruction stores thereturn address for a subprogram

The instruction je label is anexample ofGiven that dl contains 'x' which ofthe following will cause 'x' to bedisplayed:Which of the following will read acharacter into al:

Which of the following will displaya string whose address is in the dxregister:

The cmp instruction modifies the

Conditional instructions typicallyinspect theThe bp register is typically usedfor accessingThe ret instruction modifies the

The sp register is typically usedfor accessingThe call instruction modifies

An instruction consists of

Macro expanded into machine code itrepresents when it is,

Qstn

011, CF=0

EA=1B57 HPhysicalAddress=22B57

accesssubprogramsleave it withits originalvaluemov 0bh, ah

read acharacterinto ah

read acharacterinto al

ret 2

belongs tothe data bus

on the stack

indirectaddressingmov ah, 1hInt 21h

mov ah, 9hint 20hmov ah, 0h

Int21h

programcounterprogramcounterstrings

instruction

registerstrings

the flagsregister

Data andAddressAssembled

A

11100, CF=0

EA=0158 HPhysicalAddress=21158

accessmemoryadd 4 to it

mov bh,0ahread acharacterinto dl

read acharacterinto dl

push ax

belongs tothe controlbus

in thememoryaddressregister

indexedaddressingmov ah, 2h

Int16hmov ah, 2hint 21hmov ah, 2hInt 20h

instructionregisterinstructionregistermemory

program

countermemory

programcounter

Registerand MemoryLinked

B

011101,CF=1

EA=1CAFHPhysicalAddress=22CAF

performI/Oclear it

mov bh, ah

displaythecharacterin aldisplaythecharacterin ah

aDd bx,

25000belongs totheaddressbusin theprogramcounter

relativeaddressingmov ah, 2h

Int20hmov ah, 2hint 21hmov ah, 9h

Int21hflagsregisterflagsregisterstack

address

registerstack

bpregister

Opcode andOperandLoaded

C

001100CF=1

None othese

accessstackdouble

mov bh[ah]displathecharacin dldisplathecharacin dl

mov x,

CPU bu

does ninvolvusing returnaddresimmediaddresmov ah

In21hmov ah

intmov ah

22h

segmenregistaccumurdatasegmenflags

registdatasegmennone otheprevioInput Outputexecut

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An assembly language program istypically

Programs are written in assemblylanguage because they

An assembly language program istranslated to machine code by

An assembly language directive is

The output of the linker (LINKcommand) is stored in a file withthe extensionThe result of mov al, 65 is tostoreAssembly language program istranslated to machine code by

The result of MOV AL,65 is to store

To copy hexadecimal number A to BHregister you writeWhich of the following is anillegal 8086 instructionWhich of the following will displaya string whose address is in DXregisterThe RET instruction modifies the

Instructions INC AL and ADD AL,01Hincrtements AL register by 1. Frompoint of view of execution time,which instruction is preferable.The near jump is ________ while farjump is________

In case of 8086, near jump modifiesthe program address by changing

which register or registersIn case of 8086, Far jump modifiesthe program address by changingwhich register or registersIn JMP AX instruction, AX holds ------ address and is ----- type ofthe jump.Which conditional jump instructionstest both the Z and C flag bits.The near jump is ------------

Qstn

non-portable

runs fasterthan HLL

an assembler

the same asaninstruction

.lis

0100 0010 inalAn assembler

01000010 i nalmov 0bh,ah

ret 2

mov ah,0ahint 21h

instructionregisterADD AL,01

intersegment,intrasegment

IP

IP

offset, FAR

JG & JBE

intersegment,

A

shorterthan anequivalentHLL program

areportable

a compiler

used todefinespace forvariables

.obj

42H in al

a compiler

42h in al

mov bh,0ah

push ax

mov ah,02hint

20hprogramcounterINC AL

intersegment,intersegmentCS &IP

CS &IP

offset,NEAR

JA & JBE

intersegmen

B

harder toread thana machinecodeprogram

are easierto writethanmachinecodeprograms

aninterpreterused tostart aprogram

.exe

40H in al

aninterpreter40h in al

mov bh,ah

aDdbx,25000mov ah,9h

int21haddressregister

intrasegment,intrasegmentCS

CS

segment,NEAR

JC & JBE

intrasegme

C

slowerexecutthan acompilHLLprograAllowsprograto acctheregistorinstruns thaare nousuallprovidby a Ha link

to givcommanto anassemb

.lnk

0100 in ala link

010000in almovbh,[ahmov x,

mov ah

22hflagregist

intrasnt,intersntCS or

CS or

segmenFAR

JC & J

intras

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Ans

while far jump is -----------------.

What is the output of the followingcode AL=88 BCD, CL=49 BCD ADDAL, CL DAAWhat is the output of the followingcode?AL= 49 BCD, BH= 72 BCDSUB AL, BHDASWhat is the output of the followingcode?AL= -28 decimal, BL=59 decimalIMUL BLAX=? , MSB=?What is the output of the followingcodeAL= 00110100 BL= 00111000ADD AL, BLAAAWhat is the output of the followingcode?AL=00110101 BL= 39HSUB AL, BL

AAS

What is the output of the followingcode?CF =0, BH = 179RCL BH, 1What is the output of the followingcode?SI=10010011 10101101, CF=0SHR SI, 1What is the output of the followingcode?BX=23763 CL=8ROL BX, CLWhat is the output of the followingcode?AX = 37D7H, BH = 151 decimalDIV BHIn case of 8086, the LOOPinstruction decrements ------register and jumps to the labelwhen register is ------ 0.What is meant by Maskableinterrupts?

to transfer control to the addressstored I double word beginning ataddress 0084 H the softwareinterrupt _________ must be used.Which base register addresses datain stack?What does the INT21H instructionaccomplish if AH contains 4CH?The Push & POP instruction alwaystransfer ________ bits between

Qstn

intrasegment

D7, CF=1

AL=D7, CF=1.

AX= F98CH,MSB=1.

AL = 6CH

AL= 00000100,CF=1

CF=0, OF= 1,BH= 01100101

37805, CF=1,OF=1

0101110011010011, CF=0

AL = 65H, AH=94 decimal

DX, not equalto

An interruptthat can beturned off bytheprogrammer

Int21

BX

Read acharacter16

A

t,intersegment37, CF=1

AL=7D,CF=1.

) AX= 1652,MSB=1

12H

BL=00000100, CF=0

CF=1, OF=1,BH=01100110

18902,CF=1, OF=1

1101001101011100, CF=0

AL= 5EH,AH= 101decimal

CX, equalto

Aninterruptthat cannotbe turnedoff by theprogrammer.

Int21H

SP

Display acharacter24

B

nt,intrasegment73, CF=1

AL=77,CF=1

BX F9C8H,MSB=1.

12

AL=11111100 CF=1

CF=1, OF=0, BH=01001101

19820,CF=1, OF=1

0110100010011101,CF=1

AH= E5H,AL= 5EH

CX, notequal to

Aninterruptthat canbe turnedoff by thesystem.

Int42H

BP

Print acharacter32

C

nt,intersnt7D, CF

none othem

BX= 16MSB=1

C6H

) BL=000001CF=1

CF=0,OF=0,BH=001053708,CF=1,

101110001100CF=1

AL= 56AH= 5E

DX, eqto

Aninterrthatcannotturnedby thesystem

none othese

DX

Exit tDOS8

D


10/18

43617

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Tpc

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Mrk

B

A

B

A

A

C

A

D

A

C

B

B

D

B

D

Ans

stack & registeror memory

In RST interrupts, RST stands for

What is meant by Maskableinterrupts?

When an interrupt occurs, theprocessor completes the current___________ before jumping to theinterrupt service subroutineIn case of 8086, out of givenoptions which interrupt requiresacknowledgementAn interrupt instruction

Interrupts are classified as

An interrupt instruction

The NMI interrupts mechanism of the8086 microprocessor

Which interrupt have the highestpriority?Interrupts are classified as

When an Interrupt occurs theprocessor completes the current ----- before jumping to the interruptservice routineWhen an interrupt occurs, theprocessor completes the current___________ before jumping to theinterrupt service subroutineWhat is the output of the followingcode

Which interrupts are generally usedfor critical events such as Powerfailure, Emergency, Shut off etc.?The NMI interrupts mechanism of the8086 microprocessor

Qstn

Repeat StartTestAn interruptthat can beturned off bytheprogrammer.

microinstruction it isexecuting

INTR

causes anunconditionaltransfer ofcontrolHardwareinterrupts

Causes anunconditionaltransfer ofcontrolExecute aninstructionsupplied byan externaldevicethrough theINTA signalNMI

HardwareInterrupts

Microinstruction it isexecuting

microinstruction it isexecuting

Decrement SPby 2 & push aword to stack

Maskableinterrupts

execute aninstructionsupplied byan externaldevicethrough the

A

Restart

Aninterruptthat cannotbe turnedoff by theprogrammer.

instructionit isexecuting

NMI

causes aconditionaltransfer ofcontrolSoftwareinterrupts

Causes anconditionaltransfer ofcontrolExecute aninstructionfrom memorylocation20h

RST 6

softwareinterrupts



IncrementSP by 2 &push a word

to stackNon-Maskableinterruptsexecute aninstructionfrom memorylocation20H

B

Start

Aninterruptthat canbe turnedoff by thesystem.

macro itisexecuting

RTS 7.5

modifiesthe statusregister

Hardwareinterruptsand

SoftwareinterruptsModifiesthe Statusregister

Executes aNOP

RST 6.5

Hardware &softwarenterruptsMacro itisexecuting

macro itisexecuting

DecrementSP by 2 &push a AL

to stacknone ofthe above

executes aNOP

C

Aninterrthatcannotturnedby thesystemsubrouit isexecut

RST 5.

is an instrun

none othe ab

Is an instrun

None othe ab

INTR

None othe ab

Subrouit isexecut

subrouit isexecut

Illega

none othe ab

D


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43617

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Tpc

1

1

1

1

1

1

1

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2

2

2

2

2

2

2

1

1

1

Mrk

C

B

A

A

D

D

C

C

B

A

C

B

A

C

D

B

C

C

Ans

DMA stands for

In RST interrupts, RST stands for

Which interrupt has the highestpriority?An assembly language instruction

An interrupt instruction

Programs are written in assemblylanguage because they

Interrupts are classified as

The Interrupt vector table in 8086is stored sequentially from------to ------ h.NMI interrupt is of ------ typewhile INT instruction is ----------

- type of interrupt.Divide by zero interrupt is of ------ type while single step interruptis of ----------- typeThe interrupt vector table in 8086is stored sequentially from ------to ------ H8086 supports ------ number ofinterrupts and ------- locationsare reserved for interrupt vectortable.INTR interrupt is ---------interrupt and has -------- types.

PUSH operation --------- the SP by

----------- bytes.Registers --- and ----- are usedfor accessing stack elements80286 having physical memory

Operating system extensions arehaving ------- privilage level.In 80286, the size of segmentdescriptor cache register assignedto each of the segment is ------byte.

Qstn

INTA signal

Direct MemoryAllocation

Repeat StartTestNMI

always has alabel

causes anunconditionaltransfer ofcontrolrun fasterthan High-levellanguage

Hardwareinterrupts

0000,0000 to0000,003F

1,2

0,1

0000:0000 to0000:003F

128, 1024

Maskable, 255

increment, 1

CS,SS

1MByte

0

4

A

DistinctMemoryAllocationRestart

RST 6

alwaystakes at

least oneoperandcauses aconditionaltransfer ofcontrolareportable

Softwareinterrupts

0000,0000to0000,033F2,3

1,2

0000:0000to0000:033F255, 1024

Maskable,64

increment,

2CS,IP

16 M Byte

1

5

B

DirectMemoryAccessStart

RST 6.5

always hasan

operationfieldmodifiesthe statusregister

easier towrite thanmachinecodeprograms

HardwareinterruptsandSoftwareinterrupts0000,0000to0000,03FF3,4

0,2

0000:0000to0000:03FF255, 255

Non-Maskable,64decrement,

2SS,IP

24M Byte

2

6

C

DistinMemoryAccess

INTR

alwaysmodifi

the stregistis an instrun

they atheprograaccessregistorinstruns thaare no

usuallprovidby a Hlevelnone othe ab

None othe ab

1,4

0,3

None othe op

64, 64

Non-Maskab255decrem

1SS,SP

32 M B

3

8

D


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43617

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5

5

5

5

5

5

5

5

5

Tpc

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

2

2

2

2

2

2

Mrk

B

A

B

D

D

C

A

B

D

C

D

A

D

C

B

A

B

C

A

B

A

B

A

B

B

A

A

D

D

A

Ans

The 80286 supports -------- typesof descriptor tables.After reset, 80286 starts executionin --------- adress mode.

The flag useful to switch the 80286from real mode to protected mode is80286 processor consists offollowing modes.Application services are having ------- privilage level.Base address of Segment in PVAMmode of 80286 isIf TI=0 The descriptor tableselected isIn 80286 the size of segmentregister is ofAfter reset the first instructionfeched by 80286 is from addressPhysical memory of 80286 in PVAMmodeStack registers of 80287 is of

In 80386 processor the size of allgeneral purpose register is ofIn protected addressing modeof

80386 the size of all segmentreguster is ofBase address of segment in PVAMmode of 80286 isHow many Global Descriptors can bestored in GDT.Operating system routines arehaving ------ privilege levelThe flag useful to switch the 80286from real mode to protected mode isIn 80286 the size of segmentdescriptor cache register assignedto each of te segment is ----- byteIn real mode 80386 address upto

physical memoryHow many Global Descriptors can bestored in GDTOperating system routines arehaving ------- privilage level.System sevices routines are having------- privilage level.In real mode 80386 address up tophysical memory.In 80286 CPU, the address bus is of------ bit and can address ------MB of memory.In 80286, size of base and limitfield in segment descriptor isIn real address mode of 80286,

memory address range reserved forsystem initialization isIn real address mode of 80286,memory address range reserved forinterupt vector table isThe MSW od 80286 consist offollowing flags.The MSW od 80286 consist offollowing flags.80286 consist of ----- segment

Qstn

1

real

VM

Real mode

0

20 bit

GDT

32 bit

FFFFFF

64 KB

7 bytes

32 bits

32 bits

20 bit

4K

0

VM

4

1Mb

4K

0

0

1 MB

24, 32

16 bits & 32bitsFFFF0H to

FFFFFH

00000H to003FFH

P,C

AC,C

4,16

A

2

protected

PE

protectedmode1

32 bit

LDT

16 bit

0FFFFF

4 GB

4 bytes

16 bits

24 bits

32 bit

8K

1

PE

5

4Mb

8K

1

1

4MB

24,16

16 bits &24 bits00000H to

003FFH

00100H to003FFH

P,EM

AC,PE

8,16

B

3

virtualaddress

CY

Virtual

2

24 bit

GDT& LDT

24 bit

F00000

16 MB

6 bytes

24 bits

20 bits

24 bit

64K

2

CY

6

1Gb

64K

2

2

1GB

32,32

24 bits &24 bitsFFF00H to

FFFFFH

01000H to003FFH

P,TS

AC,MP

6,16

C

4

none othe a,c.OE

real &protec3

16 bit

NONE Oa,b &c8 bit

FFFFF0

1GB

8 byte

20 bit

16 bit

16 bit

1M

3

OE

8

16Mb

1M

3

3

16MB

32,16

16 bit16 bitFFFF0

FFFFFH

00000002FFH

PE,MP

PE,MP

8,32

D


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43617

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Tpc

2

2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Mrk

B

D

C

C

D

C

C

C

B

C

B

B

D

B

C

A

D

B

A

C

D

B

A

B

B

C

Ans

registers and size of each registeris ----- bit.80286 consist of ----- generalpurpose registers and size of eachregister is ----- bit.80286 consists of ----- generalpurpose registers & size of eachregister is ----- bitIn 80386 maximum size of each pagecan beThe 80386 enters into virtual 8086mode when ______ flag is setWhich register in 80386 is used aspage directory physical baseaddress registerThe on chip cache in 80486 is usedto store80386 supportoverall_____addressing modes tofacililtate efficient execution ofhigher level language programshe 80386 enters into virtual 8086mode when ------- flag is setIn 80386, GDTR and IDTR are calledas -------------- registers

In 80386, LDTR and TR are called as-------------- registersThe 80386 utilizes the -----------types of descriptor tables.The 80386 supports -------- typesof descriptors.Which register in 80386 is used aspage directory physical baseaddress register.Physical memory of 80386 in PVAMmode isSize of Cache memory in 80486 isofsize of instruction queue in 80486isThe pins used in bank selection of80486 areThe 80486 can handle ---------number of hardware interrupts.After reset, 80486 starts executionin --------- adress mode.The on-chip cache in 80486 is usedto store80386 having Instruction queue ofsize80386 addresses ______ bytes ofVirtual Memory through its MemoryManagement unitThe Cache inside 80486 is ------

KbytesSegmentation unit allows segmentsof _____ size at maximum.The ___ bit decides whether it is asystem descriptor or code/datasegment descriptor80386 support overall ___addressing modes to facilitateefficient execution of higher

level language programs.

Qstn

4,16

4,16

1 KB

Carry

cr0

code

9

Carry

address

address

2

4

CR0

1 GB

4K

32 bytes

DP0 to DP3

128

Real

Code

6 Byte

64 GB

8

4Gbytes

P

9

A

8,16

8,16

2KB

Trap

cr1

data

10

trap

systemaddress

systemaddress3

5

CR1

4 GB

16K

16 bytes

BREQ

256

Protected

data

4 Byte

64 TB

16

6Mbytes

S

10

B

6,16

6,16

4KB

Virtual

cr2

code &data11

virtual

system

systemsegment4

6

CR2

16 KB

8K

6 bytes

BRDY

16K

Virtual

Code anddata32 Byte

4 GB

32

4Mbytes

D

11

C

8,32

8,32

8KB

Overfl

cr3

code odata12

overfl

segmen

segmen

5

8

CR3

2 GB

10K

4 byte

BE0 to

512

Virtua8086code odata16 Byt

16 GB

64

6Gbyte

G

12

D


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43617

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7

Tpc

1

1

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

1

1

1

1

Mrk

C

C

C

C

B

D

B

C

B

B

C

B

C

A

A

A

D

A

D

B

B

A

C

Ans

In 80386, the maximum size ofsegment can beIn 80386, the maximum size of eachpage can beIn 80486 the pin is used to clearthe content of cache isThe 80386 CPU can support --------number of segmnets and each segmentsize is ------The 80386 have ------ controlregisters and size of each registeris ------- bits.The 80386 consist of ----------debug registers and ---------- testregisters.The 80386 descrptors have a ------bit segment limit and -------- bitsegment address.In 80486 the pin used to clear thecontent of cache isError of FPU unit in 80486 isindicated by ----- pin.The first processor to includeVirtual memory in the Intelmicroprocessor family was:

To access any segment in 80386privlage rule isIf ______input pin of 80386 isactivated, it allows addresspipelining during 80386 bus cycles.Virtual Mode Flag bit can be setusing ____ instruction or any taskswitch operation only

in the _____ modeThe interrupt vector table of 80386has been allocated ______ spacestarting from _______

to _______._____is used to control the cachewith two new control bits notpresent in the 80386

Microprocessor. What are thebits used to control the 8K bytecache?To prevent another master fromtaking over the bus during acritical operation, the 486

can assert its _____signal.The execution unit of 80386 consistof ----- general purpose and ------special purpose registers.With ----- bit address bus, 80386can address upto -------- of thephysical memory.

The size of flag register in 80386is ----- bit and reseved bits inflag register are always set toThe number stages in FPU pipelineof pentium areThe memory data bus width is ---------- in PentiumIn pentium, Compare instructionsare executed byIn pentium, Square root

Qstn

1GB

1KB

KEN

12K, 4GB

4,32

8,3

32,32

KEN

KEN

8086

CPL=DPL

BS16

IRET, Virtual

1Kbyte,00000H,003FFH

CR0, CD, NW

LOCK# orPLOCK#

8,6.

32,4GB

16,0

4

32 b

FADD

FADD

A

2GB

2KB

FERR

16K, 2GB

3,32

8,4

20,32

FERR

FERR

80286

CPLDPL

PEREQ

IRET,protected

3Kbyte,01000H,007FFH

CR0, PWT,PCD

HLDA

6,6.

32,4MB

16,1

5

128b

FDD

FDD

C

8GB

8KB

FADS

16K,8G

2,16

8,2

24,16

FADS

AHOLD

80486

none

ADS

POPF,protec

4Kbyte01000H009FFH

none

HOLD

8,8.

32,32M

32,1

6

256b

FEXP

FEXP

D


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43617

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7

Tpc

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

2

2

2

2

2

Mrk

D

B

D

C

A

B

D

A

A

B

D

B

D

B

B

C

D

C

D

C

D

B

C

D

A

Ans

instructions are executed by

MMX architecture is most sutaibleforThe sizes of level 2 cache in P-IIIprocessor isThe operating frequency of P-IIIprocessor is

The speed of pentium-pro processor

is ------ times that of pentium.RAT translates ------ registerreference to -------- register.Multiple instructions are issuedfor execution at run time by

The performnace of pentium isimproved because of it's

The use of BTB improves theperformance of the pentium byFYL2X calculates

SIMD type architecture perform ------- operation on ------ dataIn pentium, number of registersavailable for MMX programmer areInstruction EMMS implies

The performance of Pentium isimproved because of its

The number stages in FPU pipelineof Pentium areSIMD type architecture perform_____operation on_______Pentium Pro rocessor uses_____stages pipeline

MMX architecture is most suitableforPentium-pro processor uses -----stages pipeline.Pentium-Pro implements speculativeinstruction execution by lookingahead forPentium-pro processor uses dualindependent bus for simultaneousaccess ofThe sizes of code cache and datacache in pentium processor areThe number of entries that BTB inPentium can hold isFPATAN calculates -------- of Xwhere X is --------

For multimedia application, X-86CPU can manipulate ----- pixels ata time while MMX architectureallows manipulation of -------pixels at a time.The number of integer pipelines inpentium processor are ------- and

Qstn

2D imaging

256 KB

450 MHz

same

Logical,physicalVLIWarchitcture

superscalararchitecture

25%

Y*log2X

different,single2

Load MMXstacksuperscalararchitecture

4

Different,Single8

2D imaging

8

10-20instructions

main memory,virtualmemory8K,4K

128

tan, angle

2,8

2,4

A

3D imaging

512 KB

500 MHz

1.5

physical,logicalsuperscalararchitecturemassivepipelining

28%

Y*log2(X+1)

same,multiple4

Empty MMXstackMassivepipelining

8

Same,multiple10

3D imaging

10

15-25instructionsmainmemory, RAM

8K,16K

256

arctan,angle

4,8

1,4

B

Speechprocessing128 KB

550 MHz

2

logical,logical

on-chipFLU

23%

arctan(X)

same,single6

Load MMXregisteronchip FLU

5

Same,single12

Speechprocessing12

25-35instructionsmainmemory,CACHE4K,4K

512

arctan,floating-pointnumber4,4

2,3

C

2D andimagin64 KB

Alloptionareapplic2.5

physichysica

Alloptionareapplic45%

2x-1

differmultip8

Empty registAlloptionareaaplic6

differmultip16

2D & 3imagin16

20-30instrunsNo anyoptionapplic8K,8K

64

tan,floatipointnumber1,8

2,2

D


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43617

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8

8

8

8

8

8

8

Tpc

2

2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Mrk

B

D

A

D

B

A

C

B

B

B

C

A

B

D

A

D

C

D

B

C

A

Ans

each pipeline has ------- stages.

The number of entries that BTB inpentium can hold isIn pentium, which of the followingfloating point exception can bedetected even before actualfloating point calculationExecution trace cache of Pentium4can store upto______ decoded microoperation

RAT (Register Alias table) is partof processorOn chip multiprocessing switchesthe ----------- processsors betweendifferent process threadsTime slice multithreading switchesthe ----------- processsors betweendifferent process threadsIA-32 architecture's pagingmechanism includes extention PSE toaddress physical address spacegreater than --------- bytes.IA-32 architecture's pagingmechanism includes extention PAE toaddress physical address space

greater than --------- bytes.The function of InstructionScheduling in P4 is to scheduledifferent ----------- to anappropriate execution engine.The P4 BHT can hold maximum --------- entries.The P4 has a minimum loss of ----clock cycles if branch predictionis not correct.The Micro-Code ROM in Pentium-4consist of ---------

In case Trace cache miss, theinstructions are fetched from --------- cache in Pentium-4.The Trace Cache in Pentium-4 doesnot store -----

The role of______is to decodeinstruction & translate it intomicrooperation

Pentium4 processor is designedwith______ architecturePentium pro processor is designed

with ------- architecturePentium-4 processor is designedwith ------- architectureClock speed of Pentium-4 variesfromThe pipeline depth in Pentium-4processor extends upto ------stagesExecution trace cache of Pentium-4can store upto ----- decoded micro-

Qstn

128

Divide byzero

12000

Pentium-I

single

single

4K

4K

Instructions

2000

20

Micro-opeartions ofcomplexinstruction

Level-1

instruction

IA 32instructiondecoder

MII

MII

MII

1.3 GHz to1.6 GHz4

12000

A

256

Denormaloperand

10000

Pentium-II

two

two

4G

4G

micro-operations

4000

18

Micro-opeartionsof simpleinstruction

Level-2

code

Trace cache

VLIW

VLIW

VLIW

1.4 GHz to1.7 GHz15

10000

B

512

Invalidoperation

256

Pentium-IIIthree

three

4M

4M

data

8000

19

Micro-opeartionsofinstructio

nLevel-3

Data

Micro codeROM

P6MICRO

P6 micro

P6 micro

1.1 GHz to1.6 GHz20

256

C

64

Alloptionareapplic512

Pentiu

four

four

4

4

tasks

1000

10

Data

Level-

AlloptionareapplicAlloptionareapplicNET bu

Net Bu

Net Bu

1.5 GH1.6 GH8

512

D


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43617

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8

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8

8

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8

Tpc

1

1

1

2

2

2

2

2

2

2

2

2

2

2

2

1

1

Mrk

B

A

D

B

B

B

B

A

B

A

B

C

A

A

C

A

A

Ans

ops.

Basic integer instructions such asAdd, subtract etc. are get executedon Pentium-4 in ------ clockcycles.The role of ------- is to decodethe instruction and translate it tomicro-operations.

In case of Pentium-4, the

instruction is called as complex ifit is required to be translatedinto more than --------- micro-operations.Static prediction scheme works wellin P4 for ------- branches but itsperformance is get degraded for ----- branches.SSF2 instructions can perform -------- bit SIMD integer arithmetic and-------- bit SIMD double-precisionfloating-point operations.P4 connsist of ----- ALUs, --------AGUs and they operate at ---------times faster than processor.

Pentium-4 consists of L1 data cacheof size ------ KB and L2-cache ofsize ------- KB.Hyperthreading executes multiplethreads on --------- processors ------------ switching.Pentium4 consistes of L1 data cacheof size______ KB & L2 cache ofsize______ KBThe function of Trace cache inPentium-4 is to store ---- and itcan store maximum ---------

Each logical processor in P4 canuse upto maximum of ----------- re-order buffer entries, --------buffers and ------ store bufferentries.P4 supports ------ number oflogical processors and each logicalprocessor has its own set of two -------- byte streaming buffers.Multiple number of threads ----------the performance and -----------time in context switching.The cache integrated in the chip iscalled as ----- level cache whilecache external to chip is called as

----- level cacheThe register rename logic in P4allows -------- general use IA-32registers to be dynamicallyexpanded to use the available --------- physical registers.MII microprocessor are capable ofissueing multiple instructions persingle processor cycleContext of the process reflects all

Qstn

1

IA-32InstructionDecoder

6

Forward,Backward

80,16

1,1,2

128,256

single,without

128,256

Micro-operation, 12K micro-operations

24,12,63

4,128

Increases,Increases

L1,L2

4,128

TRUE

TRUE

A

0.5

Trace Cache

7

Backward,Forward.

128,128

2,2,2

8,256

single,with

8,256

Instruction, 12Instruction

63,24,12

2,128

Increases,Decreases

L2,L3

4,64

FALSE

FALSE

B

1.5

Micro-CodeROM

5

64,64

2,2,3

256,256

two,without

256,256

Micro-operation,1 K micro-operations

12,24,63

2,64

Decreases,Increases

L1,L3

8,128

C

2

Alloptionareapplic4

64,128

1,2,2

512,25

two, w

512,25

Micro-operat11 Kmicro-operat

10,20,

2,32

DecreaDecrea

L1,L4

8,64

D


18/18

43617

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8

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Tpc

1

1

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Mrk

B

A

A

Ans

the information that describes thecurrent state of the processcompletely.The scheduler selects the micro-opeartions based on wheather theybelong to one logical processor orthe other.The scheduler selects the micro-opeartions based on dependentinputs and availability ofexecution resources..8088 microprocessor accepts theprogram written for 8086 withoutany changes?

Qstn

TRUE

TRUE

Yes

A

FALSE

FALSE

No

B

C

D

advanced micro 2

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